公开(公告)号：US6073856A

公开(公告)日：2000-06-13

申请号：US146536

申请日：1998-09-03

Applicant: Norio Takahashi

Inventor： Norio Takahashi

IPC: G06K19/073 ,  G06K19/077 ,  H05K1/00 ,  H05K3/40 ,  G06K7/06 ,  G06K19/06

CPC classification number: G06K19/07749 ,  G06K19/073 ,  G06K19/07726 ,  H05K1/0293 ,  H01H2231/05 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/3025 ,  H05K1/0275 ,  H05K2201/0305 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/4084

Abstract: A noncontact IC card is provided with an antenna coil, an IC chip and a short-circuiting circuit formed on a base card. The noncontact IC card is kept inoperative unless the short-circuiting circuit is opened and the noncontact IC card is rendered operative when the short-circuiting circuit is opened. The short-circuiting circuit is formed to extend across a main part and a removable identification part included in the base card. The short-circuiting circuit can be opened by removing the identification part from the base card.

Abstract translation: 非接触IC卡设置有形成在基卡上的天线线圈，IC芯片和短路电路。 非接触式IC卡不起作用，除非短路电路断开，并且当短路电路断开时非接触式IC卡工作。 短路电路形成为延伸穿过基座中的主要部分和可拆卸的识别部件。 通过从基卡中取出识别部件可以打开短路电路。

公开(公告)号：US6069407A

公开(公告)日：2000-05-30

申请号：US195349

申请日：1998-11-18

Applicant: Ahmad Hamzehdoost

Inventor： Ahmad Hamzehdoost

IPC: H01L23/31 ,  H01L23/498 ,  H05K3/34 ,  H05K3/40 ,  H01L23/52

CPC classification number: H01L23/49833 ,  H01L23/3128 ,  H05K3/3436 ,  H01L2224/05599 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H05K2201/0305 ,  H05K2201/10666 ,  H05K3/4046 ,  Y02P70/613

Abstract: A die-up configuration includes a rigid circuit board with electrically conductive plated-through holes formed therethrough and an integrated-circuit die mounted to the upper surface of which a flexible insulated tape layer is fixed to the upper surface of a rigid circuit board and which has a number of wire-bonding sites. Conductive vias or plated-through holes are provided for connecting the wire-bonding sites on the upper surface of the flexible insulated tape layer to the contact areas formed on the lower surface of the flexible insulated tape layer. Conductors are provided for connecting respective contact areas on the lower surface of the flexible insulated tape layer to solder balls on the bottom of the rigid circuit board.

Abstract translation: 裸芯片配置包括刚性电路板，其具有穿过其中形成的导电电镀通孔，以及安装到其上表面的集成电路裸片，柔性绝缘带层固定到刚性电路板的上表面， 具有多个引线接合点。 提供导电通孔或电镀通孔，用于将柔性绝缘带层的上表面上的引线接合位置与形成在柔性绝缘带层的下表面上的接触区域相连接。 提供导体，用于将柔性绝缘带层的下表面上的各个接触区域连接到刚性电路板底部的焊球。

公开(公告)号：US6016005A

公开(公告)日：2000-01-18

申请号：US21050

申请日：1998-02-09

Applicant: Mario J. Cellarosi

Inventor： Mario J. Cellarosi

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/03 ,  H05K3/28 ,  H05K3/46 ,  H01L23/06 ,  H01L23/10 ,  H01L23/15

CPC classification number: H01L23/49833 ,  H01L21/4857 ,  H01L23/5385 ,  H05K3/4629 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/0305 ,  H05K2201/09063 ,  H05K2203/1147 ,  H05K3/28 ,  H05K3/4638

Abstract: A multilayer micro circuit module, and the method of manufacturing same, comprises a number of green sheets of ceramic material which are sintered before any other fabrication steps are undertaken. The sintered sheets are then formed with registration holes and via, and an electrically conductive pattern formed of a noble metal or copper is deposited onto one or both major surfaces of each sintered sheets. The sintered sheets are stacked one on top of the other to form a stack whose exterior surface is coated with a sealing material such as solder or glass and then fired at a temperature less than the melting point of a metal forming the conductive patterns so that the interior of the stack including the conductive patterns is substantially isolated from contaminants.

Abstract translation: 多层微电路模块及其制造方法包括在进行任何其它制造步骤之前烧结的许多生坯的陶瓷材料。 然后烧结的片材形成有配准孔和通孔，并且由贵金属或铜形成的导电图案沉积在每个烧结片材的一个或两个主表面上。 烧结片层叠在一起而形成堆叠，其外表面涂覆有诸如焊料或玻璃的密封材料，然后在小于形成导电图案的金属的熔点的温度下烧制，使得 包括导电图案的叠层的内部基本上与污染物隔离。

公开(公告)号：US6003225A

公开(公告)日：1999-12-21

申请号：US982012

申请日：1997-12-01

Applicant: Sunghee Yoon

Inventor： Sunghee Yoon

IPC: H05K3/06 ,  H05K3/42 ,  H05K3/44 ,  H05K3/10

CPC classification number: H05K3/062 ,  H05K3/44 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K3/427 ,  Y10T29/49165

Abstract: A printed wiring board has an aluminum backing, a dielectric layer overlying the aluminum backing, and a copper layer overlying the dielectric layer. Holes are drilled through the copper and the dielectric layers, and either partially or fully through the aluminum backing, and plated to provide a conductive path between the copper layer and the aluminum backing. Tin-lead traces are applied to the upper surface of the copper layer and the copper layer is etched to define conductive paths. The copper exposed and aluminum exposed surfaces are protected so as to permit processing of the printed wiring board in otherwise-incompatible etchants and other solutions.

Abstract translation: 印刷电路板具有铝背衬，覆盖在铝背衬上的电介质层和覆盖在电介质层上的铜层。 孔穿过铜和电介质层，并且部分或完全穿过铝背衬，并被电镀以在铜层和铝衬垫之间提供导电路径。 锡引线迹线被施加到铜层的上表面，并且铜层被蚀刻以限定导电路径。 铜暴露和铝暴露表面被保护，以便允许在其它不相容的蚀刻剂和其它溶液中处理印刷线路板。

公开(公告)号：US5939969A

公开(公告)日：1999-08-17

申请号：US920916

申请日：1997-08-29

Applicant: Bernhard E. Doerrwaechter ,  Keck C. Pathammavong ,  Kurt M. Krachenfels

Inventor： Bernhard E. Doerrwaechter ,  Keck C. Pathammavong ,  Kurt M. Krachenfels

IPC: H01H37/76 ,  H02H9/04 ,  H05K1/00 ,  H05K1/09 ,  H05K3/34 ,  H01H85/046 ,  H01H85/04

CPC classification number: H01H37/761 ,  H05K1/0293 ,  H01H2037/046 ,  H01H2037/768 ,  H02H9/042 ,  H05K1/092 ,  H05K2201/0305 ,  H05K2201/10181 ,  H05K2201/10992 ,  H05K3/3463

Abstract: A preformed thermal fuse comprising two electrodes, first and second layers of solder, and a conductive bridge comprising a non-paste solder material is disclosed. The conductive bridge has a melting temperature which is substantially equivalent to the predetermined actuation temperature of the fuse. The melting temperatures of the first and second layers of solder are selected to allow reflow soldering of the device.

Abstract translation: 公开了一种包括两个电极，第一和第二焊料层以及包括非糊焊料材料的导电桥的预成型热熔丝。 导电桥具有基本上等于保险丝的预定操作温度的熔化温度。 选择第一和第二层焊料的熔化温度以允许器件的回流焊接。

公开(公告)号：US5808351A

公开(公告)日：1998-09-15

申请号：US320145

申请日：1994-10-07

Applicant: Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd

Inventor： Richard J. Nathan ,  James J. D. Lan ,  Steve S. Chiang ,  William H. Shepherd

IPC: G01R1/04 ,  G01R1/06 ,  G01R31/28 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01R29/00 ,  H01R31/06 ,  H05K1/00 ,  H05K1/14 ,  H05K1/16 ,  H05K3/06 ,  H05K3/24 ,  H05K3/42 ,  H05K3/46 ,  H05K7/10 ,  H01L29/12

CPC classification number: G01R1/04 ,  H01L21/485 ,  H01L23/49827 ,  H01L23/5382 ,  H01R29/00 ,  H05K1/0293 ,  H05K7/1092 ,  G01R1/06 ,  G01R31/2863 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01R23/70 ,  H01R31/06 ,  H05K1/0289 ,  H05K1/029 ,  H05K1/0292 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/167 ,  H05K2201/0305 ,  H05K2201/09763 ,  H05K2201/10181 ,  H05K2201/10212 ,  H05K2201/10689 ,  H05K2203/0542 ,  H05K2203/105 ,  H05K2203/1115 ,  H05K2203/173 ,  H05K2203/175 ,  H05K3/062 ,  H05K3/243 ,  H05K3/429 ,  H05K3/4611

Abstract: Two types of programmable elements, fuses and antifuses, are disclosed for forming an electrically programmable burn-in board in one embodiment and an electrically programmable device-under-test (DUT) card in another embodiment. Both types of programmable elements can also be used in a reconfiguration device for interconnecting electrical contacts in a first configuration to electrical contacts in a second configuration. The various embodiments of this invention include, for example, a component socket, a socket adapter, a cable, a cable adapter, a scrambler card for a burn-in board and a device-under-test card for a burn-in board. A method for forming a fuse is also disclosed.

Abstract translation: 公开了两种可编程元件，熔丝和反熔丝，用于在一个实施例中形成电可编程老化板，以及另一实施例中的电可编程器件测试（DUT）卡。 两种类型的可编程元件也可用于重构装置中，用于将第一配置中的电触点与第二配置中的电触点相互连接。 本发明的各种实施例包括例如组件插座，插座适配器，电缆，电缆适配器，用于老化板的加扰器卡和用于老化板的测试用设备卡。 还公开了一种用于形成熔丝的方法。

公开(公告)号：US5748450A

公开(公告)日：1998-05-05

申请号：US636441

申请日：1996-04-23

Applicant: Young-Gon Kim ,  Dong-You Kim

Inventor： Young-Gon Kim ,  Dong-You Kim

IPC: H05K1/00 ,  H05K3/00 ,  H05K3/22 ,  H05K3/34 ,  H05K7/10 ,  H05K7/02 ,  H01R9/09

CPC classification number: H05K3/225 ,  H05K3/3436 ,  H05K7/1061 ,  H05K1/0293 ,  H05K2201/0305 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0126 ,  H05K2203/041 ,  H05K2203/173 ,  H05K3/0047 ,  H05K3/3484 ,  Y02P70/613

Abstract: In a BGA package having electrically connected active balls and electrically disconnected dummy balls, the active balls are positioned in a radial direction at intervals of 90.degree. around the dummy balls. When a defect occurs in a solder joint, the package can be easily repaired by finding defective active ball; forming a repair hole by using a cutting means at a predetermined portion of the printed circuit board corresponding to a central position between the dummy ball and the defectively soldered active ball; inserting a solder paste injector into the repair hole to inject solder thereinto; and mutually connecting pad extensions of the dummy ball and the defective active ball with the injected solder. Therefore, the overall process can be simplified and its reliability can be improved.

公开(公告)号：US5573632A

公开(公告)日：1996-11-12

申请号：US460885

申请日：1995-06-05

Applicant: Masakazu Shimizu ,  Hiroshi Shimamura ,  Hidetaka Kumota

Inventor： Masakazu Shimizu ,  Hiroshi Shimamura ,  Hidetaka Kumota

IPC: H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  B32B31/12 ,  B32B31/14

CPC classification number: H05K3/0014 ,  H05K3/385 ,  H05K3/4652 ,  H05K2201/0305 ,  H05K2203/0228 ,  H05K2203/0315 ,  H05K2203/063 ,  H05K2203/1105 ,  H05K2203/1157 ,  H05K2203/302 ,  H05K3/0044 ,  H05K3/4038 ,  H05K3/4069 ,  Y10S428/901 ,  Y10T428/24777 ,  Y10T428/24802 ,  Y10T428/24843 ,  Y10T428/24851 ,  Y10T428/24917 ,  Y10T428/31678

Abstract: In a multilayer printed-circuit substrate comprising a plurality of insulating resin layers, a plurality of metal-made electrically conductive circuits respectively laminated between the insulating resin layers and on the upper surface of the uppermost-positioned insulating resin layer and electrically conductive portions for respectively electrically connecting adjacent upper- and lower-positioned conductive circuits to each other, the insulating resin layers except at least the lowest-positioned insulating resin layer have flexibility, and blackening-treated films prepared by applying blackening treatment to the surface of the respective electrically conductive circuits are respectively provided between the upper surfaces of the conductive circuits and the insulating resin layers laminated thereon.

Abstract translation: 在包括多个绝缘树脂层的多层印刷电路基板中，分别层叠在绝缘树脂层之间和分别位于最上位绝缘树脂层的上表面上的多个金属制导电电路和分别用于导电部分的导电部分 将相邻的上下导电电路彼此电连接，除了至少最低定位的绝缘树脂层之外的绝缘树脂层具有柔性，并且通过将黑化处理施加到各导电表面上而制备的黑化处理膜 电路分别设置在导电电路的上表面和层叠在其上的绝缘树脂层之间。

公开(公告)号：US5567648A

公开(公告)日：1996-10-22

申请号：US552430

申请日：1995-11-03

Applicant: Debabrata Gupta

Inventor： Debabrata Gupta

IPC: H01L21/48 ,  H01L21/60 ,  H05K3/34 ,  H01L21/283

CPC classification number: H01L24/11 ,  H01L21/4853 ,  H05K3/3478 ,  H01L2224/13099 ,  H01L2924/00013 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H05K2201/0305 ,  H05K2201/10424 ,  H05K2201/10734 ,  H05K2203/043

Abstract: A method for forming conductive interconnect bumps, such as solder bumps, on bond pads on a substrate. The method includes conductive discs and a connecting member formed between two adjacent conductive discs. The discs and connecting member are then placed over the bond pads and heat is applied so that the conductive discs and the connecting member combine to form isolated interconnect bumps. A polymer backsheet is used for support.

Abstract translation: 一种用于在衬底上的接合焊盘上形成诸如焊料凸块的导电互连凸块的方法。 该方法包括导电盘和形成在两个相邻导电盘之间的连接构件。 然后将盘和连接构件放置在接合焊盘上，并施加热量，使得导电盘和连接构件组合形成隔离的互连凸块。 聚合物底片用于支撑。

公开(公告)号：US5560795A

公开(公告)日：1996-10-01

申请号：US232166

申请日：1994-08-02

Applicant: Helmut Bruckner ,  Siegfried Kopnick ,  Werner Uggowitzer

Inventor： Helmut Bruckner ,  Siegfried Kopnick ,  Werner Uggowitzer

IPC: H05K3/20 ,  H05K3/34 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46 ,  B32B31/18 ,  B32B31/20

CPC classification number: H05K3/4652 ,  H05K3/4084 ,  H05K2201/0305 ,  H05K2201/0355 ,  H05K2201/091 ,  H05K2203/033 ,  H05K2203/063 ,  H05K3/3447 ,  H05K3/4038 ,  Y10T156/1046 ,  Y10T156/1056 ,  Y10T156/109 ,  Y10T156/1093 ,  Y10T29/49155 ,  Y10T29/49167

Abstract: Producing a printed circuit board having at least two layers and having a carrier board, a first Conductor layer having contact areas and a second conductor layer having connecting areas, in which a conductive foil, provided with an adhesive coating, is laminated onto the carrier board having the first conductor layer and the contact areas, the adhesive coating an the conductive foal having holes which correspond with the contact areas of the first conductor layer. The perforated conductive foil, provided with the adhesive coating, is compressed and laminated with the carrier board having the first conductor layer, the contact areas of the first conductor layer being bulged at least partially through the holes in the adhesive coating in the direction of the surface of the connecting areas of the second conductor layer so that the surfaces of the contact areas are in each case at a distance from the surface of the connecting areas of the second conductor layer which is less than the thickness of the connecting areas. Subsequently, the second conductor layer having the connecting areas is produced from the conductive foil, the connecting areas of the second conductor layer bounding the holes in the adhesive coating, after which the contact areas of the first conductor layer can be electrically conductively connected to the corresponding connecting areas of the second conductor layer, through the holes in the adhesive coating.

Abstract translation: PCT No.PCT / EP92 / 02507 Sec。 371日期1994年8月2日 102（e）日期1994年8月2日PCT 1991年11月1日PCT PCT。 公开号WO93 / 09655 日期：1993年5月13日生产具有至少两层并具有载体板的印刷电路板，具有接触区域的第一导体层和具有连接区域的第二导体层，其中设置有粘合剂涂层的导电箔被层压 在具有第一导体层和接触区域的载体板上，粘合剂涂覆具有与第一导体层的接触面积相对应的孔的导电马俑。 设置有粘合剂涂层的穿孔导电箔被压缩并与具有第一导体层的载体板层压，第一导体层的接触区域至少部分地通过粘合剂涂层中的孔沿着 第二导体层的连接区域的表面，使得接触区域的表面在每种情况下距离第二导体层的连接区域的表面小于连接区域的厚度。 随后，具有连接区域的第二导体层由导电箔制成，第二导体层的连接区域包围粘合剂涂层中的孔，之后第一导体层的接触面积可导电地连接到 第二导体层的相应的连接区域，通过粘合剂涂层中的孔。