公开(公告)号：US07381098B2

公开(公告)日：2008-06-03

申请号：US11402544

申请日：2006-04-11

Applicant: Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

Inventor： Bernard Harold Hammond, Jr. ,  David Patrick Murray ,  Ian Robert George

IPC: H01R24/00

CPC classification number: H01R13/6466 ,  H01R4/2416 ,  H01R13/6658 ,  H01R13/719 ,  H01R24/64 ,  H01R2107/00 ,  H05K1/0228 ,  H05K1/162 ,  H05K3/4644 ,  H05K2201/09236 ,  H05K2201/09245 ,  H05K2201/09263 ,  H05K2201/10189 ,  Y10S439/941 ,  Y10T29/49117 ,  Y10T29/49204 ,  Y10T29/49222

Abstract: The present disclosure relates to a telecommunications jack including a housing having a port for receiving a plug. The jack also includes a plurality of contact springs adapted to make electrical contact with the plug when the plug is inserted into the port of the housing, and a plurality of wire termination contacts for terminating wires to the jack. The jack further includes a circuit board that electrically connects the contact springs to the wire termination contacts. The circuit board includes a multi-zone crosstalk compensation arrangement for reducing crosstalk at the jack.

Abstract translation: 本公开涉及一种电信插孔，其包括具有用于接收插头的端口的壳体。 千斤顶还包括多个接触弹簧，其适于当插头插入壳体的端口时与插头电接触，以及多个用于将插线端接到插座的导线终端触头。 千斤顶还包括将接触弹簧电连接到导线终端触点的电路板。 电路板包括用于减少插座处串扰的多区串扰补偿装置。

公开(公告)号：US20080062666A1

公开(公告)日：2008-03-13

申请号：US11893043

申请日：2007-08-13

Applicant: Myong-Bin Lim ,  Jae-Han Lee ,  Sun-Kyu Son ,  In-Yong Hwang

Inventor： Myong-Bin Lim ,  Jae-Han Lee ,  Sun-Kyu Son ,  In-Yong Hwang

IPC: G02F1/133 ,  H05K7/00

CPC classification number: H05K1/0216 ,  G02F1/13452 ,  H05K1/025 ,  H05K1/189 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09781 ,  H05K2201/10136 ,  H05K2201/10681

Abstract: A signal transfer member for a liquid crystal display (LCD) apparatus includes a power line for receiving power from an external source and for driving a semiconductor chip disposed on the transfer member or the display apparatus. The power line is bent so as to incorporate a serpentine structure, which enables the length of the power line to be easily adjusted and results in the line being longer than a power line formed with a relatively straight structure. Accordingly, the length of the power line can be adjusted to take into account the respective impedances of the chip and the external source so as to suppress electromagnetic waves in the power line. This prevents the creation of noise, distortion of signals, damage to the semiconductor chip, and disconnection of the input interconnection thereof that are caused by the electromagnetic waves, so that product yields are thereby improved.

Abstract translation: 用于液晶显示器（LCD）装置的信号传递部件包括用于从外部源接收电力并用于驱动设置在转印部件或显示装置上的半导体芯片的电力线。 电力线被弯曲以包括蛇形结构，这使得能够容易地调节电力线的长度，并且导致线比形成有相对直的结构的电力线更长。 因此，可以调整电力线的长度以考虑芯片和外部源的各自的阻抗，以便抑制电力线中的电磁波。 这防止了由电磁波引起的噪声，信号失真，半导体芯片的损坏和输入互连的断开，从而提高了产品的产量。

公开(公告)号：US07343576B2

公开(公告)日：2008-03-11

申请号：US11304267

申请日：2005-12-14

Applicant: Gary A. Brist ,  Gary B. Long ,  William O. Alger ,  Carlos Mejia ,  Bryce Horine

Inventor： Gary A. Brist ,  Gary B. Long ,  William O. Alger ,  Carlos Mejia ,  Bryce Horine

IPC: G06F17/50

CPC classification number: H05K1/0366 ,  G06F17/5077 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/0248 ,  H05K2201/029 ,  H05K2201/09236 ,  H05K2201/09263

Abstract: A method and apparatus for reducing timing skew between conductor traces. A dielectric medium made of a resin reinforced with a fabric is provided. The fabric includes a first plurality of yarns running parallel to a first axis and a second plurality of yarns running parallel to a second axis. The first plurality of yarns are separated by a first weave pitch and the second plurality of yarns separated by a second weave pitch. At least two conductor traces are formed on the dielectric medium. The conductor traces are positioned on the dielectric medium such that the conductor traces each have substantially similar effective dielectric constants.

Abstract translation: 一种用于减少导体迹线之间的定时偏差的方法和装置。 提供由用织物增强的树脂制成的电介质。 织物包括平行于第一轴线延伸的第一组多根纱线和平行于第二轴线延伸的第二组纱线。 第一组多个纱线由第一编织间距分开，第二组纱线由第二编织间距分开。 在电介质上形成至少两根导体迹线。 导电迹线位于介电介质上，使得导体迹线各自具有基本相似的有效介电常数。

公开(公告)号：US07332818B2

公开(公告)日：2008-02-19

申请号：US11127160

申请日：2005-05-12

Applicant: Irving Memis

Inventor： Irving Memis

IPC: H01L23/538

CPC classification number: H05K1/181 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0248 ,  H05K2201/0784 ,  H05K2201/09227 ,  H05K2201/09263 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2224/0401

Abstract: An electronic package which includes a circuitized substrate having at least two electrical components positioned thereon. The package includes patterns of contact sites, each for having one of the components coupled thereto. The patterns of contact sites in turn are electrically interconnected by a grouping of conductive lines which, to substantially prevent skew, are of substantially the same length. A method of making the package is also provided, as is a circuitized substrate and an information handling system, the latter adapted for having one or more of the electronic packages as part thereof.

Abstract translation: 一种电子封装，其包括具有定位在其上的至少两个电气部件的电路化基板。 该包装包括接触部位的图案，每个接触部位具有与其耦合的部件之一。 接触部位的图案依次通过一组导线相互电连接，导线基本上防止偏斜具有基本上相同的长度。 还提供了制造包装的方法，电路化基板和信息处理系统也是如此，后者适于将一个或多个电子包装作为其一部分。

公开(公告)号：US07308670B2

公开(公告)日：2007-12-11

申请号：US11015219

申请日：2004-12-17

Applicant: Mickey Steven Felton

Inventor： Mickey Steven Felton

IPC: G06F17/50

CPC classification number: G06F17/5077 ,  H05K1/0248 ,  H05K1/18 ,  H05K3/0005 ,  H05K2201/09263

Abstract: Described is a system and method of designing a length of an electrical trace used to implement a point-to-point serial link for conveying a digital signal between a transmitter and a receiver. A trace segment of the electrical trace is identified. The trace segment has a first endpoint determined by a first impedance discontinuity on the point-to-point serial link and a second endpoint determined by a second impedance discontinuity on the point-to-point serial link. A restricted length is calculated for the trace segment based on a propagation delay of the signal along the trace segment and a frequency of the signal. A length of the trace segment is set to be unequal to the restricted length.

Abstract translation: 描述了一种设计用于实现用于在发射机和接收机之间传送数字信号的点对点串行链路的电迹线的长度的系统和方法。 识别电迹线的痕迹段。 跟踪段具有由点对点串行链路上的第一阻抗不连续性确定的第一端点和由点到点串行链路上的第二阻抗不连续性确定的第二端点。 基于沿着迹线段的信号的传播延迟和信号的频率，对跟踪段计算限制长度。 跟踪段的长度设置为不等于限制长度。

公开(公告)号：US07277104B2

公开(公告)日：2007-10-02

申请号：US10372039

申请日：2003-02-19

Applicant: Nigel Anthony Dickens ,  Adrian Christopher Dickens ,  Darrin Steel

Inventor： Nigel Anthony Dickens ,  Adrian Christopher Dickens ,  Darrin Steel

IPC: G09G5/10

CPC classification number: G06F3/023 ,  H04B3/40 ,  H04N7/108 ,  H04N9/64 ,  H04N17/00 ,  H05K1/0248 ,  H05K1/0298 ,  H05K2201/09263

Abstract: Devices for reducing and determining the skew between colour video signals transmitted over at least two different video cables are described. A KVM extender including such devices is also described. The skew reduction device includes a plurality of video signal transmission tracks selectably connectable to each of the video cables to increase the video signal transmission path length so as to more closely matching the total video signal path length for each of the colour video signals. The skew determination device comprises a processing device, a signal generator for applying measuring signals to each of the video signal cables and signal detection circuitry to receive measuring signals transmitted over the video signal cables. Detection signals are output to the processing device which is programmed to determine an indication of the transmission path length difference between the video signal cables.

Abstract translation: 描述用于减少和确定通过至少两个不同视频电缆传输的彩色视频信号之间的偏斜的装置。 还描述了包括这种设备的KVM扩展器。 歪斜减少装置包括可选择地连接到每个视频电缆的多个视频信号传输轨道，以增加视频信号传输路径长度，以便更加紧密地匹配每个彩色视频信号的总视频信号路径长度。 偏斜确定装置包括处理装置，用于向每个视频信号电缆和信号检测电路施加测量信号的信号发生器，用于接收通过视频信号电缆传输的测量信号。 检测信号被输出到被编程为确定视频信号电缆之间的传输路径长度差的指示的处理设备。

公开(公告)号：US20070216800A1

公开(公告)日：2007-09-20

申请号：US11691406

申请日：2007-03-26

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: H04N7/01

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

Abstract translation: 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US20070175023A1

公开(公告)日：2007-08-02

申请号：US11651817

申请日：2007-01-10

Applicant: Kjell Heitmann ,  Douglas Clark ,  Paul Perreault

Inventor： Kjell Heitmann ,  Douglas Clark ,  Paul Perreault

IPC: H05K3/30

CPC classification number: H01L23/576 ,  G06F21/87 ,  H01L2924/0002 ,  H05K1/0275 ,  H05K2201/09263 ,  H05K2201/10151 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A tamper protected printed circuit board assembly including a printed circuit board and a partially enveloping tamper wrap covering the entirety of the top surface of the printed circuit board and a first portion of the bottom surface of the printed circuit board, wherein a second portion of the bottom surface of the printed circuit board is not covered by the tamper wrap is provided. The printed circuit board includes two security trace layers each having two security traces thereon, preferably in a serpentine pattern. The tamper wrap and the security traces together cover and prevent tampering with the electronic circuitry of the printed circuit board.

Abstract translation: 一种防篡改印刷电路板组件，包括印刷电路板和覆盖印刷电路板的整个顶表面的部分包封的篡改包裹物和印刷电路板的底表面的第一部分，其中第二部分 印刷电路板的底面未被篡改包覆覆盖。 印刷电路板包括两个安全迹线层，每个安全迹线层具有两个安全迹线，优选地以蛇形图案。 篡改包装和安全踪迹一起覆盖并防止篡改印刷电路板的电子电路。

公开(公告)号：US20070156943A1

公开(公告)日：2007-07-05

申请号：US11685152

申请日：2007-03-12

Applicant: Haw-Jyh Liaw ,  David Nguyen

Inventor： Haw-Jyh Liaw ,  David Nguyen

IPC: G06F13/14

CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

Abstract: A memory system includes a controller chip and a memory module coupled to the controller chip. A signal line carries a signal that traverses the signal line until reaching a termination at an end of the signal line. A clock line carries a clock signal that traverses the clock line to reach a second termination at an end of the clock line. The module includes a first memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the first memory device at substantially the same time. The module includes a second memory device connected to the signal line and the clock line such that the signal and the clock signal arrive at the second memory device at substantially the same time and after the signal and the clock signal arrive at the first memory device.

Abstract translation: 存储器系统包括控制器芯片和耦合到控制器芯片的存储器模块。 信号线承载穿过信号线的信号，直到在信号线的末端达到终止。 时钟线承载穿过时钟线的时钟信号，以在时钟线的末端到达第二个终端。 模块包括连接到信号线和时钟线的第一存储器件，使得信号和时钟信号在基本相同的时间到达第一存储器件。 模块包括连接到信号线和时钟线的第二存储器件，使得信号和时钟信号在基本上相同的时间到达第二存储器件，并且在信号和时钟信号到达第一存储器件之后。

公开(公告)号：US07181837B2

公开(公告)日：2007-02-27

申请号：US10861847

申请日：2004-06-04

Applicant: Mark S. Johnson

Inventor： Mark S. Johnson

IPC: H05K3/02

CPC classification number: H05K3/242 ,  H05K3/0052 ,  H05K2201/09263 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The present invention relates generally to a plating buss design and method for minimizing short circuit problems in PCB panel singulation. More particularly, the invention encompasses a serpentine plating buss which increases the PCB singulation process window thereby minimizing short circuit problems due to indexing errors caused by occasional manufacturing and equipment alignment problems. The serpentine plating buss design therefore increases board yield.