公开(公告)号：US20060000636A1

公开(公告)日：2006-01-05

申请号：US10882167

申请日：2004-07-02

Applicant: John Lauffer ,  James Larnerd ,  Voya Markovich

Inventor： John Lauffer ,  James Larnerd ,  Voya Markovich

IPC: H05K1/03 ,  H05K3/46

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: A circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. A method of making the substrate, an electrical assembly utilizing the substrate, a multilayered circuitized assembly also utilizing the substrate and an information handling system, e.g., a mainframe computer, are also provided.

Abstract translation: 电路化基板，其包括多个邻接的开放段，其在导电层内限定面对的边缘部分，以隔离导电层的分离部分，使得该层可用于不同的功能，例如功率和接地元件内部的功能和接地元件 包括基板作为其一部分的产品（例如，电气组件）。 还提供了制造衬底的方法，利用衬底的电组件，还利用衬底的多层电路化组件和诸如主机的信息处理系统。

公开(公告)号：US20050205297A1

公开(公告)日：2005-09-22

申请号：US11142399

申请日：2005-06-02

Applicant: Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H05K1/09 ,  H01L21/4763 ,  H01L23/12 ,  H01L23/14 ,  H05K1/11 ,  H05K1/14 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board including a laminate of at least one insulating layer and at least one wiring layer. The wiring layer is formed by a composite member having a first metal layer and a second metal layer formed on one or both sides of the first metal layer. The first metal layer having a smaller coefficient of thermal expansion than the second metal layer. The second metal layer having a higher electric conductivity than the first metal layer. The insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer. A layer-to-layer interconnection portion is provided on the surface of the insulating layer and in the blind via-hole and is formed in the blind via-hole to be in contact with the surface of the second metal layer.

Abstract translation: 包括至少一个绝缘层和至少一个布线层的叠层的多层电路板。 布线层由具有形成在第一金属层的一侧或两侧上的第一金属层和第二金属层的复合构件形成。 第一金属层的热膨胀系数小于第二金属层。 第二金属层的导电率比第一金属层高。 绝缘层具有通过第二金属层的表面设置的底部的盲通孔。 在绝缘层的表面和盲通孔中设置层间互连部，并且形成在盲通孔中，与第二金属层的表面接触。

公开(公告)号：US20050195579A1

公开(公告)日：2005-09-08

申请号：US11120393

申请日：2005-05-02

Applicant: Weston Roth ,  Damion Searls ,  James Jackson

Inventor： Weston Roth ,  Damion Searls ,  James Jackson

IPC: H01L23/64 ,  H05K1/02 ,  H05K1/16 ,  H05K3/02 ,  H05K3/00 ,  B05D5/12 ,  B29B15/10 ,  C23C28/00 ,  H05K1/00

CPC classification number: H01L23/642 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/162 ,  H05K3/02 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2203/0315 ,  H05K2203/0796 ,  H05K2203/095 ,  H05K2203/1142 ,  H01L2924/00

Abstract: The invention relates to an apparatus and method for improving AC coupling between adjacent signal traces and between plane splits and signals spanning plane splits on circuit boards. A circuit board includes adjacent conductive means and an oxide means interposed there between. The oxide means is a copper oxide, e.g., cupric or cuprous oxide. In one embodiment, the adjacent conductive means are adjacent voltage reference planes with a split interposed between the conductive means. The copper oxide fills the split. In another embodiment, the adjacent conductive means are differential signal traces. The copper oxide fills a gap between the differential signal traces. The copper oxide is a non-conductive material with an increased dielectric constant as compared to other common dielectric materials used as fillers. The increased dielectric constant increases capacitance, in turn, increasing AC coupling.

公开(公告)号：US20050176380A1

公开(公告)日：2005-08-11

申请号：US11013337

申请日：2004-12-17

Applicant: Hiroshi Okabe ,  Hidetoshi Matsumoto

Inventor： Hiroshi Okabe ,  Hidetoshi Matsumoto

IPC: H01L25/00 ,  H04B1/38 ,  H04B1/40 ,  H05K1/00 ,  H05K1/02 ,  H05K1/18 ,  H05K3/34 ,  H05K3/46

CPC classification number: H04B1/38 ,  H01L2224/05554 ,  H01L2224/48227 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2924/15184 ,  H01L2924/15192 ,  H01L2924/19105 ,  H01L2924/30111 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/09972 ,  H01L2924/00

Abstract: An RF circuit module, in which a power amplifier and a transceiver are united, with reduced interference between its electronic circuit blocks, downsized and still having high performance, and with a stable performance not dependent on the ground land structure on the motherboard, is provided. The ground plane 110 for at least a last-stage amplifier 11 of the power amplifier 10 where the greatest power is generated in the whole RF circuit block, that is, the source of generating the greatest noise and heat for the RF circuit block, is isolated from the ground plane for at least one circuit portion of the transceiver 9 including an LNA 51, receiver 52, transmitter 30, and VCO 70. These ground planes are connected to a common ground plane 480 through different connection conductors, respectively.

Abstract translation: 提供了一种RF电路模块，其中功率放大器和收发器组合在一起，其电子电路块之间的干扰减小，尺寸小且仍然具有高性能，并且具有不依赖于主板上的地面结构的稳定性能 。 在整个RF电路块中产生最大功率的功率放大器10的至少最后一级放大器11的接地平面110，即产生RF电路块的最大噪声和热的源是 与收发机9的至少一个电路部分的接地平面隔离，包括LNA 51，接收机52，发射机30和VCO70。 这些接地层分别通过不同的连接导体连接到公共接地层480。

公开(公告)号：US06924707B2

公开(公告)日：2005-08-02

申请号：US09901746

申请日：2001-07-10

Applicant: Yoshinori Takahashi

Inventor： Yoshinori Takahashi

IPC: H01P7/08 ,  H03B5/18 ,  H05K1/00 ,  H05K1/02

CPC classification number: H01P7/082 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10075

Abstract: A resonator minimizes degradation of the Q factor, accurately adjusts the frequency, and reduces the size and profile thereof. A voltage controlled oscillator including such a resonator includes a multilayer substrate. The multilayer substrate includes a first grounding conductor layer, a first dielectric layer, a strip line layer, a second dielectric layer, a second grounding conductor layer, and a third dielectric layer. A strip line is disposed on the strip line layer, and a microstrip line is disposed on the third dielectric layer. The strip line is connected to the microstrip line via a through hole to define the resonator. A portion of the second grounding conductor layer that faces the microstrip line is removed.

Abstract translation: 谐振器使Q因子的劣化最小化，精确地调节频率，并减小其尺寸和轮廓。 包括这种谐振器的压控振荡器包括多层基板。 多层基板包括第一接地导体层，第一介电层，带状线层，第二介电层，第二接地导体层和第三介电层。 带状线设置在带状线层上，并且微带线设置在第三介电层上。 带状线通过通孔连接到微带线以限定谐振器。 面向微带线的第二接地导体层的一部分被去除。

公开(公告)号：US20050140458A1

公开(公告)日：2005-06-30

申请号：US11061910

申请日：2005-02-18

Applicant: Clifford Clark

Inventor： Clifford Clark

IPC: H05K1/02 ,  H01P3/08

CPC classification number: H05K1/0216 ,  H05K1/023 ,  H05K2201/09263 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10022 ,  H05K2201/10689

Abstract: A printed circuit board to electrically couple electrical components has non-conductive layers. Conductive planes are formed on the non-conductive layers. Conductive traces are formed on the non-conductive layer to provide signal paths for the electrical components. Delay devices coupled to the conductive traces to space apart signals so as to minimize electric field effects on nearby signals.

Abstract translation: 用于电耦合电气部件的印刷电路板具有非导电层。 导电平面形成在非导电层上。 导电迹线形成在非导电层上以提供用于电气部件的信号路径。 延迟器件耦合到导电迹线以使信号间隔开，以便最小化对附近信号的电场效应。

公开(公告)号：US20050103523A1

公开(公告)日：2005-05-19

申请号：US11011442

申请日：2004-12-14

Applicant: William Burton

Inventor： William Burton

IPC: H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24 ,  H05K7/06 ,  H05K3/02

CPC classification number: H05K1/0251 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6633 ,  H01L2924/0002 ,  H01L2924/15173 ,  H01L2924/1903 ,  H01L2924/19039 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/242 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09781 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2924/00

Abstract: An apparatus for routing electrical signals is a layered structure having at least one signal trace disposed on a first side of an electrically insulating layer with a via electrically connected to the trace. The via also has a conductive stub trace electrically connected thereto. A generally planar electrically conductive reference layer is on a second side of the electrically insulating layer and the stub trace on the first side defines an area on the second side where the electrically conductive layer is absent. Removing a portion of the conductive reference layer increases the impedance of the stub trace without changing the impedance of the signal trace thereby improving an impedance match to another electrical element to which the apparatus is connected. A method for manufacturing a layered structure for routing electrical signals comprising the steps of providing a layout for the layered structure having an insulating layer with at least one signal trace, a via, and a stub trace on a first side of the insulating layer, and a generally planar electrically conductive layer disposed on a second side of the insulating layer. Identify the stub trace and define a beneficial portion on the second side based upon a layout of the stub trace where the electrically conductive layer on the second side is to be absent. Modify the layout according to the step of defining and manufacture the layered structure according to the modified layout.

Abstract translation: 一种用于布置电信号的装置是具有至少一个信号迹线的分层结构，该至少一个信号迹线设置在电绝缘层的第一侧，通孔电连接到迹线。 通孔还具有与其电连接的导电短截线。 大致平面的导电参考层位于电绝缘层的第二侧上，并且第一侧上的短截线限定了不存在导电层的第二侧上的区域。 去除导电参考层的一部分增加了短截线迹线的阻抗，而不改变信号迹线的阻抗，从而改善与设备连接的另一个电气元件的阻抗匹配。 一种用于制造用于布线电信号的分层结构的方法，包括以下步骤：提供具有绝缘层的分层结构的布局，该绝缘层具有在绝缘层的第一侧上的至少一个信号迹线，通孔和短截线，以及 设置在所述绝缘层的第二侧上的大致平面的导电层。 基于短路迹线的布局确定短截线并在第二面上限定有益部​​分，其中不存在第二面上的导电层。 根据修改后的布局，按照定义和制作分层结构的步骤修改布局。

公开(公告)号：US06891731B1

公开(公告)日：2005-05-10

申请号：US09431640

申请日：1999-11-01

Applicant: Dennis James Herrell

Inventor： Dennis James Herrell

IPC: H01L23/498 ,  H05K1/02 ,  H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0228 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0224 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/0969 ,  H01L2924/00

Abstract: A technique has been developed whereby crosstalk induced in a first electrical connection by current flow at an adjacent second electrical connection is at least partially cancelled by an opposing crosstalk signal induced at an inductive coupling between electrical traces extending from or toward the first and second electrical connections, respectively. Crosstalk cancellation is provided by orienting the electrical traces such that current flow through the second electrical connection and respective electrical trace induces an opposing crosstalk signal at the inductive coupling. In some configurations, an inductive coupling between electrical traces includes essentially parallel portions of the traces and an aperture in a voltage plane. In some configurations, cancellation of crosstalk induced by multiple adjacent electrical connection is provided. Crosstalk inducing electrical connections include pins, solder bumps, leads, wires, edge connectors, etc. In various configurations, crosstalk cancellation is provided on a board, on a semiconductor package, or on a semiconductor integrated circuit. The crosstalk inducing electrical connections may be integral with the board, package or integrated circuit or may be mated therewith.

Abstract translation: 已经开发了一种技术，其中通过在相邻的第二电连接处的电流流动在第一电连接中引起的串扰至少部分地被在由第一和第二电连接延伸或朝向第一和第二电连接的电迹线之间的感应耦合处感应的相对串扰信号抵消 ， 分别。 通过定向电迹线来提供串扰消除，使得通过第二电连接的电流和相应的电迹线在感应耦合处引起相反的串扰信号。 在一些配置中，电迹线之间的电感耦合包括迹线的基本上平行的部分和电压平面中的孔。 在一些配置中，提供了由多个相邻电连接引起的串扰的消除。 串扰感应电连接包括引脚，焊料凸块，引线，导线，边缘连接器等。在各种配置中，在板上，半导体封装或半导体集成电路上提供串扰消除。 引起串扰的电连接可以与电路板，封装或集成电路成一体，或者与其配合。

公开(公告)号：US20050083148A1

公开(公告)日：2005-04-21

申请号：US10767900

申请日：2004-01-28

Applicant: Jimmy Hsu

Inventor： Jimmy Hsu

IPC: H01P3/08 ,  H05K1/02 ,  H01P5/02

CPC classification number: H05K1/0253 ,  H01P3/08 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09727

Abstract: A signal transmission structure includes at least one reference plane with a non-reference area, and a signal line with a salient protruding over the edge of the signal line and the salient is corresponding to the position of the non-reference area. When a signal passes through the signal line, the effect of the parasitic capacitance between the salient and the reference plane can improve the characteristic impedance mismatch. Therefore, the signal transmission structure can reduce the insertion loss and increase the reduction of the return loss in order to locally compensate the impedance mismatch.

Abstract translation: 信号传输结构包括具有非参考区域的至少一个参考平面以及在信号线的边缘上突出的突出信号线，并且显着对应于非参考区域的位置。 当信号通过信号线时，突出和参考平面之间的寄生电容的影响可以改善特性阻抗失配。 因此，为了局部地补偿阻抗失配，信号传输结构可以减小插入损耗并增加返回损耗的降低。

公开(公告)号：US20050077077A1

公开(公告)日：2005-04-14

申请号：US11000255

申请日：2004-11-30

Applicant: Dustin Wood

Inventor： Dustin Wood

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H05K3/46 ,  H01B17/20

CPC classification number: H05K1/0224 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0253 ,  H05K1/112 ,  H05K3/4602 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/09681 ,  H05K2203/1178 ,  Y10S428/901 ,  Y10T29/49155 ,  Y10T428/24917

Abstract: A semiconductor device package includes multiple built-up layers of metal sandwiching non-conductive layers. The metal layers have grids of degassing holes arranged in rows and columns. The rows and columns are locatable via a first coordinate system. Signal traces are embedded within the non-conductive layers such that the signal traces are also sandwiched between the metal layers with degassing holes. The signal traces generally run at zero degrees, 45 degrees, and 90 degrees relative to a second coordinate system. The first coordinate system is rotated relative to the second coordinate system to lower impedance variations of different traces. Impedance variations decrease due to the decreased variation in the number of degassing holes passed over or under by a trace. The grid of degassing holes on one metal layer can be offset in two dimensions relative to the degassing holes on another layer.

Abstract translation: 半导体器件封装包括金属夹层非导电层的多个堆积层。 金属层具有以排和列排列的脱气孔格栅。 行和列可通过第一个坐标系定位。 信号迹线嵌入在非导电层内，使得信号迹线也被夹在具有脱气孔的金属层之间。 信号迹线通常相对于第二坐标系以零度，45度和90度的速度运行。 第一坐标系相对于第二坐标系旋转以降低不同轨迹的阻抗变化。 阻抗变化由于通过痕迹通过或减少的脱气孔的数量的变化减小而减小。 一个金属层上的脱气孔的网格可以相对于另一层上的脱气孔在两个维度上偏移。