公开(公告)号：US07355288B2

公开(公告)日：2008-04-08

申请号：US11120234

申请日：2005-05-02

Applicant: Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

Inventor： Jin Yuan Lee ,  Ming Ta Lei ,  Ching-Cheng Huang ,  Chuen-Jye Lin

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L21/565 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/525 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/02311 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11831 ,  H01L2224/11849 ,  H01L2224/11901 ,  H01L2224/13023 ,  H01L2224/131 ,  H01L2224/45099 ,  H01L2224/48227 ,  H01L2224/73203 ,  H01L2224/85399 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H04B1/712 ,  H05K3/108 ,  H05K3/243 ,  H05K3/3473 ,  H05K2201/0367 ,  H05K2201/09436 ,  H05K2201/0949 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

Abstract: The invention provides a new method and chip scale package is provided. The inventions starts with a substrate over which a contact point is provided, the contact point is exposed through an opening created in the layer of passivation and a layer of polymer or elastomer. A barrier/seed layer is deposited, a first photoresist mask is created exposing the barrier/seed layer where this layer overlies the contact pad and, contiguous therewith, over a surface area that is adjacent to the contact pad and emanating in one direction from the contact pad. The exposed surface of the barrier/seed layer is electroplated for the creation of interconnect traces. The first photoresist mask is removed from the surface of the barrier/seed layer. A second photoresist mask, defining the solder bump, is created exposing the surface area of the barrier/seed layer that is adjacent to the contact pad and emanating in one direction from the contact pad. The solder bump is created in accordance with the second photoresist mask, the second photoresist mask is removed from the surface of the barrier/seed layer, exposing the electroplating and the barrier/seed layer with the metal plating overlying the barrier/seed layer. The exposed barrier/seed layer is etched in accordance with the pattern formed by the electroplating, reflow of the solder bump is optionally performed.

Abstract translation: 本发明提供了一种新的方法和芯片级封装。 本发明从提供接触点的基底开始，接触点通过在钝化层中形成的开口和聚合物或弹性体层暴露。 形成屏障/种子层，产生第一光致抗蚀剂掩模，暴露阻挡层/籽晶层，其中该层覆盖在接触焊盘上，并与其邻接，在与接触焊盘相邻的表面区域上并且沿一个方向从 接触垫 电镀/种子层的暴露表面被电镀以产生互连迹线。 从阻挡层/种子层的表面去除第一光致抗蚀剂掩模。 产生限定焊料凸块的第二光致抗蚀剂掩模产生暴露与接触焊盘相邻并且在一个方向上从接触焊盘发出的势垒/种子层的表面积。 根据第二光致抗蚀剂掩模产生焊料凸块，从阻挡层/种子层的表面去除第二光致抗蚀剂掩模，用覆盖在阻挡层/种子层上的金属电镀暴露电镀和阻挡层/籽晶层。 根据由电镀形成的图案蚀刻暴露的阻挡层/籽晶层，任选地进行焊料凸点的回流。

公开(公告)号：US07282787B2

公开(公告)日：2007-10-16

申请号：US10828178

申请日：2004-04-21

Applicant: Deepak K. Pai ,  Ronald R. Denny

Inventor： Deepak K. Pai ,  Ronald R. Denny

IPC: H01L23/02

CPC classification number: H05K3/462 ,  H01L2224/05548 ,  H05K3/28 ,  H05K3/3463 ,  H05K3/3484 ,  H05K3/4623 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/0949 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2203/043 ,  H05K2203/063 ,  H05K2203/0733 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49213

Abstract: The present invention is for laminated and interconnected multiple substrates forming a multilayer package or other circuit component. A solder bump may be situated on the conductive pad of at least one of two or more substrates. The solder bump preferably is formed from an application of solder paste to the conductive pad(s). Adhesive films may be positioned between the surfaces of the substrates having the conductive pads, where the adhesive films include apertures located substantially over the conductive pads such that the conductive pads and/or solder bumps confront each other through the aperture. The two or more substrates pressed together via the adhesive films are mechanically bonded. The solder bump(s) may be reflowed during or after the lamination to create a solder segment that provides an electrical connection between the conductive pads through the aperture in the adhesive films.

Abstract translation: 本发明是用于层叠和互连的多个基板，形成多层封装或其他电路部件。 焊料凸块可以位于两个或更多个衬底中的至少一个衬底的导电焊盘上。 焊料凸块优选地由焊膏应用于导电焊盘形成。 粘合剂膜可以位于具有导电焊盘的基板的表面之间，其中粘合剂膜包括基本上位于导电焊盘上方的孔，使得导电焊盘和/或焊料凸块通过孔彼此面对。 通过粘合剂膜压合在一起的两个或多个基材被机械粘合。 可以在叠层期间或之后回流焊料凸块以产生焊接段，该焊料段通过粘合剂膜中的孔提供导电焊盘之间的电连接。

公开(公告)号：US20070238324A1

公开(公告)日：2007-10-11

申请号：US11399351

申请日：2006-04-07

Applicant: Der-Yu Ho

Inventor： Der-Yu Ho

IPC: H01R12/00

CPC classification number: H01R13/22 ,  H01R12/7076 ,  H05K1/0313 ,  H05K1/141 ,  H05K3/325 ,  H05K3/403 ,  H05K2201/0133 ,  H05K2201/049 ,  H05K2201/0949 ,  H05K2201/10378

Abstract: An electrical connector for connection between two electronic devices by means of compressive contact is disclosed to include an electrically insulative connector body, which has a plurality of through holes cut through the top and bottom surfaces thereof, a plurality of conductors respectively formed on the top and bottom surface of the electrically insulative body, and a connection structure, which is formed of a conducting material covered on the surface of each of the through holes to electrically connect the conductors on the top surface of the electrically insulative connector body to the conductors on the bottom surface of the electrically insulative connector body respectively.

Abstract translation: 公开了一种用于通过压缩接触连接在两个电子设备之间的电连接器，其包括电绝缘连接器体，其具有穿过其顶表面和底表面的多个通孔，分别形成在顶部和 电绝缘体的底表面，以及连接结构，其由覆盖在每个通孔的表面上的导电材料形成，以将电绝缘连接器主体的顶表面上的导体电连接到电绝缘体的导体上 电绝缘连接器主体的底面。

公开(公告)号：US07224314B2

公开(公告)日：2007-05-29

申请号：US10997422

申请日：2004-11-24

Applicant: Gregory Steven Lee ,  Robert C. Taber ,  John Stephen Kofol

Inventor： Gregory Steven Lee ,  Robert C. Taber ,  John Stephen Kofol

IPC: H01Q1/38

CPC classification number: H05K1/16 ,  H01Q3/46 ,  H01Q15/148 ,  H01Q19/10 ,  H01Q21/0018 ,  H01Q23/00 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/0949 ,  H05K2201/10166

Abstract: A reflectarray utilizes switching devices with non-ideal impedance characteristics to vary the impedance of reflecting elements. The antennas of the reflecting elements are configured as a function of the impedance of the non-ideal switching devices to provide optimal phase-amplitude performance. In particular, the antennas are configured such that the impedance of each antenna is proportional to the square root of the impedance of the non-ideal switching devices when in an on state and when in an off state.

Abstract translation: 反射阵列利用具有非理想阻抗特性的开关器件来改变反射元件的阻抗。 反射元件的天线被配置为非理想开关器件的阻抗的函数，以提供最佳的相位幅度性能。 特别地，天线被配置为使得当处于接通状态和处于断开状态时，每个天线的阻抗与非理想开关器件的阻抗的平方根成比例。

公开(公告)号：US07217990B2

公开(公告)日：2007-05-15

申请号：US10753828

申请日：2004-01-05

Applicant: Ye-Chung Chung

Inventor： Ye-Chung Chung

IPC: H01L23/495

CPC classification number: H01L22/32 ,  H01L23/49572 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0268 ,  H05K1/0393 ,  H05K2201/0949 ,  H05K2203/1545

Abstract: A tape package in which a test pad is formed on a reverse surface is provided. The test pad is disposed on a reverse surface of a base film through a through hole of the base film. Accordingly, shapes of the test pads are standardized so that a universal probe card can be used. A pitch between the test pads is wide so that the accuracy in an electric test of the tape package is increased. A total length of the tape package is reduced.

Abstract translation: 提供其中在反面上形成测试垫的带包装。 测试垫通过基膜的通孔设置在基膜的反面上。 因此，测试垫的形状被标准化，使得可以使用通用探针卡。 测试垫之间的间距是宽的，使得磁带封装的电测试的精度提高。 磁带封装的总长度减小。

公开(公告)号：US20070023387A1

公开(公告)日：2007-02-01

申请号：US11164388

申请日：2005-11-21

Applicant: Thomas Murry

Inventor： Thomas Murry

IPC: H01B13/00

CPC classification number: H05K3/4614 ,  H05K3/3452 ,  H05K3/4038 ,  H05K2201/0195 ,  H05K2201/0305 ,  H05K2201/0949 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2203/061 ,  H05K2203/063

Abstract: A product of and method for laminating and interconnecting multiple layer printed circuit boards (14) includes at least two complementary substrates (10 and 12) each having a solder bump (30) formed from conductive material (28) applied to a desired component (22). A dam network (34) is formed about the bumps (30) to prevent undesired spreading of the conductive material (28). Bonding material (36) between the surfaces (38a and 38b) of the substrates (10 and 12) bonds the multiple layers. The bonding material (36) has apertures through which the solder bumps (30) are connected.

Abstract translation: 用于层压和互连多层印刷电路板（14）的产品和方法包括至少两个互补基板（10和12），每个互补基板具有由施加到期望部件（22）的导电材料（28）形成的焊料凸块（30） ）。 围绕凸块（30）形成坝网（34），以防止导电材料（28）的不期望的扩散。 衬底（10和12）的表面（38a和38b）之间的粘结材料（36）将多层粘结。 接合材料（36）具有孔，焊料凸块（30）连接在该孔上。

公开(公告)号：US20060285279A1

公开(公告)日：2006-12-21

申请号：US11375797

申请日：2006-03-14

Applicant: Harold Kent ,  James Levante ,  Aaron Fine ,  Joseph Layton

Inventor： Harold Kent ,  James Levante ,  Aaron Fine ,  Joseph Layton

IPC: H02B1/00

CPC classification number: H05K3/3494 ,  H01L23/13 ,  H01L24/02 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/04042 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45147 ,  H01L2224/48 ,  H01L2224/78 ,  H01L2224/85 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/19043 ,  H01R43/0256 ,  H05K1/116 ,  H05K1/184 ,  H05K3/3405 ,  H05K3/3442 ,  H05K3/3447 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/10446 ,  H05K2201/10636 ,  H05K2203/0195 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/2075 ,  H01L2924/00014 ,  H01L2924/20754 ,  H01L2924/20755 ,  H01L2924/00015

Abstract: A micro solder pot includes a dielectric substrate having at least one hole formed therein, a conductive coating coupled to the interior of the hole, and at least one heat transfer pad spaced from the hole in thermal communication with the conductive coating of the hole. When the heat transfer pad is exposed to a heat source, the conductive coating inside the hole is heated. The micro solder pot may also include a thermally activated conductive material disposed within the hole. When the heat transfer pad is exposed to a heat source, the thermally activated conductive material becomes liquidus such that a component can be inserted into the liquidus material. When the heat source is removed, the thermally activated conductive material cools to couple the component to the conductive coating in the hole.

Abstract translation: 微焊料罐包括具有形成在其中的至少一个孔的电介质衬底，耦合到孔的内部的导电涂层以及与所述孔间隔开的与所述孔的导电涂层热连通的至少一个传热垫。 当传热垫暴露于热源时，孔内的导电涂层被加热。 微焊料罐还可以包括设置在孔内的热活化导电材料。 当传热垫暴露于热源时，热活化的导电材料变成液相线，使得部件可以插入液相线材料中。 当热源被去除时，热活化的导电材料冷却以将部件耦合到孔中的导电涂层。

公开(公告)号：US07117587B2

公开(公告)日：2006-10-10

申请号：US10655223

申请日：2003-09-05

Applicant: Huei-Jen Chen ,  Evan Liu ,  Yvon Chen

Inventor： Huei-Jen Chen ,  Evan Liu ,  Yvon Chen

IPC: H01R43/00

CPC classification number: H01L27/14618 ,  H01L31/0203 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49171 ,  H05K1/183 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/42 ,  H05K3/4691 ,  H05K2201/09036 ,  H05K2201/0949 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A method for fabricating a substrate, which includes a plurality of chip package substrates. One combined PCB includes a multi-layer rigid PCB and a soft PCB. The multi-layer rigid PCB is fixed on the soft PCB. At least one grooves or a pair is formed on an upper surface of the multi-layer rigid PCB. A portion of the multi-layer rigid PCB between the grooves is milled to expose a corresponding portion of the soft PCB to define an exposed area. The combined PCB is drilled through along two opposite sides of the grooves and the corresponding exposed area of the soft PCB. Breakable parts are formed at a center of the corresponding portion of the soft PCB and two opposite outside edges of the grooves.

Abstract translation: 一种制造衬底的方法，其包括多个芯片封装衬底。 一个组合PCB包括多层刚性PCB和软PCB。 多层刚性PCB固定在软PCB上。 在多层刚性PCB的上表面上形成至少一个凹槽或一对。 在凹槽之间的多层刚性PCB的一部分被铣削以暴露软PCB的相应部分以限定暴露区域。 组合的PCB通过沟槽的两个相对侧和软PCB的相应的暴露区域钻穿。 可破坏部分形成在软PCB的对应部分的中心和凹槽的两个相对的外边缘。

公开(公告)号：US07079399B2

公开(公告)日：2006-07-18

申请号：US11027215

申请日：2004-12-29

Applicant: Ping Wang ,  Yan-Fang Li

Inventor： Ping Wang ,  Yan-Fang Li

IPC: H05K7/06

CPC classification number: H05K3/3447 ,  H05K1/116 ,  H05K2201/0949 ,  H05K2201/09781 ,  H05K2201/10651 ,  H05K2203/1446

Abstract: A printed circuit board having improved solder pads for preventing from short circuit of the printed circuit board caused by axial leads (30, 31) of components engaging the circuit surrounding the soldering pad comprises a pair of through holes (10, 11), a pair of first pads (20, 21) surrounding corresponding through holes and a pair of second pads (40, 41) adjacent corresponding first pads. When components are inserted into the through holes of the printed circuit board using placement machines, bent portions of the axial leads that are extended out of the first pads will fall into the second pads.

Abstract translation: 一种具有改进的焊盘的印刷电路板，用于防止由围绕焊盘的电路的轴向引线（30,31）引起的印刷电路板的短路，包括一对通孔（10,11），一对 围绕对应的通孔的第一焊盘（20,21）和与相应的第一焊盘相邻的一对第二焊盘（40,41）。 当使用贴片机将部件插入印刷电路板的通孔时，从第一焊盘延伸出来的轴向引线的弯曲部分将落入第二焊盘。

公开(公告)号：US07075176B2

公开(公告)日：2006-07-11

申请号：US11188653

申请日：2005-07-26

Applicant: Huei-Jen Chen ,  Evan Liu ,  Yvon Chen

Inventor： Huei-Jen Chen ,  Evan Liu ,  Yvon Chen

IPC: H02L23/02

CPC classification number: H01L27/14618 ,  H01L31/0203 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/49171 ,  H05K1/183 ,  H05K1/189 ,  H05K3/0052 ,  H05K3/42 ,  H05K3/4691 ,  H05K2201/09036 ,  H05K2201/0949 ,  H05K2203/049 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: A chip package substrate having a soft circuit board jas a multi-layer soft and hard composite PCB, a plurality of conducting components and a plurality of conducting holes. The conducting holes are formed in the multi-layer soft and hard composite PCB. The conducting components are electroplated on the inner edges of the conducting holes on the multi-layer soft and hard composite PCB. An image-sensing chip can thus be packaged on the chip package substrate with the soft circuit board used as external signal connection lines, thereby saving the manufacturing cost and increasing the yield thereof.

Abstract translation: 具有软电路板的芯片封装基板是多层软硬复合PCB，多个导电部件和多个导电孔。 导电孔形成在多层软硬复合PCB中。 导电部件电镀在多层软硬复合PCB上的导电孔的内边缘上。 因此，图像感测芯片可以用作为外部信号连接线的软电路板封装在芯片封装基板上，从而节省制造成本并提高其产量。