公开(公告)号：US08618669B2

公开(公告)日：2013-12-31

申请号：US12174212

申请日：2008-07-16

Applicant: Toru Furuta

Inventor： Toru Furuta

IPC: H01L23/52

CPC classification number: H05K1/186 ,  H01L23/49838 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3511 ,  H05K1/113 ,  H05K3/4614 ,  H05K3/462 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A combination substrate includes a first substrate having multiple wiring board mounting pads for installing a printed wiring board and multiple connection pads on the opposite side of the wiring board mounting pads, a second substrate having multiple package substrate mounting pads for loading one or more package substrates and multiple connection pads on the opposite side of the package substrate mounting pads, a resin component filling a space between the first substrate and the second substrate, and multiple component loading pads positioned to load an electronic component between the first substrate and the second substrate and formed on one of the first substrate and the second substrate. The connection pads of the second substrate are electrically connected to the connection pads of the first substrate.

Abstract translation: 组合基板包括具有用于安装印刷线路板的多个布线板安装焊盘和在布线板安装焊盘的相对侧上的多个连接焊盘的第一基板，具有用于装载一个或多个封装基板的多个封装基板安装焊盘的第二基板 以及在所述封装衬底安装衬垫的相对侧上的多个连接焊盘，填充所述第一衬底和所述第二衬底之间的空间的树脂部件以及被定位成在所述第一衬底和所述第二衬底之间加载电子部件的多个部件装载垫，以及 形成在第一基板和第二基板中的一个上。 第二基板的连接焊盘电连接到第一基板的连接焊盘。

公开(公告)号：US20130192884A1

公开(公告)日：2013-08-01

申请号：US13685777

申请日：2012-11-27

Applicant: IBIDEN Co., Ltd.

Inventor： Toshiki FURUTANI ,  Yukinobu MIKADO ,  Mitsuhiro TOMIKAWA

IPC: H05K1/18

CPC classification number: H05K1/181 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/185 ,  H05K3/4697 ,  H05K2201/09527 ,  H05K2201/096

Abstract: A printed wiring board includes a core substrate, an electronic component accommodated in the substrate, a first buildup structure formed on surface of the substrate and including an interlayer insulation layer, and a second buildup structure formed on the opposing surface of the substrate and including an interlayer insulation layer. The substrate includes a core material portion including multiple resin layers, a first conductive layer formed on first surface of the core portion and a second conductive layer formed on second surface of the core portion, the core portion has opening through the resin layers and accommodating the component, the insulation layer of the first structure is positioned such that the opening of the core portion is covered on the first surface, and the insulation layer of the second structure is positioned such that the opening of the core portion is covered on the second surface.

Abstract translation: 印刷电路板包括芯基板，容纳在基板中的电子部件，形成在基板的表面上并且包括层间绝缘层的第一累积结构和形成在基板的相对表面上的第二累积结构， 层间绝缘层。 基板包括具有多个树脂层的芯材部分，形成在芯部的第一表面上的第一导电层和形成在芯部的第二表面上的第二导电层，芯部具有通过树脂层的开口并容纳 第一结构的绝缘层被定位成使得芯部的开口被覆盖在第一表面上，并且第二结构的绝缘层被定位成使得芯部的开口被覆盖在第二表面上 。

公开(公告)号：US20130099390A1

公开(公告)日：2013-04-25

申请号：US13712224

申请日：2012-12-12

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoichiro KURITA ,  Masaya KAWANO ,  Koji SOEJIMA

IPC: H01L23/538

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

公开(公告)号：US08354340B2

公开(公告)日：2013-01-15

申请号：US11865745

申请日：2007-10-02

Applicant: Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

Inventor： Yoichiro Kurita ,  Masaya Kawano ,  Koji Soejima

IPC: H01L21/4763 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3121 ,  H01L23/49816 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/02 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/02319 ,  H01L2224/02331 ,  H01L2224/02333 ,  H01L2224/02372 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/16137 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/17181 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/83005 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/18161 ,  H01L2924/19015 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K3/0058 ,  H05K3/284 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2201/09527 ,  H05K2201/096 ,  H05K2201/09972 ,  H05K2203/016 ,  H05K2203/0733 ,  H05K2203/1469 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a conventional electronic device and a method of manufacturing the same, reduction in cost of the electronic device is hindered because resin used in an interconnect layer on the solder ball side is limited. The electronic device includes an interconnect layer (a first interconnect layer) and an interconnect layer (a second interconnect layer). The second interconnect layer is formed on the undersurface of the first interconnect layer. The second interconnect layer is larger in area seen from the top than the first interconnect layer and is extended to the outside from the first interconnect layer.

Abstract translation: 在传统的电子设备及其制造方法中，由于在焊球侧的互连层中使用的树脂受到限制，妨碍了电子设备的成本的降低。 电子设备包括互连层（第一互连层）和互连层（第二互连层）。 第二互连层形成在第一互连层的下表面上。 第二互连层的面积比第一互连层的面积大，并且从第一互连层延伸到外部。

公开(公告)号：US08258620B2

公开(公告)日：2012-09-04

申请号：US12673409

申请日：2008-08-08

Applicant: Mayumi Nakasato ,  Ryosuke Usui ,  Kiyoshi Shibata

Inventor： Mayumi Nakasato ,  Ryosuke Usui ,  Kiyoshi Shibata

IPC: H01L23/053 ,  H01L23/12

CPC classification number: H01L23/145 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/563 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/81 ,  H01L24/83 ,  H01L24/90 ,  H01L29/0657 ,  H01L2221/68345 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13021 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/83101 ,  H01L2224/83104 ,  H01L2224/83192 ,  H01L2224/838 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/0366 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/002 ,  H05K3/305 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/1152 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2224/05599

Abstract: A circuit device includes an insulating base provided with a resin layer mixed with a fibrous filler, bumps provided in the insulating base and functioning as electrodes for connection, a semiconductor device that is flip-chip mounted, and an underfill filling a gap between the semiconductor device and the insulating base. By allowing the fibrous filler projecting through the top surface of the resin layer to be in contact with the underfill, strength of adhesion between the underfill and the insulating base is improved.

Abstract translation: 电路装置包括：绝缘基体，设置有与纤维填料混合的树脂层，设置在绝缘基底中的凸起，用作连接用电极，倒装芯片安装的半导体器件，以及填充半导体之间的间隙的底部填充物 设备和绝缘基座。 通过使通过树脂层的上表面突出的纤维状填料与底部填充剂接触，提高了底部填充剂和绝缘基材之间的粘合强度。

公开(公告)号：US20120205145A1

公开(公告)日：2012-08-16

申请号：US13453229

申请日：2012-04-23

Applicant: Norio SAKAI

Inventor： Norio SAKAI

IPC: H05K1/03 ,  B32B37/12 ,  B32B37/14

CPC classification number: H05K3/4617 ,  H05K1/186 ,  H05K3/4632 ,  H05K3/4691 ,  H05K2201/0129 ,  H05K2201/0191 ,  H05K2201/09527 ,  H05K2201/096 ,  Y10T156/10

Abstract: A multilayer substrate includes a plurality of stacked thermoplastic resin layers each including an in-plane conductive pattern provided on one principal surface thereof and an interlayer conductive portion arranged to penetrate through the thermoplastic resin layer in a thickness direction. The plurality of thermoplastic resin layers include a first thermoplastic resin layer and a second thermoplastic resin layer, a stacking direction of which is inverted with respect to a stacking direction of the first thermoplastic resin layer. The second thermoplastic resin layer is thicker than the first thermoplastic resin layer. One end in the thickness direction of the interlayer conductive portion provided in the second thermoplastic resin layer is connected with the interlayer conductive portion of the thermoplastic resin layer adjacent to the second thermoplastic resin layer in the thickness direction such that the in-plane conductive pattern is not interposed therebetween.

Abstract translation: 多层基板包括多个堆叠的热塑性树脂层，每个层叠的热塑性树脂层包括设置在其一个主表面上的面内导电图案和布置成在厚度方向上穿透热塑性树脂层的层间导电部分。 多个热塑性树脂层包括第一热塑性树脂层和第二热塑性树脂层，层叠方向相对于第一热塑性树脂层的层叠方向反转。 第二热塑性树脂层比第一热塑性树脂层厚。 设置在第二热塑性树脂层中的层间导电部分的厚度方向的一端与厚度方向上与第二热塑性树脂层相邻的热塑性树脂层的层间导电部分连接，使得面内导电图案为 不插入其间。

公开(公告)号：US08097946B2

公开(公告)日：2012-01-17

申请号：US12263174

申请日：2008-10-31

Applicant: Kouichi Saitou ,  Mayumi Nakasato ,  Ryosuke Usui

Inventor： Kouichi Saitou ,  Mayumi Nakasato ,  Ryosuke Usui

IPC: H01L23/053 ,  H01L23/12

CPC classification number: H01L23/49811 ,  H01L23/145 ,  H01L23/3733 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H05K1/0366 ,  H05K1/112 ,  H05K3/0041 ,  H05K3/3436 ,  H05K3/3457 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2203/1152 ,  H01L2224/05599

Abstract: A device mounting board includes an insulating layer formed of an insulating resin, a glass cloth covering the surface of the insulating layer, and an electrode provided in a through hole extending through the glass cloth. The angle of contact with solder of the glass cloth is larger than that of the resin. Thus, solder bumps are formed on the electrode 14 of the device mounting board 10 with high precision.

Abstract translation: 装置安装板包括由绝缘树脂形成的绝缘层，覆盖绝缘层表面的玻璃布和设置在穿过玻璃布的通孔中的电极。 玻璃布与焊料的接触角大于树脂的接触角。 因此，在装置安装基板10的电极14上高精度地形成焊锡凸块。

公开(公告)号：US20110220399A1

公开(公告)日：2011-09-15

申请号：US13114693

申请日：2011-05-24

Applicant: Ayao NIKI

Inventor： Ayao NIKI

IPC: H05K1/00

CPC classification number: H05K1/115 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/0352 ,  H05K2201/0394 ,  H05K2201/09527 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2203/0554 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49162

Abstract: A multilayer printed wiring board includes one or more resin layers having via-holes and a core layer having via-holes. The via-holes formed in the one or more resin layers are open in the direction opposite to the direction in which the via-holes formed in the core layer are open. A method for manufacturing a multilayer printed wiring board includes a step of preparing a single- or double-sided copper-clad laminate; a step of forming lands by processing the copper-clad laminate; a step of forming a resin layer on the upper surface of the copper-clad laminate, forming openings for via-holes in the resin layer, and then forming the via-holes; and a step of forming openings for via-holes in the lower surface of the copper-clad laminate and then forming the via-holes.

Abstract translation: 多层印刷线路板包括一个或多个具有通孔的树脂层和具有通孔的芯层。 在一个或多个树脂层中形成的通孔在与芯层中形成的通路孔打开的方向相反的方向上开口。 一种制造多层印刷线路板的方法包括制备单面或双面覆铜层压板的步骤; 通过加工覆铜层压板来形成焊盘的步骤; 在覆铜层压板的上表面上形成树脂层的步骤，在树脂层中形成通孔的开口，然后形成通孔; 以及在覆铜层压板的下表面中形成用于通孔的开口，然后形成通孔的步骤。

公开(公告)号：US20110156272A1

公开(公告)日：2011-06-30

申请号：US12976427

申请日：2010-12-22

Applicant: Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

Inventor： Shinnosuke MAEDA ,  Tetsuo SUZUKI ,  Atsuhiko SUGIMOTO ,  Tatsuya ITO ,  Takuya HANDO ,  Satoshi HIRANO

IPC: H01L23/48

CPC classification number: H05K3/3452 ,  H01L23/49811 ,  H01L23/49822 ,  H01L2924/0002 ,  H05K1/113 ,  H05K3/205 ,  H05K3/383 ,  H05K3/4682 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09527 ,  H05K2201/099 ,  H05K2203/0346 ,  H05K2203/0369 ,  H01L2924/00

Abstract: A multilayered wiring substrate, comprising: a plurality of first main surface side connecting terminals arranged in a first main surface of a stack structure; and a plurality of second main surface side connecting terminals being arranged in a second main surface of the stack structure; wherein a plurality of conductor layers are alternately formed in a plurality of stacked resin insulation layers and are operably connected to each other through via conductors tapered such that diameters thereof are widened toward the first or the second main surface, wherein a plurality of openings are formed in an exposed outermost resin insulation layer in the second main surface, and terminal outer surfaces of the second main surface side connecting terminals arranged to match with the plurality of the openings are positioned inwardly from an outer main surface of the exposed outermost resin insulation layer, and edges of terminal inner surfaces are rounded.

Abstract translation: 一种多层布线基板，包括：布置在堆叠结构的第一主表面中的多个第一主表面侧连接端子; 并且多个第二主表面侧连接端子布置在所述堆叠结构的第二主表面中; 其中多个导体层交替地形成在多个堆叠的树脂绝缘层中，并且通过锥形的通孔导体可操作地连接，使得其直径朝向第一或第二主表面加宽，其中形成多个开口 在第二主表面中暴露的最外层树脂绝缘层中，并且布置成与多个开口相匹配的第二主表面侧连接端子的端子外表面从暴露的最外层树脂绝缘层的外主表面位于内侧， 并且端子内表面的边缘是圆形的。

公开(公告)号：US07882626B2

公开(公告)日：2011-02-08

申请号：US12393478

申请日：2009-02-26

Applicant: Kei Murayama ,  Mitsutoshi Higashi ,  Masahiro Sunohara

Inventor： Kei Murayama ,  Mitsutoshi Higashi ,  Masahiro Sunohara

IPC: H05K3/30

CPC classification number: H05K3/3473 ,  H01L21/4857 ,  H01L21/568 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/81 ,  H01L24/97 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81801 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/005 ,  H05K3/007 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/0108 ,  H05K2203/0113 ,  H05K2203/016 ,  H05K2203/0338 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A method of manufacturing a wiring board having a semiconductor chip mounting surface for mounting a semiconductor chip thereon which is manufactured by a process including a step of forming a wiring layer and an insulating layer on a support board and a step of removing the support board, including a peeling layer forming step of forming a peeling layer on the support board formed by a material having a coefficient of thermal expansion which is equal to that of a semiconductor substrate constituting the semiconductor chip, and a support board removing step of removing the support board by carrying out a predetermined treatment over the peeling layer.

Abstract translation: 一种制造具有用于安装半导体芯片的半导体芯片安装表面的布线板的方法，其通过包括在支撑板上形成布线层和绝缘层的步骤的工艺制造，以及去除支撑板的步骤， 包括在由具有与构成半导体芯片的半导体衬底的热膨胀系数相同的热膨胀系数的材料形成的支撑板上形成剥离层的剥离层形成步骤，以及去除支撑板的支撑板移除步骤 通过对剥离层进行预定处理。