公开(公告)号：US07432776B2

公开(公告)日：2008-10-07

申请号：US10890054

申请日：2004-07-13

Applicant: Herman Kwong ,  Aneta Wyrzykowska ,  Larry Marcanti

Inventor： Herman Kwong ,  Aneta Wyrzykowska ,  Larry Marcanti

IPC: H01P3/08

CPC classification number: H05K1/0221 ,  H01P3/06 ,  H01P5/183 ,  H05K1/024 ,  H05K2201/09672 ,  H05K2201/09809 ,  H05K2201/09981

Abstract: A printed circuit board transmission line has an outer conductive wall surrounding an inner dielectric core. The transmission line may be disposed inside a grounded shielding to provide a form of coaxial conductor that mitigates cross talk from adjacent transmission lines and EMI. Further, groups of dielectric-core transmission lines may be disposed within a single grounded shield. For example, edge coupled differential pairs may be disposed in parallel with each other on a plane defined by a layer of the printed circuit board, i.e., side-by-side. Further, broadside-coupled differential pairs of dielectric-core transmission lines may be disposed in parallel with each other in a stack which is orthogonal with the plane defined by a layer of the printed circuit board, i.e., one on top of the other. Further, a plurality of dielectric-core transmission lines which may include all or ones of single-ended lines and differential pairs may be disposed within a single grounded shield.

Abstract translation: 印刷电路板传输线具有围绕内部介质芯的外部导电壁。 传输线可以设置在接地屏蔽内，以提供一种形式的同轴导体，其减轻了来自相邻传输线的串扰和EMI。 此外，介质芯传输线组可以设置在单个接地屏蔽内。 例如，边缘耦合差动对可以在由印刷电路板的层（即并排）限定的平面上彼此平行地设置。 此外，介质芯传输线的宽侧耦合差分对可以彼此平行地布置在与由印刷电路板的层（即，一个在另一个上面）限定的平面正交的堆叠中。 此外，可以包括单端线路和差分对线路中的全部或者多条的多个介质芯线传输线路设置在单个接地屏蔽层内。

公开(公告)号：US07430128B2

公开(公告)日：2008-09-30

申请号：US10967541

申请日：2004-10-18

Applicant: William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

Inventor： William J. Borland ,  G. Sidney Cox ,  David Ross McGregor

IPC: H05K1/16

CPC classification number: H05K1/167 ,  H05K1/162 ,  H05K3/429 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09672 ,  H05K2201/09763 ,  H05K2203/0361 ,  H05K2203/1461 ,  Y10T29/435

Abstract: This invention relates to a capacitive/resistive device, which may be embedded within a layer of a printed wiring board. Embedding the device conserves board surface real estate, and reduces the number of solder connections, thereby increasing reliability. More specifically, the device, comprises a first metallic foil; a second metallic foil; a first electrode formed from the first metallic foil; a dielectric disposed over the first electrode, a resistor element formed on and adjacent to the dielectric; a conductive trace; and a second electrode formed from the second metallic foil and disposed over the dielectric and in electrical contact with the resistor element, wherein the dielectric is disposed between the first electrode and the second electrode and wherein said dielectric comprises an unfilled polymer of dielectric constant less than 4.0. This invention also relates to a method of making the device.

Abstract translation: 本发明涉及可以嵌入在印刷线路板的层内的电容/电阻装置。 嵌入器件节省了电路板表面的空间，并减少了焊接连接的数量，从而提高了可靠性。 更具体地，该装置包括第一金属箔; 第二金属箔; 由所述第一金属箔形成的第一电极; 设置在所述第一电极上的电介质; 形成在电介质上并与其相邻的电阻元件; 导电迹线 以及由所述第二金属箔形成并且设置在所述电介质上并与所述电阻元件电接触的第二电极，其中所述电介质设置在所述第一电极和所述第二电极之间，并且其中所述电介质包括介电常数小于 4.0。 本发明还涉及制造该装置的方法。

公开(公告)号：US20080196933A1

公开(公告)日：2008-08-21

申请号：US12148017

申请日：2008-04-16

Applicant: Karl Joseph Bois ,  Timothy L. Michalka

Inventor： Karl Joseph Bois ,  Timothy L. Michalka

IPC: H01R12/14 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4688 ,  H05K1/024 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/49124

Abstract: A printed circuit board (PCB) substrate and method for construction of the same. In one embodiment, a first dielectric material is associated with a first current return layer and a second dielectric material is associated with a second current return layer. A first signal path layer is embedded in the first dielectric material and a second signal path layer is embedded in the second dielectric material, wherein the first and second signal path layers are substantially parallel to each other in a stack-up arrangement. An adhesive layer is interposed between the first dielectric material and the second dielectric material.

Abstract translation: 印刷电路板（PCB）基板及其构造方法。 在一个实施例中，第一电介质材料与第一电​​流返回层相关联，并且第二电介质材料与第二电流返回层相关联。 第一信号通路层被嵌入在第一电介质材料中，第二信号路径层被嵌入在第二电介质材料中，其中第一和第二信号通路层以叠层布置基本上彼此平行。 在第一电介质材料和第二电介质材料之间插入粘合剂层。

公开(公告)号：US20080121418A1

公开(公告)日：2008-05-29

申请号：US11970163

申请日：2008-01-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area. The wiring board further includes: a line that electrically connects either one of a power pad for supplying power to the IC chip and a ground pad for grounding the IC chip to either one of the first lower electrode and the second lower electrode; and a line that electrically connects the other of the power pad and the ground pad to the other of the first upper electrode and the second upper electrode.

公开(公告)号：US07378598B2

公开(公告)日：2008-05-27

申请号：US10782640

申请日：2004-02-19

Applicant: Karl Joseph Bois ,  Timothy L. Michalka

Inventor： Karl Joseph Bois ,  Timothy L. Michalka

IPC: H01R12/14 ,  H05K1/11

CPC classification number: H05K3/4688 ,  H05K1/024 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/0715 ,  H05K2201/09672 ,  H05K2201/09881 ,  Y10T29/49124

Abstract: A printed circuit board (PCB) substrate and method for construction of the same. In one embodiment, a first dielectric material is associated with a first current return layer and a second dielectric material is associated with a second current return layer. A signal path layer is interposed between the first dielectric material and the second dielectric material. An adhesive layer is interposed between the first dielectric material and the second dielectric material such that the adhesive layer is substantially coplanar relative to the signal path layer.

Abstract translation: 印刷电路板（PCB）基板及其构造方法。 在一个实施例中，第一电介质材料与第一电​​流返回层相关联，并且第二电介质材料与第二电流返回层相关联。 信号通路层介于第一电介质材料和第二电介质材料之间。 粘合剂层介于第一电介质材料和第二电介质材料之间，使得粘合剂层相对于信号路径层基本上是共面的。

公开(公告)号：US20080054308A1

公开(公告)日：2008-03-06

申请号：US11928070

申请日：2007-10-30

Applicant: Zhaoqing Chen ,  Christian Schuster

Inventor： Zhaoqing Chen ,  Christian Schuster

IPC: H01L27/10

CPC classification number: H01L23/5222 ,  H01L2924/0002 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: An electrical device includes a plurality of interconnects passing through a plane. The interconnects have a longitudinal axis substantially perpendicular to the plane and including an arrangement pattern which reduces or eliminates cross-talk between nearest neighboring interconnects, wherein the interconnects include a first differentially driven signal conductor pair and at least one other signal conductor, and the arrangement includes the at least one other signal conductor disposed at a substantially same distance from each conductor of the first differentially driven signal conductor pair.

Abstract translation: 电气装置包括通过平面的多个互连件。 互连具有基本上垂直于平面的纵向轴线并且包括减少或消除最近相邻互连件之间的串扰的布置图案，其中互连包括第一差分驱动信号导体对和至少一个其它信号导体，并且布置 包括设置在与第一差分驱动信号导体对的每个导体基本相同的距离处的至少一个其它信号导体。

公开(公告)号：US20080000061A1

公开(公告)日：2008-01-03

申请号：US11819897

申请日：2007-06-29

Applicant: Seung Gyo Jeong ,  Yong Seok Choi ,  Ki Pyo Hong

Inventor： Seung Gyo Jeong ,  Yong Seok Choi ,  Ki Pyo Hong

IPC: H01G9/00

CPC classification number: H01G4/30 ,  H01G4/232 ,  H01L2224/48091 ,  H01L2924/01019 ,  H01L2924/09701 ,  H01L2924/30107 ,  H05K1/0231 ,  H05K1/0306 ,  H05K1/162 ,  H05K1/186 ,  H05K3/4611 ,  H05K3/4629 ,  H05K3/4688 ,  H05K2201/09672 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of manufacturing a capacitor-embedded low temperature co-fired ceramic substrate, the method including: manufacturing a capacitor part by firing a deposition including at least one high dielectric ceramic sheet to form a capacitor part; providing a plurality of low temperature co-fired green sheets each having at least one of a conductive pattern and a conductive via hole thereon; forming a low temperature co-fired ceramic deposition by depositing the low temperature co-fired green sheets to embed the capacitor part in the low temperature co-fired ceramic deposition, the embedded capacitor part connected to the one of conductive pattern and conductive via hole of an adjacent one of the green sheets; and firing the low temperature co-fired ceramic deposition having the capacitor part embedded therein. The capacitor-embedded low temperature co-fired ceramic substrate may be beneficially employed in various types of capacitor part such as a deposited chip capacitor and a capacitor layer structure.

Abstract translation: 一种制造电容器嵌入式低温共烧陶瓷基板的方法，所述方法包括：通过烧结包括至少一个高介电陶瓷片的沉积物来形成电容器部分，以形成电容器部分; 提供多个低温共烧生坯片，每个低温共烧生坯在其上具有导电图案和导电通孔中的至少一个; 通过沉积低温共烧生片将电容器部分嵌入低温共烧陶瓷沉积中形成低温共烧陶瓷沉积，将嵌入式电容器部分连接到导电图案和导电通孔中的一个 相邻的一个生片; 并烧制具有嵌入其中的电容器部分的低温共烧陶瓷沉积。 电容器嵌入式低温共烧陶瓷基板可以有利地用于各种类型的电容器部分，例如沉积的芯片电容器和电容器层结构。

公开(公告)号：US20070297147A1

公开(公告)日：2007-12-27

申请号：US11471849

申请日：2006-06-21

Applicant: Weidong Zhuang

Inventor： Weidong Zhuang

IPC: H05K7/00

CPC classification number: H05K1/0228 ,  H01L23/5387 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/48091 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H05K1/189 ,  H05K2201/09672 ,  H05K2201/10166 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A power module includes a power switching device and a flexible circuit with first and second traces electrically connected to the switching device, the first and second traces serving as an input signal carrier and an output signal carrier for the switching device.

Abstract translation: 功率模块包括功率开关器件和柔性电路，其中第一和第二迹线电连接到开关器件，第一和第二迹线用作输入信号载体和用于开关器件的输出信号载体。

公开(公告)号：US20070240303A1

公开(公告)日：2007-10-18

申请号：US11670463

申请日：2007-02-02

Applicant: Jin Kim ,  Min Kim ,  Jun Oh ,  Tae Kim

Inventor： Jin Kim ,  Min Kim ,  Jun Oh ,  Tae Kim

IPC: H01R43/00 ,  H05K1/00

CPC classification number: H05K1/162 ,  H05K1/0373 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/0209 ,  H05K2201/09536 ,  H05K2201/09672 ,  Y10T29/435 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed herein is a printed circuit board including embedded capacitors, composed of a polymer condenser laminate including a plurality of polymer condenser layers, each of which has a polymer sheet and a conductor pattern formed on the polymer sheet, and a via hole for interlayer connection therethrough, and a circuit layer formed on either surface or both surfaces of the polymer condenser laminate and having a circuit pattern and a via hole for interlayer connection therethrough. The printed circuit board of the current invention has higher capacitance density per unit area than conventional embedded capacitor printed circuit boards, whereby capacitors having various capacitance values, such as multilayered ceramic capacitors having high capacitance, can be embedded in the printed circuit board, instead of being mounted thereon. Also, a method of manufacturing the printed circuit board including embedded capacitors is provided.

Abstract translation: 本发明公开了一种印刷电路板，其包括嵌入式电容器，其由聚合物冷凝器层压体构成，聚合物冷凝层压板包括多个聚合物聚合物层，每个聚合物聚合物层具有形成在聚合物片上的聚合物片和导体图案，以及用于层间连接的通孔 以及形成在聚合物冷凝层叠体的任一表面或两个表面上的电路层，并且具有电路图案和用于通过其进行层间连接的通孔。 本发明的印刷电路板比传统的嵌入式电容器印刷电路板具有更高的每单位面积的电容密度，由此具有各种电容值的电容器，例如具有高电容的多层陶瓷电容器可以嵌入印刷电路板中，而不是 安装在其上。 此外，提供了一种制造包括嵌入式电容器的印刷电路板的方法。

公开(公告)号：US20070222031A1

公开(公告)日：2007-09-27

申请号：US11456094

申请日：2006-07-07

Applicant: Uei-Ming Jow ,  Chang-Sheng Chen ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

Inventor： Uei-Ming Jow ,  Chang-Sheng Chen ,  Ying-Jiunn Lai ,  Chin-Sun Shyu

IPC: H01L29/00

CPC classification number: H05K1/162 ,  H01G4/232 ,  H01G4/306 ,  H01L23/50 ,  H01L23/5223 ,  H01L28/10 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/09672 ,  H01L2924/00

Abstract: A capacitor structure with a cross-coupling design is provided. In the capacitor structure, conductive lines or electrode plates are coupled together by cross coupling an electrode above or below or aside the other electrode. By cross coupling and fewer vias, the largest capacitance value can be obtained within a minimum area. The capacitor structure provided can also be applied to a high-frequency high-speed module or system to enhance noise inhibition capability of a capacitive substrate.

Abstract translation: 提供了具有交叉耦合设计的电容器结构。 在电容器结构中，通过在另一电极上方或下方或旁边交叉耦合电极将导线或电极板耦合在一起。 通过交叉耦合和较少的通孔，可以在最小区域内获得最大的电容值。 所提供的电容器结构也可以应用于高频高速模块或系统，以增强电容性基板的噪声抑制能力。