公开(公告)号：US5067229A

公开(公告)日：1991-11-26

申请号：US601934

申请日：1990-10-22

Applicant: Nobuyuki Nakamura

Inventor： Nobuyuki Nakamura

IPC: B23C3/28 ,  B23C1/06 ,  B23C3/00 ,  B24B27/06 ,  G09F3/00 ,  H01L25/075 ,  H05K1/02 ,  H05K3/00

CPC classification number: G09F3/00 ,  H01L25/0753 ,  H05K1/0266 ,  H05K3/0052 ,  H01L2924/0002 ,  H05K2201/09063 ,  H05K2201/0909 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2201/10106 ,  H05K2203/1545 ,  Y10T29/49121 ,  Y10T29/5148 ,  Y10T409/307 ,  Y10T409/307112 ,  Y10T409/30924

Abstract: The present invention provides a method of producing electronic components such as LED displays and hybrid IC's from a board supply frame. The frame comprises a parallel pair of elongate side bands, and a plurality of unit circuit boards integrally incorporated in the frame by means of connecting webs and arranged between the pair of side bands at a predetermined interval therealong. Various process steps such as chip bonding and wire bonding are performed with respect to the individual circuit boards while they are still in the frame. In a final step, each unit circuit board or electronic component is separated from the frame. The frame may be provided with an identification pattern to identify the type of unit circuit boards incorporated in the frame.

Abstract translation: 本发明提供一种从电路板供给框架制造诸如LED显示器和混合IC的电子部件的方法。 该框架包括平行的一对细长边带，以及多个单元电路板，其通过连接腹板一体地结合在框架中，并且以一定间隔在该对边带之间布置。 当各个电路板仍在框架中时，执行诸如芯片接合和引线键合的各种工艺步骤。 在最后一步中，每个单元电路板或电子部件与框架分离。 该框架可以设置有识别图案，以识别结合在框架中的单元电路板的类型。

公开(公告)号：US5010449A

公开(公告)日：1991-04-23

申请号：US504466

申请日：1990-04-04

Applicant: Robert L. Baldino

Inventor： Robert L. Baldino

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4638 ,  H05K1/0266 ,  H05K1/0269 ,  H05K2201/0108 ,  H05K2201/09781 ,  H05K2201/09936

Abstract: A method for assuring that a multi-layer circuit board has been assembled in a selected order which method incorporates the step of forming a label on each layer of the multi-layer circuit board, with each of the labels having a unique indicia thereon indicative of that layers position in a correctly assembled multi-layer circuit board. Additionally, there is provided the step of forming a transparent area in each layer above the last layer to be viewed, with the size of each transparent area limited to that necessary to view only the indicia of the following correctly assembled layers, such that an incorrectly ordered layer prevents the viewing of at least one indicia. A replication of the labels, commencing from the last ordered layer to the first ordered layer, provides for a doubling in the number of layers that can be checked for correct assembly order.

Abstract translation: 一种用于确保以选定顺序组装多层电路板的方法，该方法包括在多层电路板的每层上形成标签的步骤，其中每个标签在其上具有唯一的标记，指示 该层位于正确组装的多层电路板中。 此外，提供了在要观看的最后一层上的每个层中形成透明区域的步骤，每个透明区域的尺寸仅限于仅查看以下正确组装的层的标记所需的尺寸，使得不正确地 有序层阻止观看至少一个标记。 从最后一个有序层开始到第一个有序层的标签的复制提供可以检查正确的汇编顺序的层数加倍。

公开(公告)号：US4756929A

公开(公告)日：1988-07-12

申请号：US681686

申请日：1984-12-14

Applicant: Donald F. Sullivan

Inventor： Donald F. Sullivan

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/18 ,  H05K3/24 ,  H05K3/34 ,  H05K3/46 ,  B05D5/12 ,  G03C5/00 ,  H05K1/00 ,  H05K3/02

CPC classification number: H05K3/107 ,  H05K3/184 ,  H05K3/242 ,  H05K3/3452 ,  H05K1/117 ,  H05K2201/09036 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2201/09981 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/056 ,  H05K2203/0571 ,  H05K2203/0577 ,  H05K2203/066 ,  H05K2203/0759 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/108 ,  H05K3/4661 ,  Y10T29/49155

Abstract: Densely packed high resolution printed wiring boards may be achieved by providing channels below grade in a substrate planar surface, thereby providing greater conductor width for closely spaced conductors. By mechanically removing the substrate surface between the channels, high virtual resolution is obtained with high quality conductors and insulation spacings of the order of about 0.003 inch, and with actual conductor widths of greater than 0.012 inch. Thus the packing density of printed wiring patterns may be increased significantly. Also the quality of conductor adherence and conductivity is improved. Thus a non-critical and inexpensive process unexpectedly provides an improved quality, more precise printed wiring pattern.

Abstract translation: 密集的高分辨率印刷线路板可以通过在基板平面中提供低于等级的通道，从而为紧密间隔的导体提供更大的导体宽度。 通过机械地去除通道之间的基板表面，可以获得具有约0.003英寸量级的高质量导体和绝缘间距以及大于0.012英寸的实际导体宽度的高虚拟分辨率。 因此，可以显着地增加印刷布线图案的包装密度。 导体粘附性和导电性也提高了。 因此，非关键和廉价的工艺意外地提供了改进的质量，更精确的印刷布线图案。

公开(公告)号：US4750264A

公开(公告)日：1988-06-14

申请号：US804506

申请日：1985-12-04

Applicant: Pedro V. Melero

Inventor： Pedro V. Melero

IPC: G09B23/18 ,  H05K3/10 ,  H05K7/06 ,  H05K13/06 ,  H05K3/30 ,  B23P19/04

CPC classification number: H05K3/103 ,  H05K7/06 ,  H05K2201/09936 ,  H05K2201/10287 ,  H05K2203/1469 ,  Y10T29/49131 ,  Y10T29/49139 ,  Y10T29/53222

Abstract: A procedure and apparatus for preparing an electronic baseboard are disclosed. The baseboard is marked such that each side shows the specific location for various circuit elements and their corresponding connections. The components are inserted into holes in the base board and are connected by means of a wiring device. The wiring device includes a tubular hollow body which houses an electrical conductor wire. A reel is rotatably attached to one end of the hollow body. The electrical conductor wire is wound on the rotatable reel, runs axially through the hollow body and emanates through a nozzle at a second end of the device. The device is optionally provided with a blade for cutting the electrical conductor wire.

Abstract translation: 公开了一种用于制备电子基板的程序和装置。 基板被标记为使得每一侧显示各种电路元件及其相应连接的特定位置。 部件插入基板的孔中，并通过接线装置连接。 布线装置包括容纳电导线的管状中空体。 卷轴可旋转地附接到中空体的一端。 电导体线缠绕在可旋转的卷轴上，轴向地穿过中空体，并通过装置的第二端处的喷嘴发出。 该设备可选地设置有用于切割电导线的刀片。

公开(公告)号：US4682271A

公开(公告)日：1987-07-21

申请号：US844609

申请日：1986-03-27

Applicant: Kazuhiko Yamada

Inventor： Kazuhiko Yamada

IPC: H05K1/02 ,  H05K3/12 ,  H05K3/28 ,  H05K3/30

CPC classification number: H05K1/0266 ,  H05K2201/09936 ,  H05K2203/122 ,  H05K2203/1572 ,  H05K3/1216 ,  H05K3/30 ,  Y10T29/49124

Abstract: A printed circuit board having a circuit pattern formed on at least one of the first and second faces of a substrate and having characters and symbols representing components to be mounted on said substrate printed on the first face and the second face of the substrate, wherein the characters printed on the first face have been printed in the reversed images in about the corresponding positions of the back face. Since the characters printed on the first face of the printed circuit board are also printed in the reversed images in the immediately corresponding positions of the second face of the board, these characters can be used as indexes to find a particular position on the printed circuit board, and the first or second face can be instantly distinguished from the second or first face. The present invention also provides a method for the fabrication of a printed circuit board comprising the steps of printing on the first face of a substrate which has a circuit pattern formed on at least one of the first and second faces of the substrate with a first printing plate on which characters are disposed, preparing a second printing plate having the reversed character images by turning over the above first printing plate to reverse the normal characters, and printing the reversed character images on the second face of the substrate with the second printing plate.

Abstract translation: 一种印刷电路板，其具有形成在基板的第一和第二面中的至少一个上的电路图案，并且具有表示将被安装在印刷在基板的第一面和第二面上的所述基板上的部件的字符和符号，其中， 打印在第一面上的字符已经被打印在背面的相应位置的反转图像中。 由于打印在印刷电路板的第一面上的字符也印刷在板的第二面的紧接相应位置的反转图像中，所以这些字符可以用作在印刷电路板上找到特定位置的索引 并且第一或第二面可以立即与第二面或第一面区分开。 本发明还提供一种制造印刷电路板的方法，包括以下步骤：在基板的第一面上印刷，该基板具有形成在基板的第一和第二表面中的至少一个上的电路图案，并具有第一印刷 通过翻转上述第一印版来反转正常字符，通过第二印刷版印刷反转的字符图像在基板的第二面上来制作具有反转字符图像的第二印版。

公开(公告)号：US4668603A

公开(公告)日：1987-05-26

申请号：US878608

申请日：1986-06-26

Applicant: Harvey W. Taylor, Jr.

Inventor： Harvey W. Taylor, Jr.

IPC: H05K3/28 ,  G03F7/34 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06 ,  H05K3/34

CPC classification number: G03F7/34 ,  H05K1/0266 ,  H05K3/0079 ,  H05K2201/09936 ,  H05K2203/0514 ,  H05K2203/0537 ,  H05K2203/122 ,  H05K2203/161 ,  H05K3/28

Abstract: Nomenclature is applied to a soldermask surface employing a peel apart film prior to application of molten solder.

Abstract translation: 在施加熔融焊料之前，使用剥离膜将命名法应用于焊接表面。

公开(公告)号：US4088828A

公开(公告)日：1978-05-09

申请号：US662440

申请日：1976-03-01

Applicant: Yoshio Yamamoto ,  Masaki Sono ,  Masahiko Ekeuti

Inventor： Yoshio Yamamoto ,  Masaki Sono ,  Masahiko Ekeuti

IPC: H01R12/55 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K1/00

CPC classification number: H05K3/3452 ,  H05K1/0266 ,  H05K1/116 ,  H05K2201/09936 ,  H05K2203/0588 ,  H05K3/3447

Abstract: A printed circuit board wherein a conductor pattern is printed on an insulating base, first solder resist layers are formed on the surface of the conductor pattern remaining lands which are for soldering thereon, second solder resist layers for prevention of bridging for preventing bridging of solder are formed at least at portions where the gap between the lands is narrow, and thereby electronic parts such as an IC can be reliably assembled on the printed circuit board.

Abstract translation: 一种印刷电路板，其中导体图案印刷在绝缘基底上，第一阻焊层形成在用于焊接其上的导体图案剩余的焊盘的表面上，用于防止桥接以防止焊料桥接的第二阻焊层是 至少形成在台阶之间的间隙窄的部分，从而可以将电子部件如IC可靠地组装在印刷电路板上。

公开(公告)号：US3853564A

公开(公告)日：1974-12-10

申请号：US23086672

申请日：1972-03-01

Applicant: FOTEL INC

Inventor： BAKER E

IPC: H05K3/00 ,  G03C5/04

CPC classification number: H05K3/0002 ,  H05K2201/09936 ,  H05K2203/056

Abstract: A master grid layout sheet and methods of manufacture associated therewith are disclosed for use in graphic art work such as the layout and reproduction of printed circuits and the like. In typical printed circuit work precision art work and subsequent photographic reproduction thereof are normal intermediate processing steps. The master sheet includes a pattern, usually of orthogonal reference lines, printed thereon in a predetermined critical gray or neutral monotone. The monotone has a visual density such that the reference line pattern is visible to a draftsman but the light transmission density or opacity thereof is insufficient to cause the pattern to be reproduced in a controlled photographic reproduction of the master sheet.

Abstract translation: 公开了主网格布局表和与之相关联的制造方法用于图形艺术作品中，例如印刷电路的布局和再现等。 在典型的印刷电路工作中，精密艺术作品及其随后的照相再现是正常的中间处理步骤。 母片包括通常以正交参考线的图案，其印刷在预定的临界灰色或中性单调体中。 单调子具有视觉密度，使得参考线图案对于绘图员是可见的，但是其透光密度或不透明度不足以在母版的受控照相再现中导致图案再现。

公开(公告)号：US3272909A

公开(公告)日：1966-09-13

申请号：US40891164

申请日：1964-11-04

Applicant: AVCO CORP

Inventor： GEORGE BRUCK ,  FRENO JOHN F

IPC: H05K1/02 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K1/0266 ,  H05K3/4092 ,  H05K3/4611 ,  H05K2201/0108 ,  H05K2201/0382 ,  H05K2201/0397 ,  H05K2201/09354 ,  H05K2201/0969 ,  H05K2201/09936

公开(公告)号：US20240260173A1

公开(公告)日：2024-08-01

申请号：US18561206

申请日：2022-01-21

Applicant: NITTO DENKO CORPORATION

Inventor： Yusaku TAMAKI ,  Rihito FUKUSHIMA ,  Teppei NIINO

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K1/0266 ,  H05K3/0038 ,  H05K2201/09936

Abstract: A method for producing a wiring circuit board assembly sheet includes a marking step of forming a mark made of a recessed portion in a metal support board, and after the marking step, an insulating layer forming step of forming a base insulating layer on one surface in a thickness direction of the metal support board formed with the mark.