公开(公告)号：US09113574B2

公开(公告)日：2015-08-18

申请号：US14063052

申请日：2013-10-25

Applicant: IBIDEN CO., LTD.

Inventor： Kenji Sato ,  Masahiro Zanma

IPC: H05K1/00 ,  H05K1/18 ,  H05K3/46

CPC classification number: H05K1/186 ,  H05K3/4644 ,  H05K3/4697 ,  H05K2201/09827 ,  H05K2201/10015 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49146

Abstract: A wiring board with a built-in electronic component includes a core substrate having a cavity, an electronic component accommodated in the cavity of the core substrate and having a body portion and multiple conductive portions formed on a surface of the body portion, a filling resin filling the space formed in the cavity having the component positioned in the cavity, and an resin insulation layer formed on the core substrate such that the resin insulation layer is covering an opening of the cavity and a surface of the component. The core substrate has an inclination suppressing structure formed on one or more side walls forming the cavity such that the distance between the side wall forming the cavity and the component varies in a portion of the side wall having the inclination suppressing structure and a portion of the side wall other than the portion having the inclination suppressing structure.

Abstract translation: 具有内置电子部件的布线基板包括具有空腔的芯基板，容纳在芯基板的空腔中的电子部件，具有主体部和形成在主体部的表面上的多个导电部，填充树脂 填充形成在具有位于空腔中的部件的空腔中的空间，以及形成在芯基板上的树脂绝缘层，使得树脂绝缘层覆盖空腔的开口和部件的表面。 核心基板具有形成在形成空腔的一个或多个侧壁上的倾斜抑制结构，使得形成空腔的侧壁与部件之间的距离在具有倾斜抑制结构的侧壁的一部分中变化，并且部分 侧壁除了具有倾斜抑制结构的部分之外。

公开(公告)号：US20150223334A1

公开(公告)日：2015-08-06

申请号：US14600134

申请日：2015-01-20

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kiyoyuki NAKAGAWA

IPC: H05K1/11 ,  H01G4/30 ,  H01G4/008 ,  H05K1/18 ,  H05K1/09 ,  H01G4/012 ,  H01G4/12

CPC classification number: H05K1/111 ,  H01G2/065 ,  H01G4/005 ,  H01G4/008 ,  H01G4/012 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K1/09 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/10984 ,  H05K2203/0465 ,  H05K2203/048 ,  Y02P70/611 ,  Y02P70/613

Abstract: A mounted structure includes an electronic component including external electrodes, a wiring substrate including lands, and joint portions composed of a solder joint material and configured to join the external electrodes and the lands. The external electrodes respectively include coatings that cover a principal surface of a body, which is opposed to the wiring substrate, and coatings that cover end surfaces of the body, which are opposed to each other in the length direction. A distance De between the coatings in the length direction and a distance Dl between the lands in the length direction satisfy a condition of 0.91≦Dl/De≦1.09.

Abstract translation: 安装结构包括包括外部电极的电子部件，包括焊盘的布线基板和由焊接材料构成并且被配置为接合外部电极和焊盘的接合部分。 外部电极分别包括覆盖主体的与布线基板相对的主表面的涂层和覆盖主体的在长度方向上彼此相对的端表面的涂层。 在长度方向上的涂层与长度方向上的焊盘之间的距离D1的距离De满足0.91＆nlE; D1 / De＆nlE; 1.09的条件。

公开(公告)号：US20150221436A1

公开(公告)日：2015-08-06

申请号：US14549824

申请日：2014-11-21

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Takanobu KATSUYAMA ,  Yasunari NAKAMURA ,  Naoto MURANISHI ,  Masaaki TANIGUCHI ,  Takashi SAWADA

IPC: H01G2/06 ,  H01G4/012 ,  H01G4/30 ,  H05K1/11 ,  H05K1/18 ,  H01G4/12 ,  H01G4/248

CPC classification number: H01G2/065 ,  H01G4/012 ,  H01G4/232 ,  H05K1/111 ,  H05K1/181 ,  H05K3/3442 ,  H05K2201/09427 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/162 ,  Y02P70/611

Abstract: A first terminal electrode extends from a second principal surface onto first and second side surfaces and a first end surface such as not to reach a first principal surface. A second terminal electrode extends from the second principal surface onto the first and second side surfaces and a second end surface such as not to reach the first principal surface. A third terminal electrode extends from the second principal surface onto the first and second side surfaces such as not to reach the first principal surface.

Abstract translation: 第一端子电极从第二主表面延伸到第一和第二侧表面以及第一端面，例如不能到达第一主表面。 第二端子电极从第二主表面延伸到第一和第二侧表面以及第二端表面，例如不能到达第一主表面。 第三端子电极从第二主表面延伸到第一和第二侧表面上，例如不能到达第一主表面。

公开(公告)号：US09099242B2

公开(公告)日：2015-08-04

申请号：US13588696

申请日：2012-08-17

Applicant: Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

Inventor： Young Ghyu Ahn ,  Sang Soo Park ,  Min Cheol Park ,  Se Hwa Jeong

IPC: H05K1/16 ,  H01G4/005 ,  H05K1/02 ,  H01G4/30

CPC classification number: H01G4/005 ,  H01G4/30 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09427 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2045 ,  Y02P70/611

Abstract: A laminated chip electronic component includes: a ceramic body including internal electrodes and dielectric layers; external electrodes formed to cover both end portions of the ceramic body in a length direction; an active layer in which the internal electrodes are disposed in an opposing manner, while having the dielectric layers interposed therebetween, to form capacitance; and upper and lower cover layers formed on upper and lower portions of the active layer in a thickness direction, the lower cover layer having a thickness greater than that of the upper cover layer.

Abstract translation: 层叠芯片电子部件包括：陶瓷体，其包括内部电极和电介质层; 形成为在长度方向上覆盖陶瓷体的两端部的外部电极; 其中内部电极以相对的方式设置在其间插入电介质层的有源层以形成电容; 以及在有源层的厚度方向的上部和下部形成的上部和下部覆盖层，所述下部覆盖层的厚度大于上部覆盖层的厚度。

公开(公告)号：US09095073B2

公开(公告)日：2015-07-28

申请号：US13959949

申请日：2013-08-06

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kazuo Hattori ,  Isamu Fujimoto

IPC: H05K1/16 ,  H05K1/18 ,  H01G4/30 ,  H05K1/11 ,  H05K3/34 ,  H01G2/06 ,  H01G4/12 ,  H01G4/232

CPC classification number: H05K1/181 ,  H01G2/065 ,  H01G4/12 ,  H01G4/232 ,  H01G4/30 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2201/2036 ,  H05K2201/2045 ,  Y02P70/611 ,  Y02P70/613

Abstract: A mounting land structure and a mounting structure include land patterns to be bonded to outer electrodes of a laminated ceramic capacitor. Each of the land patterns includes a first conductor pattern and a second conductor pattern separated from each other in a width direction and a third conductor pattern connecting the first conductor pattern and the second conductor pattern. The first conductor pattern and the second conductor pattern include respective portions to be bonded to first ridgeline portions of the laminated ceramic capacitor provided with the outer electrodes. The third conductor pattern is arranged at a position overlapping the corresponding outer electrode as viewed in a height direction, when the laminated ceramic capacitor is mounted.

Abstract translation: 安装平台结构和安装结构包括与层压陶瓷电容器的外部电极接合的焊盘图案。 每个焊盘图案包括在宽度方向上彼此分离的第一导体图案和第二导体图案，以及连接第一导体图案和第二导体图案的第三导体图案。 第一导体图案和第二导体图案包括要被接合到设置有外部电极的层叠陶瓷电容器的第一脊线部分的各个部分。 当安装层叠陶瓷电容器时，第三导体图案被布置在与高度方向相对的相应的外部电极重叠的位置。

公开(公告)号：US09066422B2

公开(公告)日：2015-06-23

申请号：US13520980

申请日：2011-01-04

Applicant: Osamu Shimada

Inventor： Osamu Shimada

IPC: H05K7/06 ,  H05K1/02 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/18 ,  H05K3/46 ,  H01L23/31 ,  H05K3/40 ,  H01L23/00

CPC classification number: H05K1/023 ,  H01L21/486 ,  H01L23/3121 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5389 ,  H01L24/48 ,  H01L2224/04105 ,  H01L2224/24195 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/0224 ,  H05K1/186 ,  H05K3/4069 ,  H05K3/4614 ,  H05K3/4647 ,  H05K2201/0355 ,  H05K2201/10636 ,  H05K2203/061 ,  H05K2203/063 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: In an electronic component in which a semiconductor chip (semiconductor element) and a passive component are integrated on a multilayer wiring board and the semiconductor chip and the passive component constitute a feedback circuit, an input end and an output end of the semiconductor chip (semiconductor element) are electrically separated from each other. The electronic component includes the multilayer wiring board, the semiconductor chip disposed on the main surface of or inside the multilayer wiring board, and the passive component having a first terminal and a second terminal connected to the input end and the output end of the semiconductor chip respectively, and is configured such that a conductive member constituting the multilayer wiring board is located at a position where a distance from at least one of the first terminal and the second terminal is smaller than a distance between the first terminal and the second terminal.

Abstract translation: 在其中将半导体芯片（半导体元件）和无源部件集成在多层布线板上并且半导体芯片和无源部件构成反馈电路的电子部件中，半导体芯片（半导体）的输入端和输出端 元件）彼此电分离。 电子部件包括多层布线基板，设置在多层布线基板的主表面或内侧的半导体芯片，无源部件具有与半导体芯片的输入端和输出端连接的第一端子和第二端子 并且被构造为使得构成多层布线板的导电构件位于距离第一端子和第二端子中的至少一个的距离小于第一端子和第二端子之间的距离的位置处。

公开(公告)号：US20150173197A1

公开(公告)日：2015-06-18

申请号：US14453289

申请日：2014-08-06

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Suk Hyeon Cho ,  Yong Sam Lee ,  Jin O Yoo

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/00

CPC classification number: H05K1/185 ,  H01F17/0013 ,  H01F17/04 ,  H01F27/255 ,  H01F41/046 ,  H05K3/4602 ,  H05K2201/086 ,  H05K2201/1003 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/49075

Abstract: A printed circuit board having an inductor embedded therein may include a conductive coil part embedded in an insulating layer; and a magnetic material part integrally formed so as to enclose a vicinity of the conductive coil part. In the printed circuit board having the inductor embedded therein, a gap between coils is narrowed and coils having a high height and a narrow width are formed, whereby resistance may be decreased and a higher inductance value may be implemented in a narrow area.

Abstract translation: 具有嵌入其中的电感器的印刷电路板可以包括嵌入在绝缘层中的导电线圈部分; 以及整体形成为包围导电线圈部分附近的磁性材料部分。 在具有嵌入其中的电感器的印刷电路板中，线圈之间的间隙变窄，并且形成具有高高度和窄宽度的线圈，从而可以减小电阻并且可以在较窄的区域中实现更高的电感值。

公开(公告)号：US20150163916A1

公开(公告)日：2015-06-11

申请号：US14452785

申请日：2014-08-06

Applicant: Mitsubishi Electric Corporation

Inventor： Taichi OBARA ,  Rei YONEYAMA ,  Takami OTSUKI ,  Eiju SHITAMA

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/183 ,  H01L23/13 ,  H01L23/15 ,  H01L23/3735 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L2224/32225 ,  H01L2924/19105 ,  H05K1/11 ,  H05K1/111 ,  H05K1/186 ,  H05K1/188 ,  H05K3/3442 ,  H05K2201/09072 ,  H05K2201/09745 ,  H05K2201/10 ,  H05K2201/10174 ,  H05K2201/1059 ,  H05K2201/10636 ,  H05K2201/10651 ,  H05K2201/10674 ,  H05K2201/10689 ,  Y02P70/611 ,  Y02P70/613

Abstract: An electronic component mounting device includes an insulating substrate having a metal pattern formed thereon and a MELF electronic component. The MELF electronic component is fitted into a first receiving portion configured with the metal pattern and the insulating substrate exposed from a lacking portion of the metal pattern. The electronic component mounting device further includes a conductive member formed between the MELF electronic component and the metal pattern, and the conductive member is not formed between the MELF electronic component and the insulating substrate.

Abstract translation: 电子部件安装装置包括其上形成有金属图案的绝缘基板和MELF电子部件。 MELF电子部件装配到由金属图案构成的第一接收部分和从金属图案的缺少部分露出的绝缘基板。 电子部件安装装置还包括形成在MELF电子部件和金属图案之间的导电部件，并且在MELF电子部件和绝缘基板之间不形成导电部件。

公开(公告)号：US09044830B2

公开(公告)日：2015-06-02

申请号：US14141800

申请日：2013-12-27

Applicant: IBIDEN CO., LTD.

Inventor： Yukinobu Mikado ,  Yuki Tanaka

IPC: H05K1/11 ,  B23K26/00 ,  B23K26/38 ,  H05K3/46 ,  B23K26/08 ,  H05K3/00 ,  H05K1/18

CPC classification number: B23K26/383 ,  B23K26/08 ,  B23K26/384 ,  B23K26/386 ,  B23K26/389 ,  H05K1/185 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4697 ,  H05K2201/10636 ,  H05K2203/107 ,  Y02P70/611 ,  Y10T29/49135

Abstract: A method for forming cavity in substrate includes setting start position on closed loop line having circumference L for substrate, consecutively irradiating laser from laser device upon board for the substrate such that holes are formed, and moving the device in loop from the start position along the line such that penetrating hole is formed through the board. The start position of first loop is set as base position, the moving includes shifting the start position by distance d after each loop and controlling such that the moving satisfies p=Σdi, m≅L/p and M=m×n, where i=1 to n, n represents number of loops, p represents pitch of the holes, m represents number of the holes in loop, Σdi is distance from the base position for the start position after i-th loop, and M is number of the holes by the loops.

Abstract translation: 在衬底中形成空腔的方法包括：在具有用于衬底的圆周L的闭环线上设置开始位置，从基板上的激光装置连续照射激光，使得形成孔，并且沿着沿着衬底的起始位置循环移动装置 使得穿过该板形成穿透孔。 将第一循环的起始位置设定为基准位置，移动包括在每个回路之后移动开始位置距离d，并且控制使移动满足p =＆Sgr; di，m≅L/ p和M = m×n， 其中i = 1至n，n表示环数，p表示孔的间距，m表示环中的孔数，＆lt; di是与第i个回路之后的起始位置的基准位置的距离，M 是环的数目。

公开(公告)号：US20150116892A1

公开(公告)日：2015-04-30

申请号：US14257806

申请日：2014-04-21

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Min Cheol PARK ,  Sang Soo PARK

IPC: H01G4/40 ,  H05K1/16

CPC classification number: H01G4/40 ,  H01G2/06 ,  H01G4/232 ,  H01G4/30 ,  H05K1/0231 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/1006 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A multilayer ceramic capacitor may include: a ceramic body including a plurality of dielectric layers; a capacitor part including a first internal electrode formed in the ceramic body and a second internal electrode formed in the ceramic body; a resistor part including a first internal connection conductor formed in the ceramic body and a second internal connection conductor formed in the ceramic body; a first dummy electrode formed in the ceramic body and a second dummy electrode formed in the ceramic body; and first to sixth external electrodes and the first and second internal connection conductors. The capacitor part and the resistor part may be connected in series to each other.

Abstract translation: 多层陶瓷电容器可以包括：陶瓷体，其包括多个电介质层; 电容器部分，包括形成在陶瓷体中的第一内部电极和形成在陶瓷体中的第二内部电极; 电阻部分，包括形成在陶瓷体中的第一内部连接导体和形成在陶瓷体中的第二内部连接导体; 形成在陶瓷体中的第一虚拟电极和形成在陶瓷体中的第二虚拟电极; 以及第一至第六外部电极以及第一和第二内部连接导体。 电容器部分和电阻器部分可以彼此串联连接。