公开(公告)号：US20170031436A1

公开(公告)日：2017-02-02

申请号：US14856563

申请日：2015-09-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  Wei-Yung Chen ,  Yu-An Chen

IPC: G06F3/01

CPC classification number: G06F3/013 ,  A61B3/11

Abstract: An eye-width detector, a memory storage device and an eye-width detection method of data signal are provided. The eye-width detector includes a phase interpolator, a calibration circuit and an eye-width detection circuit. The phase interpolator receives a first clock signal and a phase control signal and output a second clock signal. The calibration circuit receives the first clock signal and the second clock signal and output a first control signal. The eye-width detection circuit receive the data signal, the first clock signal and the second clock signal and generate a first sampling value and a second sampling value. If the first sampling value and the second sampling value do not match a first condition, the eye-width detection circuit outputs a second control signal; otherwise, outputs eye-width information of the data signal. Accordingly, the efficiency of the eye-width detection may be improved.

Abstract translation: 提供了眼宽检测器，存储器存储装置和数据信号的眼宽检测方法。 眼宽检测器包括相位插值器，校准电路和眼睛宽度检测电路。 相位插值器接收第一时钟信号和相位控制信号并输出​​第二时钟信号。 校准电路接收第一时钟信号和第二时钟信号并输出​​第一控制信号。 眼宽检测电路接收数据信号，第一时钟信号和第二时钟信号，并产生第一采样值和第二采样值。 如果第一采样值和第二采样值与第一条件不匹配，则眼宽检测电路输出第二控制信号; 否则输出数据信号的眼宽信息。 因此，可以提高眼宽检测的效率。

公开(公告)号：US20170024136A1

公开(公告)日：2017-01-26

申请号：US14846830

申请日：2015-09-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0659 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.

Abstract translation: 提供存储器管理方法，存储器控制电路单元和存储器存储装置。 在一个示例性实施例中，存储器管理方法包括：接收第一写入命令和首先写入数据并获得第一个数字; 编程所述第一写入数据和移动存储在多个第一物理编程单元中的第一存储数据，其中所述第一物理编程单元的总数符合所述第一数量; 接收第二写入命令和第二写入数据并获得第二个数字; 编程所述第二写数据和移动存储在多个第二物理编程单元中的第二存储数据，其中所述第二物理编程单元的总数符合所述第二数目; 并擦除至少一个物理擦除单元。 因此，可以减少数据合并过程中的系统资源浪费。

公开(公告)号：US20170019116A1

公开(公告)日：2017-01-19

申请号：US15261878

申请日：2016-09-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei-Yung Chen ,  Yu-Chiang Liao

IPC: H03L7/091

CPC classification number: H03L7/091 ,  G11C7/1084 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0802 ,  H03L7/0807 ,  H03L7/087 ,  H03L7/099 ,  H03L7/1072 ,  H03L7/22 ,  H04L7/0004 ,  H04L7/033

Abstract: A clock and data recovery circuit module and a phase lock method are provided. The module includes a phase detection circuit, a converter circuit and a voltage control oscillation circuit. The phase detection circuit is configured to detect a phase difference between a data signal and a feedback clock. The converter circuit is coupled to the phase detection circuit and configured to output a first phase control voltage and a second phase control voltage according to the phase difference. The voltage control oscillation circuit is coupled to the converter circuit and configured to receive the first phase control voltage and the second phase control voltage and output the feedback clock according to the first phase control voltage and the second phase control voltage.

Abstract translation: 提供时钟和数据恢复电路模块和锁相方法。 该模块包括相位检测电路，转换器电路和电压控制振荡电路。 相位检测电路被配置为检测数据信号和反馈时钟之间的相位差。 转换器电路耦合到相位检测电路，并被配置为根据相位差输出第一相位控制电压和第二相位控制电压。 电压控制振荡电路耦合到转换器电路，并被配置为接收第一相位控制电压和第二相位控制电压，并根据第一相位控制电压和第二相位控制电压输出反馈时钟。

公开(公告)号：US20160378384A1

公开(公告)日：2016-12-29

申请号：US15261881

申请日：2016-09-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chien-Fu Lee

IPC: G06F3/06 ,  H04W12/06 ,  H04W4/00 ,  H04L29/06

CPC classification number: G06F3/0622 ,  G06F3/0659 ,  G06F3/067 ,  G06F21/31 ,  G06F21/6218 ,  G06F21/78 ,  G06F2221/2143 ,  G06F2221/2153 ,  H04L63/0492 ,  H04L63/083 ,  H04W4/80 ,  H04W12/06 ,  H04W12/08

Abstract: A data accessing method and system for a memory storage apparatus are provided. The method includes: performing a near field communication between a memory storage apparatus and an electronic apparatus, and receiving a first password from the electronic apparatus by the memory storage device in the near field communication. The method also includes: recording the first password in a memory unit of the memory storage apparatus. The method further includes: when the memory storage apparatus is not connected to the electronic apparatus or a host in a predetermined time after the memory storage apparatus receives the first password, deleting the first password recorded in the memory unit; and when the first password recorded in the memory unit is the same as a second password in the memory storage apparatus, allowing the electronic apparatus or the host to access the memory storage apparatus by the memory storage apparatus.

Abstract translation: 提供了一种用于存储器存储装置的数据访问方法和系统。 该方法包括：在存储器存储装置和电子设备之间执行近场通信，并且在近场通信中由存储器存储装置从电子设备接收第一密码。 该方法还包括：将第一密码记录在存储器存储装置的存储单元中。 该方法还包括：当存储器存储装置在存储器存储装置接收到第一密码之后的预定时间内没有连接到电子设备或主机时，删除记录在存储器单元中的第一密码; 并且当存储器单元中记录的第一密码与存储器存储装置中的第二密码相同时，允许电子设备或主机由存储器存储装置访问存储器存储装置。

公开(公告)号：US20160350179A1

公开(公告)日：2016-12-01

申请号：US14818323

申请日：2015-08-05

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C16/26 ,  G11C16/08 ,  H03M13/45 ,  G11C29/52

Abstract: A decoding method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a plurality of first memory cells according to a first soft-decision read voltage level to obtain a first soft-decision coding unit belonging to a block code; performing a first soft-decision decoding procedure for the first soft-decision coding unit; if the first soft-decision decoding procedure fails, reading the first memory cells according to a second soft-decision read voltage level to obtain a second soft-decision coding unit belonging to the block code, where a difference value between the first soft-decision read voltage level and the second soft-decision read voltage level is related to a wear degree of the first memory cells; and performing a second soft-decision decoding procedure for the second soft-decision coding unit. Accordingly, a decoding efficiency of block codes may be improved.

Abstract translation: 提供了解码方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一软判决读取电压电平读取多个第一存储器单元以获得属于块码的第一软判决编码单元; 对所述第一软判决编码单元执行第一软判决解码过程; 如果第一软判决解码过程失败，则根据第二软判决读取电压电平读取第一存储器单元以获得属于块代码的第二软判决编码单元，其中第一软判决解码程序 读取电压电平，第二软判决读取电压电平与第一存储器单元的磨损程度相关; 以及对所述第二软判决编码单元执行第二软判决解码过程。 因此，可以提高块码的解码效率。

公开(公告)号：US09496041B2

公开(公告)日：2016-11-15

申请号：US14692759

申请日：2015-04-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  An-Cheng Liu ,  Siu-Tung Lam

IPC: G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3459

Abstract: A memory programming method for a rewritable non-volatile memory module having memory cells is provided. The memory programming method includes: performing a first programming process on the memory cells according to write data and obtaining a first programming result of the first programming process; grouping the memory cells into programming groups according to the first programming result; and performing a second programming process on the memory cells according to the write data. The second programming process includes: programming a first programming group among the programming groups by using a first program voltage; and programming a second programming group among the programming groups by using a second program voltage. The first program voltage and the second program voltage are different. Moreover, a memory control circuit unit and a memory storage device are provided.

Abstract translation: 提供了一种用于具有存储器单元的可重写非易失性存储器模块的存储器编程方法。 存储器编程方法包括：根据写数据对存储器单元执行第一编程处理并获得第一编程处理的第一编程结果; 根据第一编程结果将存储器单元分组成编程组; 以及根据写入数据对存储器单元执行第二编程处理。 第二编程过程包括：通过使用第一编程电压对编程组中的第一编程组进行编程; 以及通过使用第二编程电压来编程所述编程组中的第二编程组。 第一编程电压和第二编程电压不同。 此外，提供存储器控制电路单元和存储器存储装置。

公开(公告)号：US20160314040A1

公开(公告)日：2016-10-27

申请号：US14736284

申请日：2015-06-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Chih-Kang Yeh ,  Chang-Guang Lin

IPC: G06F11/10 ,  H03M13/29 ,  G06F3/06 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/1012 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/05 ,  H03M13/09 ,  H03M13/2906

Abstract: A data accessing method for a memory storage apparatus is provided. The method includes using a first check code circuit to generate a first check code corresponding to a first data stream and generating a first data set based on the first data stream and the first check code. The method also includes using a second check code circuit to obtain the first data stream and the first check code from the first data set and check the first data stream according to the first check code. The method still includes using a third check code circuit to generate a second check code according to the checked first data stream and generating a data frame based on the checked first data stream and the second check code and thereby programming the data frame into a physical programming unit.

Abstract translation: 提供了一种用于存储器存储装置的数据存取方法。 该方法包括使用第一校验码电路来生成与第一数据流相对应的第一校验码，并且基于第一数据流和第一校验码产生第一数据集。 该方法还包括使用第二校验码电路从第一数据集获得第一数据流和第一校验码，并根据第一校验码检查第一数据流。 该方法还包括使用第三检验码电路根据所检查的第一数据流生成第二检验码，并且基于所检查的第一数据流和第二检验码产生数据帧，从而将数据帧编程为物理编程 单元。

公开(公告)号：US20160306693A1

公开(公告)日：2016-10-20

申请号：US14745472

申请日：2015-06-22

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Tien-Ching Wang ,  Kuo-Hsin Lai

IPC: G06F11/10 ,  G11C29/50

CPC classification number: G06F11/1048 ,  G11C29/021 ,  G11C29/028 ,  G11C29/44 ,  G11C2029/5004

Abstract: A read voltage level estimating method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first region of a rewritable non-volatile memory module according to a first read voltage level to obtain a first encoding unit which belongs to a block code; performing a first decoding procedure on the first encoding unit and recording first decoding information; reading the first region according to a second read voltage level to obtain a second encoding unit which belongs to the block code; performing a second decoding procedure on the second encoding unit and recording second decoding information; and estimating and obtaining a third read voltage level according to the first decoding information and the second decoding information. Accordingly, a management ability of the rewritable non-volatile memory module adopting the block code may be improved.

Abstract translation: 提供读取电压电平估计方法，存储器存储装置和存储器控制电路单元。 该方法包括：根据第一读取电压电平读取可重写非易失性存储器模块的第一区域，以获得属于块码的第一编码单元; 对所述第一编码单元执行第一解码过程并记录第一解码信息; 根据第二读取电压电平读取第一区域以获得属于块码的第二编码单元; 对所述第二编码单元执行第二解码过程并记录第二解码信息; 以及根据第一解码信息和第二解码信息估计并获得第三读取电压电平。 因此，可以提高采用块代码的可重写非易失性存储器模块的管理能力。

公开(公告)号：US20160283510A1

公开(公告)日：2016-09-29

申请号：US14723466

申请日：2015-05-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Feng Yeh

IPC: G06F17/30

CPC classification number: G06F17/30091 ,  G06F3/062 ,  G06F3/0638 ,  G06F3/0643 ,  G06F3/0679

Abstract: A storage device management method, a storage device management system and a memory storage device are provided. The method includes establishing multiple first temporary files in a first directory before receiving a setting instruction from a host, wherein the first temporary files are stored in multiple consecutive clusters of a file system and an operating system of the host is unable to access files in the first directory. The method further includes receiving the setting instruction from the host, wherein the setting instruction instructs to configure a temporary file directory in a second directory and the operating system of the host is able to access files in the second directory. The method further includes linking a cluster number of the consecutive clusters storing the first temporary files to the temporary file directory in the directory area corresponding to the file system.

Abstract translation: 提供存储设备管理方法，存储设备管理系统和存储器存储设备。 该方法包括在接收来自主机的设置指令之前在第一目录中建立多个第一临时文件，其中第一临时文件存储在文件系统的多个连续的集群中，并且主机的操作系统不能访问 第一个目录 该方法还包括从主机接收设置指令，其中设置指令指示在第二目录中配置临时文件目录，并且主机的操作系统能够访问第二目录中的文件。 该方法还包括将存储第一临时文件的连续簇的簇数与对应于文件系统的目录区中的临时文件目录相链接。

公开(公告)号：US09449660B2

公开(公告)日：2016-09-20

申请号：US14309879

申请日：2014-06-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jen-Chu Wu ,  An-Chung Chen

IPC: G11C7/22 ,  H03L7/091 ,  H03L7/08 ,  H03L7/081 ,  G11C7/10

CPC classification number: G11C7/22 ,  G11C7/1093 ,  H03L7/0805 ,  H03L7/0812

Abstract: A sampling circuit module, a memory control circuit unit, and a method for sampling data are provided. The sampling circuit module includes a state machine circuit, a first delay line circuit, a second delay line circuit and a delay signal output circuit. In response to a first control signal, the state machine circuit outputs a second control signal and/or a third control signal. The first delay line circuit is configured to receive a reference clock signal and the second control signal to output a first delay clock signal. The second delay line circuit is configured to receive the reference clock signal and the third control signal to output a second delay clock signal. The delay signal output circuit is configured to receive the first delay clock signal and the second delay clock signal to output a third delay clock signal.

Abstract translation: 提供采样电路模块，存储器控制电路单元和数据采样方法。 采样电路模块包括状态机电路，第一延迟线电路，第二延迟线电路和延迟信号输出电路。 响应于第一控制信号，状态机电路输出第二控制信号和/或第三控制信号。 第一延迟线电路被配置为接收参考时钟信号和第二控制信号以输出第一延迟时钟信号。 第二延迟线电路被配置为接收参考时钟信号和第三控制信号以输出第二延迟时钟信号。 延迟信号输出电路被配置为接收第一延迟时钟信号和第二延迟时钟信号以输出第三延迟时钟信号。