公开(公告)号：US20100326512A1

公开(公告)日：2010-12-30

申请号：US12740425

申请日：2008-10-16

Applicant: Harry Berek ,  Alexander Paul ,  Steffen Schmidt ,  Lothar Herlitze ,  Hansjoerg Weis ,  Karl Haeuser

Inventor： Harry Berek ,  Alexander Paul ,  Steffen Schmidt ,  Lothar Herlitze ,  Hansjoerg Weis ,  Karl Haeuser

IPC: H01L31/0224 ,  H01L31/18

CPC classification number: H01C1/14 ,  C23C24/04 ,  C23C28/321 ,  C23C28/322 ,  C23C28/3225 ,  C23C28/34 ,  C23C28/345 ,  C23C28/3455 ,  H01G4/228 ,  H01L31/022425 ,  H01L31/0296 ,  H01L31/0322 ,  H01L31/03685 ,  H01L31/03762 ,  H01L31/0392 ,  H01L31/03923 ,  H01L31/03925 ,  H05K1/0306 ,  H05K3/4007 ,  H05K3/467 ,  H05K2201/0367 ,  H05K2203/1344 ,  Y02E10/541 ,  Y02E10/545 ,  Y02E10/548 ,  Y02P70/521

Abstract: The invention relates to a layer system comprising a contact element (5) and a substrate (1). A multilayer system (14) that is disposed on the substrate (1) has at least one top layer (3; 4) and a bottom layer (2; 3) as well as a contact element (5) which penetrates the at least one top layer (3; 4) and contacts the bottom layer (2; 3). The invention further relates to a method for producing a contact element (5) of a multi-layer system (14).

Abstract translation: 本发明涉及包括接触元件（5）和基底（1）的层系统。 设置在基板（1）上的多层系统（14）具有至少一个顶层（3; 4）和底层（2; 3）以及穿透至少一个的接触元件（5） 顶层（3; 4）并与底层（2; 3）接触。 本发明还涉及一种用于制造多层系统（14）的接触元件（5）的方法。

公开(公告)号：US20100253375A1

公开(公告)日：2010-10-07

申请号：US12418438

申请日：2009-04-03

Applicant: Treliant Fang ,  Michael Harburn ,  Onnik Yaglioglu

Inventor： Treliant Fang ,  Michael Harburn ,  Onnik Yaglioglu

IPC: G01R31/02 ,  H01R13/02 ,  B32B7/00 ,  B82B1/00 ,  B82B3/00

CPC classification number: G01R3/00 ,  B81C1/00031 ,  G01R1/0483 ,  G01R1/06744 ,  G01R1/07314 ,  H05K3/4007 ,  H05K2201/026 ,  H05K2201/0323 ,  H05K2201/0367 ,  H05K2201/10977 ,  H05K2203/0338 ,  Y10T29/49147 ,  Y10T29/49204 ,  Y10T29/49208 ,  Y10T29/4921 ,  Y10T29/49222 ,  Y10T428/24174

Abstract: A technique for anchoring carbon nanotube columns to a substrate can include use of a filler material placed onto the surface of the substrate into area between the columns and surrounding a base portion of each of the columns.

Abstract translation: 用于将碳纳米管柱锚定到基底的技术可以包括使用放置在基底表面上的填充材料到列之间的区域并围绕每个柱的基部。

公开(公告)号：US07794234B2

公开(公告)日：2010-09-14

申请号：US12315305

申请日：2008-12-02

Applicant: Naoya Kitajima ,  Seiya Takahashi ,  Katsumi Arai

Inventor： Naoya Kitajima ,  Seiya Takahashi ,  Katsumi Arai

IPC: H01R12/00

CPC classification number: H05K1/118 ,  H01R12/716 ,  H01R13/2414 ,  H05K3/0058 ,  H05K3/027 ,  H05K3/365 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09172 ,  H05K2201/09663 ,  H05K2203/0369

Abstract: The present invention provides a connector configured to electrically connect two connection objects. The connector comprises an elastic member having a surface and a conductive film placed on the surface of the elastic member. The conductive film comprises two contact portions to be brought into contact with the connection objects, respectively, and a connect portion connecting the contact portions. Each of the contact portions comprises projections and a drainage arranged, at least in part, between the projections.

Abstract translation: 本发明提供一种被配置为电连接两个连接对象的连接器。 连接器包括具有放置在弹性构件的表面上的表面和导电膜的弹性构件。 导电膜包括分别与连接对象接触的两个接触部分和连接接触部分的连接部分。 每个接触部分包括至少部分地在突起之间布置的突起和排水。

公开(公告)号：US07791197B2

公开(公告)日：2010-09-07

申请号：US12068593

申请日：2008-02-08

Applicant: Daisuke Mizutani

Inventor： Daisuke Mizutani

IPC: H01L23/488

CPC classification number: H05K3/4007 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/10152 ,  H01L2224/13099 ,  H01L2224/81192 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/30105 ,  H05K1/113 ,  H05K3/423 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09563 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0733 ,  Y10T29/49147 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A semiconductor device has a semiconductor element having a plurality of connection terminals, a circuit substrate electrically connected with the semiconductor element; and a connecting member arranged between the semiconductor element and the circuit substrate having a plurality of conductive projections each having a columnar portion, each of columnar portions are connected with each of connection terminals, a cross section of the columnar portion along a plane parallel to a surface of the semiconductor element being smaller than a surface area of each of connection terminals of the semiconductor element.

Abstract translation: 半导体器件具有具有多个连接端子的半导体元件，与半导体元件电连接的电路基板; 以及布置在所述半导体元件和所述电路基板之间的连接构件，所述连接构件具有多个具有柱状部分的导电突起，每个所述柱状部分与每个连接端子连接，所述柱状部分沿着平行于 半导体元件的表面小于半导体元件的每个连接端子的表面积。

公开(公告)号：US20100218986A1

公开(公告)日：2010-09-02

申请号：US12685716

申请日：2010-01-12

Applicant: Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

Inventor： Toru Furuta ,  Kotaro Takagi ,  Michio Ido ,  Fumitaka Takagi

IPC: H05K1/11 ,  B23K31/02

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49866 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/108 ,  H05K3/3484 ,  H05K3/4644 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2203/0369 ,  H05K2203/043 ,  Y02P70/611 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/49156 ,  H01L2224/0401

Abstract: A method for manufacturing a printed wiring board includes forming a metal film on a surface of an insulative board, a plating resist on the metal film, and a plated-metal film on the metal film exposed from the plating resist, covering a portion of the plated-metal film with an etching resist, etching to reduce thickness of the plated-metal film exposed from the etching resist, removing the resists, and forming a wiring having a pad and a conductive circuit thinner than the pad by removing the metal film exposed through the removing of the plating resist, a solder-resist layer on the surface of the board and wiring, in the layer an opening exposing the pad and a portion of the circuit contiguous to the pad, a solder film on the pad and portion of the circuit exposed through the opening, and a solder bump on the pad by solder reflow.

Abstract translation: 一种制造印刷电路板的方法，包括在绝缘板的表面上形成金属膜，在金属膜上形成电镀抗蚀剂，以及在电镀抗蚀剂暴露的金属膜上的镀金属膜，覆盖一部分 具有抗蚀剂的镀金属膜，蚀刻以减少从抗蚀剂暴露的镀金属膜的厚度，去除抗蚀剂，以及通过除去暴露的金属膜，形成具有焊盘和比焊盘更薄的导电电路的布线 通过去除电镀抗蚀剂，在基板和布线的表面上形成阻焊层，在该层中，露出焊盘的开口和与焊盘相邻的电路的一部分，焊盘上的焊料膜和 通过开口暴露的电路，以及通过焊料回流焊盘上的焊料凸块。

公开(公告)号：US20100203747A1

公开(公告)日：2010-08-12

申请号：US12576252

申请日：2009-10-09

Applicant: NAN HU ,  HAN-MING ZHANG

Inventor： NAN HU ,  HAN-MING ZHANG

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H01R12/7076 ,  H01R12/772 ,  H05K1/118 ,  H05K1/189 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/091 ,  H05K2201/10189 ,  H05K2201/10393

Abstract: A flexible printed circuit board (20) for electrically connecting an insulator substrate (21) and a plurality of elongate conductors (21a) laminated over the insulator substrate by an upper layer. The conductor has a contact engaging portion (211a) exposed over the insulator substrate at end thereof. The contact engaging portion (211a) defines an embossed portion (212) for engaging against the mating component.

Abstract translation: 一种柔性印刷电路板（20），用于通过上层电绝缘基板（21）和层压在绝缘体基板上的多个细长导体（21a）电连接。 导体具有在绝缘体基板的端部露出的接触接合部分（211a）。 接触接合部分（211a）限定用于与配合部件接合的压花部分（212）。

公开(公告)号：US07765686B2

公开(公告)日：2010-08-03

申请号：US11908731

申请日：2006-03-02

Applicant: Akishige Murakami ,  Ikue Kawashima ,  Yoshikazu Akiyama

Inventor： Akishige Murakami ,  Ikue Kawashima ,  Yoshikazu Akiyama

IPC: H05K3/20

CPC classification number: G02F1/136227 ,  H05K3/1225 ,  H05K3/125 ,  H05K3/4007 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4664 ,  H05K2201/0367 ,  H05K2203/0126 ,  H05K2203/013 ,  H05K2203/1105 ,  Y10T29/49128 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49826

Abstract: A method of manufacturing a multilayer wiring structure is disclosed. The method comprises a step of forming a via post on a first metal wiring element, a step of printing an interlayer insulation film on the first metal wiring element, with use of a screen mask having a non-ejection area slightly larger than a head of the via post, such that the interlayer insulation film has an upper surface at the level lower than the head of the via post, while generally aligning the non-ejection area with the head of the via post, a step of curing the interlayer insulation film, and a step of forming a second metal wiring element in contact with the via post on the interlayer insulation film such that the first metal wiring element and the second metal wiring element are connected through the via post.

Abstract translation: 公开了一种制造多层布线结构的方法。 该方法包括在第一金属布线元件上形成通孔的步骤，在第一金属布线元件上印刷层间绝缘膜的步骤，使用具有略大于 所述通孔使得所述层间绝缘膜具有比所述通孔的头部低的水平面的上表面，同时大致将所述非喷射区域与所述通孔的头部对准，所述层间绝缘膜的固化步骤 以及在所述层间绝缘膜上形成与所述通孔接触的第二金属配线元件的步骤，使得所述第一金属配线元件和所述第二金属配线元件通过所述通孔连接。

公开(公告)号：US07759795B2

公开(公告)日：2010-07-20

申请号：US11850576

申请日：2007-09-05

Applicant: Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Chul-Yong Jang ,  Hyun-Jong Woo

Inventor： Young-Lyong Kim ,  Young-Shin Choi ,  Jong-Gi Lee ,  Kun-Dae Yeom ,  Chul-Yong Jang ,  Hyun-Jong Woo

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H05K3/4084 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K3/38 ,  H05K3/4007 ,  H05K3/4038 ,  H05K3/4647 ,  H05K3/4652 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0382 ,  H05K2201/09481 ,  H05K2201/0969 ,  H05K2201/2072 ,  H05K2203/0195 ,  H05K2203/0733 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: Provided is a printed circuit board having a bump interconnection structure that improves reliability between interconnection layers. Also provided is a method of fabricating the printed circuit board and semiconductor package using the printed circuit board. According to one embodiment, the printed circuit board includes a plurality of bumps formed on a resin layer between a first interconnection layer and a second interconnection layer. The second interconnection layer includes insertion holes corresponding to upper portions of the bumps so that the upper portions of the bumps protrude from the second interconnection layer. The upper portion of at least one of the bumps includes a rivet portion having a diameter greater that the diameter of the corresponding insertion hole to reliably interconnect the first and second interconnection layers.

Abstract translation: 提供了具有提高互连层之间的可靠性的凸块互连结构的印刷电路板。 还提供了使用印刷电路板制造印刷电路板和半导体封装的方法。 根据一个实施例，印刷电路板包括形成在第一互连层和第二互连层之间的树脂层上的多个凸点。 第二互连层包括对应于凸起的上部的插入孔，使得凸起的上部从第二互连层突出。 至少一个凸块的上部包括具有大于相应插入孔的直径的直径的铆钉部分，以可靠地互连第一和第二互连层。

公开(公告)号：US07754598B2

公开(公告)日：2010-07-13

申请号：US12068256

申请日：2008-02-05

Applicant: Wei-Hung Lin ,  Zao-Kuo Lai

Inventor： Wei-Hung Lin ,  Zao-Kuo Lai

IPC: H01L21/4763

CPC classification number: H05K3/4682 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/205 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/1105 ,  H01L2924/00

Abstract: Method for making a coreless packaging substrate are disclosed in the present invention. The coreless packaging substrate is made by first providing a metal adhesion layer having a melting point lower than that of the substrate, and removing a core board connected with the substrate therefrom through melting the metal adhesion layer. In addition, the disclosed packaging substrate further includes a circuit built-up structure of which has the electrical pads embedded under a surface. The disclosed packaging substrate can achieve the purposes of reducing the thickness, increasing circuit layout density, and facilitating the manufacturing of the substrate.

Abstract translation: 制造无芯封装基板的方法在本发明中公开。 无芯封装基板通过首先提供熔点低于基板的金属粘附层，并且通过熔化金属粘合层来除去与基板相连的芯板。 此外，所公开的封装基板还包括电路组合结构，其中电垫嵌入在表面下。 所公开的封装基板可以实现减小厚度，增加电路布局密度以及促进基板的制造的目的。

公开(公告)号：US07749887B2

公开(公告)日：2010-07-06

申请号：US11958842

申请日：2007-12-18

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L21/50 ,  H01L21/44

CPC classification number: H01L24/14 ,  H01L21/4846 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1012 ,  H01L2224/13012 ,  H01L2224/13016 ,  H01L2224/13019 ,  H01L2224/13023 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/73103 ,  H01L2224/73204 ,  H01L2224/81136 ,  H01L2224/81138 ,  H01L2224/8114 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81208 ,  H01L2224/81801 ,  H01L2224/83192 ,  H01L2224/83194 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/20105 ,  H01L2924/20106 ,  H05K3/06 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2201/10977 ,  H05K2203/0315 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012

Abstract: A method is disclosed which includes forming a layer of conductive material above a substrate, forming a masking layer above the layer of conductive material, performing a first etching process on the layer of conductive material with the masking layer in place, removing the masking layer and, after removing the masking layer, performing an isotropic etching process on the layer of conductive material to thereby define a plurality of piercing bond structures positioned on the substrate.

Abstract translation: 公开了一种方法，其包括在衬底上形成导电材料层，在导电材料层之上形成掩模层，在掩蔽层就位的导电材料层上执行第一蚀刻工艺，去除掩模层和 在去除掩模层之后，对导电材料层进行各向同性蚀刻处理，从而限定位于基板上的多个穿孔接合结构。