公开(公告)号：US20070262467A1

公开(公告)日：2007-11-15

申请号：US10588401

申请日：2005-02-03

Applicant: Christian Birzer ,  Jens Pohl

Inventor： Christian Birzer ,  Jens Pohl

IPC: H01L23/48 ,  H01L21/66

CPC classification number: H01L23/49838 ,  H01L22/32 ,  H01L23/3128 ,  H01L24/48 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48235 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0101 ,  H01L2924/01021 ,  H01L2924/01032 ,  H01L2924/01052 ,  H01L2924/01068 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0293 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09663 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device having a semiconductor chip stack on a rewiring plate is disclosed. In one embodiment, the device includes an external contact area having a plurality of external contact area regions which are physically separate from one another is arranged on the underside. The individual external contact area regions are assigned to the individual semiconductor chips in the semiconductor chip stack. The external contact regions of an individual external contact area have a common external contact which electrically connects the external contact area regions.

Abstract translation: 公开了一种在再布线板上具有半导体芯片堆叠的半导体器件。 在一个实施例中，该装置包括具有彼此物理分离的多个外部接触区域的外部接触区域布置在下侧。 各个外部接触区域被分配给半导体芯片堆叠中的各个半导体芯片。 单个外部接触区域的外部接触区域具有电连接外部接触区域区域的公共外部接触。

公开(公告)号：US07294791B2

公开(公告)日：2007-11-13

申请号：US10953923

申请日：2004-09-29

Applicant: Charles E. Danoski ,  Irving Memis ,  Steven G. Rosser

Inventor： Charles E. Danoski ,  Irving Memis ,  Steven G. Rosser

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H01L23/66 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01087 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/093 ,  H05K2201/09627 ,  H05K2201/09663 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155

Abstract: A circuitized substrate designed to substantially eliminate impedance disruptions during passage of signals through signal lines of the substrate's circuitry. The substrate includes a first conductive layer with a plurality of conductors on which an electrical component may be positioned and electrically coupled. The pads are coupled to signal lines (e.g., using thru-holes) further within the substrate and these signal lines are further coupled to a second plurality of conductive pads located even further within the substrate. The signal lines are positioned so as to lie between the substrate's first conductive layer and a voltage plane within a third conductive layer below the second conductive layer including the signal lines. A second voltage plane may be used adjacent the first voltage plane of the third conductive layer. Thru-holes may also be used to couple the signal lines coupled to the first conductors to a second plurality of conductors which form part of the third conductive layer. A method of making the substrate, and an electrical assembly and information handling system (e.g., computer) utilizing the substrate are also disclosed.

Abstract translation: 电路化基板被设计为基本上消除信号通过基板电路的信号线时的阻抗中断。 衬底包括具有多个导体的第一导电层，电组件可以在其上定位和电耦合。 这些焊盘在衬底内进一步耦合到信号线（例如，使用通孔），并且这些信号线还被进一步耦合到位于衬底内的另外多个导电衬垫。 信号线被定位成位于衬底的第一导电层和位于包括信号线的第二导电层下面的第三导电层内的电压平面之间。 可以在第三导电层的第一电压平面附近使用第二电压平面。 通孔也可用于将耦合到第一导体的信号线耦合到形成第三导电层的一部分的第二多个导体。 还公开了制造衬底的方法，以及利用衬底的电组件和信息处理系统（例如，计算机）。

公开(公告)号：US20070249209A1

公开(公告)日：2007-10-25

申请号：US11739573

申请日：2007-04-24

Applicant: Srdjan Djordjevic ,  Wolfgang Hoppe

Inventor： Srdjan Djordjevic ,  Wolfgang Hoppe

IPC: H01R13/62

CPC classification number: H05K1/115 ,  G11C5/063 ,  H01L25/112 ,  H01L2924/0002 ,  H05K1/0227 ,  H05K1/0234 ,  H05K1/117 ,  H05K1/167 ,  H05K1/181 ,  H05K3/222 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/093 ,  H05K2201/09536 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K2203/061 ,  H01L2924/00

Abstract: A circuit arrangement includes an arrangement of layers, wherein the arrangement of layers has a first surface and a second surface, at least one first and at least one second plated-through hole, at least one third plated-through hole, at least one first semiconductor component, and at least one second semiconductor component. A first layer from among the plurality of layers has a first conductive region and a second conductive region, which are coupled via a conductive connection. A second layer from among the plurality of layers has at least one first conductive region coupled to the first plated-through hole, and a second conductive region coupled to the second plated-through hole.

Abstract translation: 电路装置包括层的布置，其中层的布置具有第一表面和第二表面，至少一个第一和至少一个第二电镀通孔，至少一个第三电镀通孔，至少一个第一电镀通孔 半导体部件和至少一个第二半导体部件。 多个层中的第一层具有通过导电连接耦合的第一导电区域和第二导电区域。 多个层中的第二层具有耦合到第一电镀通孔的至少一个第一导电区域和耦合到第二电镀通孔的第二导电区域。

公开(公告)号：US20070235832A1

公开(公告)日：2007-10-11

申请号：US11309771

申请日：2006-09-22

Applicant: Ying-Xin Wang ,  Yu-Hsu Lin

Inventor： Ying-Xin Wang ,  Yu-Hsu Lin

IPC: H01L29/00

CPC classification number: H05K1/0216 ,  H05K1/165 ,  H05K2201/093 ,  H05K2201/09663

Abstract: A ground layer of a printed circuit board (PCB) includes a digital area, an analog area, and a connecting portion. The digital area is connected to the analog area via the connecting portion. The connecting portion with one end connected to the digital area, and the other end connected to the analog area follows a path resembling a labyrinth. The connecting portion replaces a conventional linear connecting portion and a plurality of chip capacitors. The connecting portion improves noise filtering effect and reduces cost as well.

Abstract translation: 印刷电路板（PCB）的接地层包括数字区域，模拟区域和连接部分。 数字区域通过连接部分连接到模拟区域。 连接部分的一端连接到数字区域，另一端与模拟区域连接，其后面是类似于迷宫的路径。 连接部分代替传统的线性连接部分和多个片状电容器。 连接部分提高噪声过滤效果，降低成本。

公开(公告)号：US20070192559A1

公开(公告)日：2007-08-16

申请号：US11616966

申请日：2006-12-28

Applicant: Takafumi BETSUI ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

Inventor： Takafumi BETSUI ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G06F13/00

CPC classification number: G11C5/04 ,  G11C5/02 ,  G11C5/06 ,  G11C5/063 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/17 ,  H01L25/18 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/49175 ,  H01L2924/1432 ,  H01L2924/14361 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/181 ,  H05K3/4602 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09663 ,  H05K2201/10159 ,  H05K2201/10522 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

Abstract translation: 设置在矩形半导体板上的微型计算机具有存储器接口电路。 存储器接口电路分别设置在从作为基准位置的一个角部沿着半导体板的两侧的周边延伸的位置。 在这种情况下，与仅在一侧具有存储器接口电路的半导体板相比，可以减小对半导体板的尺寸减小的限制。 每个分离的存储器接口电路上的各个部分电路具有与数据和数据选通信号相关联的相等的数据单元。 因此，微型计算机在主板和模块板上简化了线路设计。

公开(公告)号：US07239527B1

公开(公告)日：2007-07-03

申请号：US11009408

申请日：2004-12-08

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H01R12/16

CPC classification number: H05K1/0237 ,  H05K1/0219 ,  H05K1/0225 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09609 ,  H05K2201/09663

Abstract: For electrical backplanes and the like, a power plane adaptation to improve the propagation of high-speed signals through clearances in an embedded power plane is disclosed. In exemplary embodiments, the power plane is segmented in a high-speed connector region, such that a portion of the metal layer that forms the power plane is retained in the high-speed connector region—but isolated from the power-delivery portion of the power plane. The isolated portion is connected to digital ground, and clearances are formed therein where high-speed signaling throughholes will pass through the region. In some embodiments, various attainable advantages include better manufacturability, better matching and control of high-speed signaling throughhole impedance, and improved noise isolation. Other embodiments are described and claimed.

Abstract translation: 对于电气背板等，公开了一种用于改善高速信号通过嵌入式电源平面中的间隙的传播的电力平面适配。 在示例性实施例中，电力平面在高速连接器区域中分段，使得形成电力平面的金属层的一部分保持在高速连接器区域中，但是与电力输送部分 电力飞机 隔离部分连接到数字地，并且在其中形成间隙，其中高速信令通孔将通过该区域。 在一些实施例中，各种可获得的优点包括更好的可制造性，更好地匹配和控制高速信号通孔阻抗以及改进的噪声隔离。 描述和要求保护其他实施例。

公开(公告)号：US20070144772A1

公开(公告)日：2007-06-28

申请号：US11641810

申请日：2006-12-20

Applicant: John Lauffer ,  James Larnerd ,  Voya Markovich

Inventor： John Lauffer ,  James Larnerd ,  Voya Markovich

IPC: H05K1/16

CPC classification number: H01L23/49811 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/0216 ,  H05K1/0256 ,  H05K1/056 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/44 ,  H05K3/4641 ,  H05K2201/093 ,  H05K2201/09345 ,  H05K2201/09481 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49162 ,  Y10T29/49165 ,  Y10T29/49176 ,  H01L2224/0401

Abstract: A method of making circuitized substrate which includes a plurality of contiguous open segments which define facing edge portions within an electrically conductive layer to isolate separate portions of the conductive layer such that the layer can be used for different functions, e.g., as both power and ground elements, within a product (e.g., electrical assembly) which includes the substrate as part thereof. An information handling system, e.g., a mainframe computer, which represents one of the products in which the substrate may be utilized, is also provided.

Abstract translation: 一种制造电路化衬底的方法，其包括多个邻接的开放段，其限定导电层内的相对边缘部分以隔离导电层的分离部分，使得该层可用于不同的功能，例如电力和地面 元件，在包括基板作为其一部分的产品（例如，电气组件）内。 还提供了代表其中可以使用衬底的产品之一的信息处理系统，例如主机计算机。

公开(公告)号：US20070114057A1

公开(公告)日：2007-05-24

申请号：US11517786

申请日：2006-09-08

Applicant: Yoshinari Matsuda

Inventor： Yoshinari Matsuda

IPC: H05K1/16

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

Abstract: A printed wiring board on which a pattern can be formed favorably by printing and soldering even where a small part of the 1005 size or less is mounted. The printed wiring board includes a substrate; a pair of soldering lands on the substrate, the soldering lands being spaced from one another with a first side of one land opposing a first side of another land; and a mounted part having a pair of electrodes on opposite ends thereof soldered to the respective lands. A wiring line is connected to each soldering land, and an insulating element overlies the wiring lines. The insulating element has openings formed so as to expose the soldering lands therethrough. Wiring line connection elements are individually connected to only the first sides of the lands. Each insulating element opening has an edge positioned outside of the corresponding land and on the inner side of the corresponding wiring line connection element.

Abstract translation: 即使安装有小于1005的小部分，也可以通过印刷和焊接而形成图案的印刷电路板。 印刷线路板包括基板; 在基板上的一对焊接区域，所述焊接区域彼此间隔开，其中一个焊盘的第一面与另一焊盘的第一面相对; 以及其相对端上具有一对电极的安装部分焊接到相应的焊盘。 布线与每个焊接区连接，绝缘元件覆盖在布线上。 绝缘元件具有形成为暴露焊接区域的开口。 连接线连接元件仅分别连接到焊盘的第一侧。 每个绝缘元件开口具有位于对应的焊盘外侧和相应的布线连接元件的内侧的边缘。

公开(公告)号：US20070076350A1

公开(公告)日：2007-04-05

申请号：US11529666

申请日：2006-09-27

Applicant: Masashi Watanabe ,  Toshiki Ooka ,  Takahiro Sakaguchi

Inventor： Masashi Watanabe ,  Toshiki Ooka ,  Takahiro Sakaguchi

IPC: H01G9/10 ,  H05K5/03 ,  H01G4/228

CPC classification number: H05K1/0243 ,  H01G2/065 ,  H01G9/008 ,  H01G9/10 ,  H05K1/0231 ,  H05K1/112 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663 ,  H05K2201/10015

Abstract: According to one embodiment, a capacitor includes a first anode terminal exposed from an end portion of a first inner electrode coupled to one side of a dielectric in a predetermined direction, a second anode terminal exposed from the other end portion of the first electrode in the predetermined direction, a first cathode terminal exposed from a predetermined portion of a second inner electrode that is connected to the other side of the dielectric and provided independently of the first electrode, to insides of the exposed portions of the first and second anode terminals, in the predetermined direction, and a second cathode terminal exposed from a part of the predetermined portion of the second electrode which is close to the second anode terminal, to the insides of the exposed portions of the first and second anode terminals, in the predetermined direction, at a predetermined interval from the first cathode terminal.

Abstract translation: 根据一个实施例，电容器包括从第一内部电极的端部暴露的第一阳极端子，第一阳极端子沿预定方向耦合到电介质的一侧，第二阳极端子从第一电极的另一端部露出， 从第二内部电极的预定部分暴露的第一阴极端子，其连接到电介质的另一侧并且独立于第一电极而设置在第一和第二阳极端子的暴露部分的内部， 所述预定方向和从所述第二电极的接近所述第二阳极端子的所述预定部分的一部分露出的第二阴极端子沿所述预定方向延伸到所述第一阳极端子和所述第二阳极端子的暴露部分的内部， 从第一阴极端子预定间隔。

公开(公告)号：US20070030626A1

公开(公告)日：2007-02-08

申请号：US11198257

申请日：2005-08-06

Applicant: Ronald Barnett

Inventor： Ronald Barnett

IPC: H01G4/06

CPC classification number: H01G4/33 ,  H01L23/50 ,  H01L23/642 ,  H01L23/66 ,  H01L2224/16 ,  H01L2924/3011 ,  H05K1/0225 ,  H05K1/0233 ,  H05K1/0234 ,  H05K1/167 ,  H05K2201/086 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09663

Abstract: A capacitive structure and technique for allowing near-instantaneous charge transport and reliable, wide-band RF ground paths in integrated circuit devices such as integrated circuit dies, integrated circuit packages, printed circuit boards, and electronic circuit substrates is presented. Methods for introducing resistive loss, dielectric loss, magnetic loss, and/or radiation loss in a signal absorption ring implemented around a non-absorptive area of one or more conductive layers of an integrated circuit structure to dampen laterally flowing Electro-Magnetic (EM) waves between electrically adjacent conductive layers of the device are also presented.