公开(公告)号：US07626216B2

公开(公告)日：2009-12-01

申请号：US11583212

申请日：2006-10-18

Applicant: William E. McKinzie, III

Inventor： William E. McKinzie, III

IPC: H01L31/072 ,  H01L31/109 ,  H01L31/0328 ,  H01L31/0336

CPC classification number: H01P1/20 ,  H01P1/2005 ,  H05K1/0218 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0236 ,  H05K1/0239 ,  H05K1/162 ,  H05K1/165 ,  H05K1/181 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09609 ,  H05K2201/09663 ,  H05K2201/09672 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49018 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A hybrid electromagnetic bandgap (EBG) structure for broadband suppression of noise on printed wiring boards includes an array of coplanar patches interconnected into a grid by series inductances, and a corresponding array of shunt LC networks connecting the coplanar patches to a second conductive plane. This combination of series inductances and shunt resonant vias lowers the cutoff frequency for the fundamental stopband. The series inductances and shunt capacitances may be implemented using surface mount component technology, or printed traces. Patches may also be interconnected by coplanar coupled transmission lines. The even and odd mode impedances of the coupled lines may be increased by forming slots in the second conductive plane disposed opposite to the transmission line, lowering the cutoff frequency and increasing the bandwidth of the fundamental stopband. Coplanar EBG structures may be integrated into power distribution networks of printed wiring boards for broadband suppression of electromagnetic noise.

Abstract translation: 用于宽带抑制印刷电路板上的噪声的混合电磁带隙（EBG）结构包括通过串联电感互连到电网中的共面贴片阵列，以及将共面贴片连接到第二导电平面的相应阵列的分流LC网络。 串联电感和并联谐振通孔的组合降低了基波阻带的截止频率。 串联电感和分流电容可以使用表面贴装元件技术或印刷迹线实现。 补片也可以通过共面耦合传输线相互连接。 可以通过在与传输线相对布置的第二导电平面中形成槽，降低截止频率并增加基带阻带的带宽来增加耦合线的偶模和奇模阻抗。 共面EBG结构可以集成到用于宽带抑制电磁噪声的印刷线路板的配电网络中。

公开(公告)号：US20090268369A1

公开(公告)日：2009-10-29

申请号：US12109356

申请日：2008-04-25

Applicant: Wei-Ting Chen ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Chang-Lin Wei ,  Cheng-Hua Tsai ,  Kuo-Chiang Chin

Inventor： Wei-Ting Chen ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Chang-Lin Wei ,  Cheng-Hua Tsai ,  Kuo-Chiang Chin

IPC: H01G4/005

CPC classification number: H05K1/162 ,  H01G4/012 ,  H01G4/228 ,  H01G4/33 ,  H01L23/50 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A capacitor structure is provided. In the capacitor structure, a signal electrode plate and an extension ground electrode plate are disposed on the same plane to form a co-plane capacitor structure. Due to slow wave characteristic, the resonance frequency of the capacitor structure is effectively raised and the capacitor structure may be applied in high frequency.

Abstract translation: 提供电容器结构。 在电容器结构中，信号电极板和延伸接地电极板设置在同一平面上以形成共面电容器结构。 由于慢波特性，电容器结构的谐振频率有效提高，电容器结构可以高频应用。

公开(公告)号：US20090242506A1

公开(公告)日：2009-10-01

申请号：US12457183

申请日：2009-06-03

Applicant: Kei Nakamura ,  Hitoshi Ishizaka

Inventor： Kei Nakamura ,  Hitoshi Ishizaka

IPC: H05K3/06

CPC classification number: H05K1/0269 ,  H01L21/4846 ,  H01L23/4985 ,  H01L23/544 ,  H01L2223/54473 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/056 ,  H05K3/303 ,  H05K2201/0108 ,  H05K2201/0969 ,  H05K2201/09918 ,  H05K2203/166 ,  Y02P70/613 ,  H01L2924/00

Abstract: A wired circuit board is provided having a high-reliability conductive pattern formed thereon and mounting an electronic component thereon with high accuracy, and a method is provided for manufacturing the wired circuit board and mounting the electronic component thereon. An insulating layer including a mounting portion is formed on a metal supporting layer having a specular gloss of 150 to 500% at an incidence angle of 45°. A conductive pattern is formed on the insulating layer. By a reflection-type optical sensor, a defective shape of the conductive pattern is inspected. Then, an opening is formed by etching the portion of the metal supporting layer which is overlapping the mounting portion such that the mounting portion of the insulating layer exposed by etching has a haze value of 20 to 50%, whereby a TAB tape carrier is obtained. Thereafter, an electronic component is aligned with the mounting portion by a reflection-type optical sensor such that the electronic component is mounted on the mounting portion.

公开(公告)号：US07592551B2

公开(公告)日：2009-09-22

申请号：US11783999

申请日：2007-04-13

Applicant: Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

Inventor： Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

IPC: H05K1/00

CPC classification number: H05K1/0269 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/0969 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/53022 ,  Y10T29/53026 ,  Y10T29/5303 ,  Y10T29/53035 ,  Y10T29/53039 ,  Y10T29/53043

Abstract: A wired circuit board assembly sheet having a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified wired circuit board.

Abstract translation: 一种布线电路板组装片，具有多个布线电路板，用于区分布线电路板的缺陷的区别标记和用于支撑多个布线电路板和区别标记的支撑片。 每个识别标记具有用于指示指定的布线电路板的指示部分。

公开(公告)号：US20090233465A1

公开(公告)日：2009-09-17

申请号：US11885262

申请日：2006-10-27

Applicant: Masanori Mizoguchi

Inventor： Masanori Mizoguchi

IPC: H01R12/00

CPC classification number: H01R12/592 ,  H01R12/58 ,  H01R12/613 ,  H01R12/62 ,  H01R12/777 ,  H01R12/778 ,  H01R12/78 ,  H01R12/79 ,  H05K1/118 ,  H05K3/326 ,  H05K3/365 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/09063 ,  H05K2201/091 ,  H05K2201/0969 ,  H05K2201/1059 ,  H05K2201/209

Abstract: An electrical connection structure allowing reduction in height and easy disassembly, wherein a first connecting member comprises a flexible substrate comprising a flexible insulating film, at least one conductive pad formed on at least one side thereof, a conductive circuit pattern extending from the rim of the pad, a through-hole formed through the thickness thereof at a planar position within the pad, and a small aperture formed at a planar position within the pad and communicating with the through-hole, and a second connecting member comprises a conductive projection formed at least one side thereof and electrically connected with a conductive circuit pattern formed inside or on the second connecting member, where the electrical connection is formed in the manner such that the conductive projection is inserted in the through-hole, through the small aperture, and mechanically contacts the pad.

Abstract translation: 一种电连接结构，其允许降低高度并易于拆卸，其中第一连接构件包括柔性基底，该柔性基底包括柔性绝缘膜，至少一个导电垫在其至少一侧上形成，导电电路图案从 衬垫，在衬垫内的平面位置处形成通过其厚度的通孔，以及形成在衬垫内的平面位置并与通孔连通的小孔，第二连接构件包括形成在 至少一侧，并与形成在第二连接构件的内部或第二连接构件上的导电电路图形电连接，其中电连接形成为使得导电突起通过小孔插入到通孔中，并机械地 接触垫

公开(公告)号：US20090223707A1

公开(公告)日：2009-09-10

申请号：US12041916

申请日：2008-03-04

Applicant: Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

Inventor： Sampath Komarapalayam Velayudham Karikalan ,  Rezaur Rahman Khan

IPC: H05K1/02 ,  H05K3/20

CPC classification number: H05K1/0224 ,  H05K1/024 ,  H05K1/0245 ,  H05K2201/0191 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09054 ,  H05K2201/0969 ,  H05K2201/09736 ,  H05K2201/09745 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49147

Abstract: Magnetic field distribution and mutual capacitance control for transmission lines are provided. A first circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, and attaching a first trace to the second surface of the dielectric material. A surface profile of the reference plane layer is modified to decrease a resistance of a return current signal path through the reference plane layer, to reduce a magnetic field coupling between the first trace and a second trace. A second circuit board is fabricated by attaching a reference plane layer to a dielectric material layer, attaching a trace to the dielectric material, and forming a solder mask layer on the dielectric material layer over the trace. An effective dielectric constant of the solder mask layer is modified to reduce or increase a mutual capacitance between the first trace and a second trace on the dielectric material.

Abstract translation: 提供传输线的磁场分布和互电容控制。 通过将参考平面层附着到介电材料层并且将第一迹线附接到电介质材料的第二表面来制造第一电路板。 修改参考平面层的表面轮廓以减小通过参考平面层的返回电流信号路径的电阻，以减小第一迹线和第二迹线之间的磁场耦合。 通过将参考平面层附着到电介质材料层，将迹线附着到电介质材料上，以及在迹线上的介电材料层上形成焊料掩模层来制造第二电路板。 修改焊接掩模层的有效介电常数以减小或增加介电材料上的第一迹线和第二迹线之间的互电容。

公开(公告)号：US07585699B2

公开(公告)日：2009-09-08

申请号：US11477111

申请日：2006-06-29

Applicant: Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Kazuhiro Baba

Inventor： Katsumi Kikuchi ,  Tadanori Shimoto ,  Koji Matsui ,  Kazuhiro Baba

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50

CPC classification number: H01L21/4857 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/81 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K3/0097 ,  H05K3/06 ,  H05K3/20 ,  H05K3/205 ,  H05K3/4007 ,  H05K3/44 ,  H05K3/4644 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0969 ,  H05K2203/0323 ,  H05K2203/0376 ,  H05K2203/061 ,  H05K2203/1536 ,  H01L2924/00

Abstract: A semiconductor package board for mounting thereon a semiconductor chip includes a metal base having an opening for receiving therein the semiconductor chip and a multilayer wiring film layered onto the metal base. The semiconductor chip is flip-chip bonded onto the metal pads disposed on the multilayer wiring film within the opening. The surface of the metal base is flush with the top surface of the semiconductor chip received in the opening. The resultant semiconductor device has a larger number of external pins and a smaller deformation without using a stiffener.

公开(公告)号：US20090194321A1

公开(公告)日：2009-08-06

申请号：US12356106

申请日：2009-01-20

Applicant: Yasuto Ishimaru ,  Hirofumi Ebe

Inventor： Yasuto Ishimaru ,  Hirofumi Ebe

IPC: H05K1/18 ,  H05K3/10

CPC classification number: H05K1/0209 ,  H01L23/3735 ,  H01L23/562 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K1/189 ,  H05K2201/09318 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/10674

Abstract: A mounting region is provided at an approximately center of one surface of an insulating layer. A conductive trace is formed so as to outwardly extend from inside of the mounting region. A cover insulating layer is formed in a periphery of the mounting region so as to cover the conductive trace. A terminal of the conductive trace is arranged in the mounting region, and a bump of an electronic component is bonded to the terminal. A metal layer made of copper, for example, is provided on the other surface of the insulating layer. A pair of slits is formed in the metal layer such that a region being opposite to the electronic component is sandwiched therebetween. Each slit is formed so as not to divide the metal layer into a plurality of regions.

Abstract translation: 安装区域设置在绝缘层的一个表面的大致中心处。 导电迹线形成为从安装区域的内部向外延伸。 在安装区域的周围形成覆盖绝缘层以覆盖导电迹线。 导电迹线的端子布置在安装区域中，并且电子部件的凸块接合到端子。 例如，在绝缘层的另一个表面上设置由铜构成的金属层。 在金属层中形成一对狭缝，使得与电子部件相对的区域夹在其间。 每个狭缝形成为不将金属层划分成多个区域。

公开(公告)号：US20090190320A1

公开(公告)日：2009-07-30

申请号：US12362354

申请日：2009-01-29

Applicant: ICHIO SHIMIZU ,  Kenya Kawano ,  Kisho Ashida ,  Yuichi Machida

Inventor： ICHIO SHIMIZU ,  Kenya Kawano ,  Kisho Ashida ,  Yuichi Machida

IPC: H05K7/04 ,  H01L23/48

CPC classification number: H05K7/04 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49575 ,  H01L23/49589 ,  H01L24/28 ,  H01L24/29 ,  H01L24/36 ,  H01L24/39 ,  H01L24/40 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/40245 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73221 ,  H01L2224/83801 ,  H01L2224/83855 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0781 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/351 ,  H05K3/202 ,  H05K3/321 ,  H05K3/3442 ,  H05K2201/0397 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2201/1003 ,  H05K2201/10484 ,  H05K2201/10636 ,  H05K2201/10924 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/3512 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Coupling reliability of a passive component is improved to increase the reliability of a semiconductor device. A first through hole is formed in a first electrode part of a first plate-like lead, and a second through hole is formed in a second electrode part of a second plate-like lead. As a result, at the first electrode part of the first plate-like lead, one external terminal of the passive component can be coupled to the first electrode parts on both sides of the first through hole while being laid across the first through hole. Also, at the second electrode part of the second plate-like lead, the other external terminal of the passive component can be coupled to the second electrode parts on both sides of the second through hole while being laid across the second through hole. Accordingly, at central portions both in the longitudinal and width directions of the passive component, the passive component is surrounded by sealing members. As a result, thermal stress applied to jointing materials such as solder can be reduced, improving the reliability of the semiconductor device (semiconductor package).

Abstract translation: 改善了无源部件的耦合可靠性，以提高半导体器件的可靠性。 第一通孔形成在第一板状引线的第一电极部分中，第二通孔形成在第二板状引线的第二电极部分中。 结果，在第一板状引线的第一电极部分，无源部件的一个外部端子可以被连接到第一通孔的两侧的第一电极部分，同时跨过第一通孔。 此外，在第二板状引线的第二电极部分，无源部件的另一个外部端子可以在跨过第二通孔而被布置在第二通孔的两侧上的第二电极部件上。 因此，在无源部件的纵向和宽度方向的中心部分处，被动部件被密封部件包围。 结果，可以减少施加到诸如焊料的接合材料的热应力，从而提高半导体器件（半导体封装）的可靠性。

公开(公告)号：US20090178271A1

公开(公告)日：2009-07-16

申请号：US12007820

申请日：2008-01-16

Applicant: Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

Inventor： Frank D. Egitto ,  John S. Kresge ,  John M. Lauffer

IPC: H01C17/06

CPC classification number: H01C17/06 ,  H01C17/24 ,  H05K1/0268 ,  H05K1/167 ,  H05K2201/0355 ,  H05K2201/0969 ,  H05K2203/0361 ,  H05K2203/171 ,  Y10T29/49099 ,  Y10T29/49101

Abstract: A method of making a circuitized substrate which involves forming a plurality of individual film resistors having approximate resistance values as part of at least one circuit of the substrate, measuring the resistance of a representative (sample) resistor to define its resistance, utilizing these measurements to determine the corresponding precise width of other, remaining film resistors located in a defined proximity relative to the representative resistor such that these remaining film resistors will include a defined resistance value, and then selectively isolating defined portions of the resistive material of these remaining film resistors while simultaneously defining the precise width of the resistive material in order that these film resistors will possess the defined resistance.

Abstract translation: 一种制造电路化衬底的方法，其包括形成具有近似电阻值的多个单独的膜电阻器作为衬底的至少一个电路的一部分，测量代表性（样品）电阻器的电阻以限定其电阻，利用这些测量 确定位于相对于代表性电阻器确定的接近度的其它剩余膜电阻器的对应精确宽度，使得这些剩余的膜电阻器将包括限定的电阻值，然后选择性地隔离这些剩余膜电阻器的电阻材料的限定部分，同时 同时限定电阻材料的精确宽度，以使这些薄膜电阻器具有限定的电阻。