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公开(公告)号：US20170374739A1
公开(公告)日：2017-12-28
申请号：US15189435
申请日：2016-06-22
Applicant: R&D CIRCUITS, INC.
Inventor： THOMAS P. WARWICK , DHANANJAYA TRUPUSEEMA , JAMES V. RUSSELL
CPC classification number: H05K1/111 , H01L21/486 , H01L23/49827 , H01R13/2435 , H05K1/0251 , H05K1/0296 , H05K1/09 , H05K1/118 , H05K1/18 , H05K3/10 , H05K3/32 , H05K3/368 , H05K3/4007 , H05K3/4038 , H05K3/4046 , H05K2201/10015 , H05K2201/10022 , H05K2201/1003 , H05K2201/10378
Abstract: The present invention provides for a method and structure for forming three-dimensionally routed dielectric wires between discrete points on the two or more parallel circuit planes. The wires may be freely routed in three-dimensional space as to create the most efficient routing between the two arbitrarily defined points on the two or more parallel circuit planes. Metalizing the outer surfaces of these three dimensional dielectric wires electrically coupling the discrete wires to their respective discrete contact points. Two or more of these wires may be in intimate contact to one another electrically coupling to each other as well as to two or more discrete contact pads. These electrically coupled contact pads may be on opposite sides or on the same side of the structure and the formed metalized wires may originate on one side and terminate on the other or originate and terminate from the same side
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公开(公告)号：US20170373567A1
公开(公告)日：2017-12-28
申请号：US15629261
申请日：2017-06-21
Applicant: RENESAS ELECTRONICS CORPORATION
Inventor： Shinji NISHIZONO , Tadashi SHIMIZU , Norikazu MOTOHASHI , Tomohiro Nishiyama
CPC classification number: H02K11/33 , H02H7/08 , H02H9/02 , H02K7/145 , H02M7/003 , H02P6/085 , H05K1/0206 , H05K1/0263 , H05K1/115 , H05K1/181 , H05K3/3447 , H05K3/429 , H05K7/1432 , H05K2201/10015 , H05K2201/10166 , H05K2201/10356 , H05K2201/10522 , H05K2201/10545 , H05K2201/10628 , H05K2201/10636
Abstract: An electronic device is downsized while suppressing performance degradation of the electronic device. In the electronic device, a power module including a power transistor is arranged in a first region on a back surface of a through hole board having a plurality of through hole vias having different sizes while a pre-driver including a control circuit is arranged in a second region on a front surface of the board. In this case, in a plan view, the first region and the second region have an overlapping region. The power module and the pre-driver are electrically connected to each other via a through hole via. The plurality of through hole vias include a through hole via having a first size, a through hole via which is larger than the first size and in which a cable can be inserted, and a through hole via in which a conductive member is embedded.
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公开(公告)号：US20170367186A1
公开(公告)日：2017-12-21
申请号：US15392160
申请日：2016-12-28
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Min Cheol PARK , Hwi Dae KIM , Young Ghyu AHN
CPC classification number: H05K1/181 , H01G4/005 , H01G4/12 , H01G4/236 , H01G4/30 , H05K1/111 , H05K3/3442 , H05K2201/10015 , Y02P70/613
Abstract: A multilayer capacitor include dielectric layers stacked in a direction perpendicular to a mounting surface of a capacitor body, and internal electrodes and an equivalent series inductance (ESL) control pattern formed on upper and lower portions of the dielectric layers, respectively. The internal electrodes have an area larger than that of the ESL control pattern, and the ESL control pattern is exposed to a mounting surface of a capacitor body.
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公开(公告)号：US09847286B2
公开(公告)日：2017-12-19
申请号：US14781572
申请日：2014-04-18
Applicant: HALLIBURTON ENERGY SERVICES, INC.
Inventor： Oleg Bondarenko
CPC classification number: H01L23/49838 , H01L23/32 , H01L23/49805 , H01L23/49811 , H01L23/49816 , H01L23/49833 , H01L23/49861 , H01L24/17 , H01L24/81 , H01L2224/16055 , H01L2224/16057 , H01L2224/16227 , H01L2224/48091 , H01L2224/48227 , H01L2224/81191 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H05K1/141 , H05K1/181 , H05K3/3426 , H05K3/3436 , H05K2201/049 , H05K2201/10015 , H05K2201/10734 , H01L2924/00014 , H01L2924/00012
Abstract: An example method for attaching a ball grid array chip to a circuit board includes providing an adapter for attaching a chip with a plurality of solder balls to a circuit board, the adapter having an adapter substrate made from a material having substantially the same coefficient of thermal expansion as the substrate used in the chip and having at least one electrical contact site on a mounting surface of the adapter substrate for engaging a solder ball on the ball grid array chip and a plurality of lead wires extending from each side of the adapter substrate. At least one of the lead wires is electrically connected to at least one electrical contact site on the adapter substrate.
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公开(公告)号：US09847173B2
公开(公告)日：2017-12-19
申请号：US15185099
申请日：2016-06-17
Applicant: Murata Manufacturing Co., Ltd.
Inventor： Masaaki Taniguchi , Yasuji Yamamoto , Takahiro Ishibashi
CPC classification number: H01G4/248 , H01G4/008 , H01G4/12 , H01G4/232 , H01G4/30 , H05K1/0243 , H05K1/111 , H05K3/3442 , H05K2201/10015 , Y02P70/611
Abstract: A multilayer ceramic capacitor connected to an output electrode and an input electrode of a mounting substrate includes a laminated body. In the laminating direction of the laminated body, the shortest distance from an outer first internal electrode to the surface of an external electrode on the side closer to a first principal surface, and the shortest distance from an outer second internal electrode to the surface of an external electrode on the side closer to a second principal surface are each about 40 μm or less. In the width direction of the laminated body, the shortest distance from an end of an internal electrode to the surface of the external electrode on the side closer to a first side surface, and the shortest distance from an end of an internal electrode to the surface of the external electrode on the side closer to a second side surface are each about 40 μm or less.
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Patent Agency Ranking
106.发明授权公开(公告)号：US09837484B2
公开(公告)日：2017-12-05
申请号：US14722872
申请日：2015-05-27
Applicant: STATS ChipPAC, Ltd.
Inventor： JinHee Jung , HyungSang Park , SungSoo Kim
IPC: H01L23/498 , H01L49/02 , H01L23/538 , H01L21/683 , H01L23/00 , H01L23/50 , H01L21/48
CPC classification number: H01L28/40 , H01L21/486 , H01L21/6835 , H01L23/49827 , H01L23/50 , H01L23/5389 , H01L24/19 , H01L24/25 , H01L2221/68345 , H01L2224/04105 , H01L2224/2518 , H01L2224/32225 , H01L2224/82031 , H01L2224/82039 , H01L2224/82047 , H01L2224/83005 , H01L2224/92144 , H05K1/185 , H05K3/4664 , H05K2201/10015
Abstract: A semiconductor device comprises a first conductive layer. A second conductive layer is formed over the first conductive layer. A semiconductor component is disposed over the first conductive layer. The second conductive layer lies in a plane between a top surface of the semiconductor component and a bottom surface of the semiconductor component. A third conductive layer is formed over the semiconductor component opposite the first conductive layer. The semiconductor device includes a symmetrical structure. A first insulating layer is formed between the first conductive layer and semiconductor component. A second insulating layer is formed between the semiconductor component and third conductive layer. A height of the first insulating layer between the first conductive layer and semiconductor component is between 90% and 110% of a height of the second insulating layer between the semiconductor component and third conductive layer. The semiconductor component includes a passive device.
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公开(公告)号：US20170346243A1
公开(公告)日：2017-11-30
申请号：US15262475
申请日：2016-09-12
Applicant: ACBEL POLYTECH INC.
Inventor： Wei HONG , Jia-Jiann HUANG , Hsiao-Kai CHEN , Chih-Chieh TSENG
IPC: H01R13/74 , H01R13/6594 , H01R13/66 , H05K1/11 , H01R13/621 , H05K1/02 , H05K1/18
CPC classification number: H01R13/748 , H01R13/6215 , H01R13/6594 , H01R13/665 , H01R13/719 , H05K1/0224 , H05K1/0231 , H05K1/111 , H05K1/181 , H05K3/4015 , H05K2201/09063 , H05K2201/10015 , H05K2201/10265
Abstract: A filtered connector is mounted on a casing and includes a connection port and a filter board. An electrode plate mounted on one end of the connection port and electrically isolated from the casing is securely mounted through a through hole of the casing. The filter board has a circuit board assembly, multiple grounding spring plates and multiple filtering capacitors. The circuit board assembly has a slot to be mounted through by the electrode plate. The grounding spring plates are mounted on a surface of the circuit board assembly and electrically contact the casing. The filtering capacitors are electrically connected between the electrode plate and the grounding spring plates. As the filter board is not mounted inside the connection port, only the filter board is to be mounted without replacing the connection port, thereby lowering users' expense in installation of the filter board.
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公开(公告)号：US09831924B2
公开(公告)日：2017-11-28
申请号：US15072389
申请日：2016-03-17
Applicant: Renesas Electronics Corporation
Inventor： Xihua Lin
IPC: H04B5/00 , H04M1/00 , H01L29/66 , H01L27/08 , H01L21/02 , H01L23/48 , H01L23/52 , H01L29/40 , H04B3/28 , H03H7/01 , H03H5/00 , H01F29/02 , H01F21/08 , H05K1/02 , H05K1/18 , H05K1/11 , H02J50/12
CPC classification number: H04B5/0081 , H02J50/10 , H02J50/12 , H04B5/0031 , H04B5/0037 , H04B5/0062 , H04B5/0087 , H05K1/0219 , H05K1/115 , H05K1/181 , H05K2201/10015 , H05K2201/1003 , H05K2201/10098 , H05K2201/10287 , H05K2201/10545
Abstract: An apparatus including a board, an inductor that is provided on the board, a guard ring that includes a first guard ring part provided to be adjacent to a circumference of the inductor and a second guard ring part provided to be adjacent to an outer side of the first guard ring part, in which one end of the second guard ring part is connected to one end of the first guard ring part, and a first power supply that is connected to another end of the first guard ring part and another end of the second guard ring part.
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109.发明申请公开(公告)号：US20170333703A1
公开(公告)日：2017-11-23
申请号：US15651045
申请日：2017-07-17
Applicant: Greatbatch Ltd.
Inventor： Robert A. Stevenson , Christine A. Frysz , Richard L. Brendel
IPC: A61N1/08 , H05K5/00 , H03H1/00 , H01G4/35 , H01G4/40 , A61N1/37 , H01R13/7195 , H05K9/00 , A61N1/375 , H03H7/01
CPC classification number: A61N1/08 , A61N1/086 , A61N1/3718 , A61N1/375 , A61N1/3754 , H01G4/06 , H01G4/35 , H01G4/40 , H01R13/7195 , H03H1/0007 , H03H7/1766 , H03H2001/0042 , H03H2001/0085 , H05K1/181 , H05K5/0095 , H05K9/00 , H05K2201/10015
Abstract: An EMI/energy dissipating filter for an active implantable medical device (AIMD) is described. The filter comprises a first gold braze hermetically sealing the insulator to a ferrule that is configured to be mounted in an opening in a housing for the AIMD. A lead wire is hermetically sealed in a passageway through the insulator by a second gold braze. A circuit board substrate is disposed adjacent the insulator. A two-terminal chip capacitor disposed adjacent to the circuit board has an active end metallization that is electrically connected to the active electrode plates and a ground end metallization that is electrically connected to the at least one ground electrode plates of the capacitor. A ground path electrically extends between the ground end metallization of the chip capacitor and the ferrule. The ground path comprises a conductive pin electrically and mechanically connected to the ferrule by a third gold braze. The ground path comprises an internal ground plate disposed within the circuit board substrate, and the internal ground plate is electrically connected to both the conductive pin and the ground end metallization of the chip capacitor. An active path electrically extends between the active end metallization of the chip capacitor and the lead wire.
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公开(公告)号：US09824824B2
公开(公告)日：2017-11-21
申请号：US14992904
申请日：2016-01-11
Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
Inventor： Heung Kil Park
IPC: H05K1/02 , H05K1/18 , H01G4/30 , H01G4/248 , H01G4/12 , H01G4/012 , H01G4/38 , H01G2/06 , H01G4/232 , H01L41/053 , H05K1/03 , H05K1/14 , H01L41/083
CPC classification number: H01G4/248 , H01G2/06 , H01G4/012 , H01G4/232 , H01G4/30 , H01G4/38 , H01L41/053 , H01L41/083 , H05K1/0306 , H05K1/141 , H05K2201/10015 , H05K2201/10378 , H05K2201/1053 , H05K2201/10962
Abstract: A capacitor component includes a capacitor including a plurality of internal electrodes, a capacitor body containing a piezoelectric material disposed in at least regions between the plurality of internal electrodes, and external electrodes connected to the plurality of internal electrodes; and an interposer disposed to be coupled to the capacitor and including a buffer substrate containing a buffer material having a degree of piezoelectricity lower than that of the piezoelectric material, and connection electrodes electrically connected to the external electrodes.
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