公开(公告)号：US5092034A

公开(公告)日：1992-03-03

申请号：US544770

申请日：1990-06-27

Applicant: John M. Altendorf ,  Marvin G. Wong

Inventor： John M. Altendorf ,  Marvin G. Wong

IPC: H01L23/495 ,  H01L23/498 ,  H05K3/30 ,  H05K3/34

CPC classification number: H05K3/301 ,  H01L23/49572 ,  H01L23/49861 ,  H05K3/3426 ,  H01L2924/0002 ,  H05K2201/10393 ,  H05K2201/10681 ,  H05K3/305 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49144

Abstract: A method and apparatus for attaching the outer leads of a semiconductor package (preferably a Tape Automated Bonded circuit) to the traces on a printed circuit board is described. The outer leads of the package are configured in an angled orientation so that the tip of each lead extends downwardly below the lower surface of the package. As a result, placement of the package against the circuit board causes the leads to be biased downwardly against the traces. In order to accomplish this, the package is secured to the board using a rigid frame structure. The frame structure urges the edges of the package against the board. This insures that the leads make electrical contact with the traces in a fast and efficient manner, while avoiding problems associated with a lack of lead coplanarity.

Abstract translation: 描述了用于将半导体封装（优选磁带自动绑定电路）的外引线附接到印刷电路板上的迹线的方法和装置。 包装的外引线被配置成成角度的方向，使得每个引线的尖端在包装的下表面下方向下延伸。 结果，将封装放置在电路板上使引线相对于迹线向下偏置。 为了实现这一点，使用刚性框架结构将包装固定到板上。 框架结构将包装的边缘推向板。 这确保引线以快速和有效的方式与迹线电接触，同时避免与缺乏引线共面性相关的问题。

公开(公告)号：US5001302A

公开(公告)日：1991-03-19

申请号：US436295

申请日：1989-11-13

Applicant: Yoshinori Atsumi

Inventor： Yoshinori Atsumi

IPC: H01L31/042 ,  H01R4/04 ,  H05K1/02 ,  H05K3/32

CPC classification number: H01R4/04 ,  H05K3/323 ,  H01L2224/2929 ,  H01L2224/2939 ,  H01L2224/29393 ,  H01L2224/29399 ,  H01L2224/29444 ,  H01L2224/29455 ,  H01L2924/01079 ,  H01L2924/07811 ,  H05K1/0274 ,  H05K2201/0129 ,  H05K2201/0221 ,  H05K2201/0233 ,  H05K2201/0323 ,  H05K2201/09072 ,  H05K2201/10681 ,  Y10T29/49922 ,  Y10T29/49924

Abstract: A connecting structure for an electronic part employs an improved anisotropic electrically conductive layer. The layer includes a hot melt type insulative adhesive, heat resilient particles and carbon particles. Each of the heat resilient particles is made of thermoplastic resin and is plated with metal such as gold, nickel or the like. Each of the carbon particles is melted by a heat pressure and brings about an electric conductivity when it is dried and hardened. Thus, the anisotropically conductive layer disclosed in this invention does not include hard particles at all. Namely, an electronic part such as a solar battery cell or a semiconductor device is not damaged by particles of the conductive layer. In addition, the connecting structure employing the aforementioned layer improves the security of adherence and the reliability of the electric conductivity.

Abstract translation: 电子部件的连接结构采用改进的各向异性导电层。 该层包括热熔型绝缘粘合剂，热弹性颗粒和碳颗粒。 每个热弹性颗粒由热塑性树脂制成，并镀有诸如金，镍等的金属。 每个碳颗粒通过热压熔化并在干燥和硬化时产生电导率。 因此，本发明中公开的各向异性导电层根本不包括硬颗粒。 也就是说，诸如太阳能电池单元或半导体器件的电子部件不会被导电层的颗粒损坏。 此外，采用上述层的连接结构提高了粘附的安全性和导电性的可靠性。

公开(公告)号：US4985601A

公开(公告)日：1991-01-15

申请号：US346220

申请日：1989-05-02

Applicant: George R. Hagner

Inventor： George R. Hagner

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/08 ,  H05K3/10 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K3/08 ,  H05K1/111 ,  H05K1/183 ,  H05K3/107 ,  H05K3/20 ,  H05K3/3473 ,  H05K2201/0129 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2201/09981 ,  H05K2201/10636 ,  H05K2201/10681 ,  H05K2203/0117 ,  H05K2203/0278 ,  H05K2203/042 ,  H05K2203/0726 ,  H05K2203/0769 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/184 ,  H05K3/244 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/42 ,  H05K3/426 ,  Y02P70/611

Abstract: Circuit boards with imbedded traces, which may form grooves or trenches are provided. The traces may be at least partially filled with a reflowable conductive material such as solder. The grooves may be selectively furnished with solder while other regions may be empty or void of solder. In assembling electronic components, with or without extended leads, such as surface mount integrated circuits or chips, to the solder core circuit boards, the leads may be placed within the regions of the grooves without solder (contact regions) and then the circuit board may be heated selectively or as a whole to reflow the solder to the bonding or contacting regions to bond the traces to the leads upon cooling. Circuit boards having surface mount devices on both sides may be formed in this manner. Further, tape automated bonded or TAB mounted devices may be directly placed into and bonded to the traces or solder core circuit boards with minimum exposure of the excised TAB leads prior to assembly. In one form, the grooves are plated with copper before they are filled with solder.

Abstract translation: 提供具有嵌入痕迹的电路板，其可以形成凹槽或沟槽。 迹线可以至少部分地填充有可回流的导电材料，例如焊料。 凹槽可以选择性地装备有焊料，而其它区域可能是空的或者没有焊料。 在组装电子部件的情况下，将带有或不具有延伸引线（例如表面贴装集成电路或芯片）的电子部件组装到焊料芯电路板上，可以将引线放置在槽的区域内而不用焊料（接触区域），然后电路板可以 被选择性地或作为整体加热以将焊料回流到接合或接触区域，以在冷却时将迹线结合到引线。 可以以这种方式形成具有两侧表面安装装置的电路板。 此外，胶带自动粘合或TAB安装的装置可以在组装之前以最小的切割的TAB导线的暴露直接放置到轨迹或焊芯电路板中并结合到轨迹或焊芯电路板。 在一种形式中，在填充有焊料之前，将槽镀铜。

公开(公告)号：US4982265A

公开(公告)日：1991-01-01

申请号：US209739

申请日：1988-06-22

Applicant: Masayuki Watanabe ,  Toshio Sugano ,  Seiichiro Tsukui ,  Takashi Ono ,  Yoshiaki Wakashima

Inventor： Masayuki Watanabe ,  Toshio Sugano ,  Seiichiro Tsukui ,  Takashi Ono ,  Yoshiaki Wakashima

IPC: G11C5/00 ,  H01L23/495 ,  H01L25/065 ,  H01L25/10 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  G11C5/00 ,  H01L23/49572 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/1147 ,  H01L2225/06517 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/06579 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/01055 ,  H01L2924/10253 ,  H01L2924/13091 ,  H01L2924/14 ,  H05K2201/10515 ,  H05K2201/10681 ,  H05K2203/1572 ,  H05K3/3447 ,  H05K3/368

Abstract: In the present invention, memory chips are stuck together in stacked fashion by TAB (tape automated bonding), and a multiple memory chip and lead complex like an SOP (small out-line package) is formed of the chips and leads, whereby a memory module of high packaging density can be realized by a flat packaging technique.

Abstract translation: 在本发明中，存储芯片通过TAB（磁带自动键合）以堆叠的方式粘合在一起，并且由芯片和引线形成像SOP（小外线封装）的多存储器芯片和引线复合体，由此存储器 高封装密度的模块可以通过扁平封装技术实现。

公开(公告)号：US4935312A

公开(公告)日：1990-06-19

申请号：US282183

申请日：1988-12-09

Applicant: Hiroshi Nakayama ,  Keijiro Suzuki ,  Susumu Miyata

Inventor： Hiroshi Nakayama ,  Keijiro Suzuki ,  Susumu Miyata

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/498 ,  H05K3/24 ,  H05K3/34

CPC classification number: H05K3/244 ,  H01L23/49572 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K2201/10681 ,  H05K3/3473 ,  Y10S428/929 ,  Y10T428/12681 ,  Y10T428/12708

Abstract: Film carriers for mounting electronic components such as semiconductor chips thereon have lead portions plated with a tin or tin alloy layer and further with an indium layer. The tin or tin alloy layer is 0.1-3 .mu.m thick and the indium layer 0.01-2 .mu.m thick. Alternatively, the leads have a tin or tin alloy plated portion having an indium diffusion layer, with an indium content of 0.2-50 wt %. The carriers are manufactured by a method which comprises plating the leads with tin or a tin alloy and then with indium, with or without heat treatment at 50.degree.-150.degree. C. to form an indium diffusion layer in the tin or tin alloy coating. Plating is done by electroless plating.

Abstract translation: 用于安装诸如半导体芯片的电子部件的薄膜载体具有镀锡或锡合金层并且还具有铟层的引线部分。 锡或锡合金层的厚度为0.1-3μm，铟层为0.01〜2μ​​m厚。 或者，引线具有锡或锡合金电镀部分，其具有铟扩散层，铟含量为0.2-50重量％。 载体的制造方法包括：用锡或锡合金，然后用铟电镀引线，在50〜150℃下进行或不进行热处理，以在锡或锡合金涂层中形成铟扩散层。 电镀是通过化学镀进行的。

公开(公告)号：US4890194A

公开(公告)日：1989-12-26

申请号：US161572

申请日：1987-02-28

Applicant: Lesli A. Derryberry ,  Charles E. Williams

Inventor： Lesli A. Derryberry ,  Charles E. Williams

IPC: H05K1/02 ,  H05K1/14 ,  H05K1/18 ,  H05K3/30 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K3/303 ,  H05K1/141 ,  H05K3/3436 ,  H01L2224/48091 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/16195 ,  H05K1/0201 ,  H05K1/0203 ,  H05K1/147 ,  H05K1/189 ,  H05K2201/049 ,  H05K2201/09072 ,  H05K2201/10681 ,  H05K2201/10727 ,  H05K2201/2036 ,  H05K3/363 ,  Y02P70/613

Abstract: A chip carrier including a connecting strip is supported by a thermally conductive spacer block under its center, which provides a mechanical connection to a circuit board. The external contact pads on the underside of the chip carrier are not bonded directly to traces on the board, but instead are bonded to the connecting strip which is formed from a polymer layer having conductive traces thereon. The conductive traces may be bonded to traces on the circuit board.

Abstract translation: 包括连接条的芯片载体由其中心处的导热间隔块支撑，其提供与电路板的机械连接。 芯片载体下侧的外部接触焊盘不直接粘合到板上的迹线上，而是与由其上具有导电迹线的聚合物层形成的连接条接合。 导电迹线可以结合到电路板上的迹线上。

公开(公告)号：US4857671A

公开(公告)日：1989-08-15

申请号：US260472

申请日：1988-10-17

Applicant: Hirotaka Nakano ,  Thunekazu Yoshino

Inventor： Hirotaka Nakano ,  Thunekazu Yoshino

IPC: H01L21/60 ,  H01L21/603 ,  H01L23/498 ,  H05K3/18 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K3/363 ,  H01L23/498 ,  H01L23/4985 ,  H01L24/81 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H05K2201/10136 ,  H05K2201/10681 ,  H05K2203/0195 ,  H05K3/188 ,  H05K3/3473 ,  Y10T29/49144

Abstract: A film carrier according to this invention comprises a base film, a plurality of conductors formed on the base film, and a plurality of layers formed on the conductors, each being made of a low-melting point bonding metal. A bonding method of this invention comprises the steps of aligning the bonding metal layers of the film carrier with the terminals of an electronic part, and half-melting the bonding metal layers by thermocompression, thereby to electrically connect the conductors of the film carrier to the terminals of the electronic part. The object of the present invention is to provide a film carrier which can serve to connect electronic parts to a circuit by means of a low pressure and at a low temperature, without causing damage to the electronic parts such as semiconductor elements, and also a bonding method using this film carrier.

公开(公告)号：US4835847A

公开(公告)日：1989-06-06

申请号：US183948

申请日：1988-04-20

Applicant: James S. Kamperman

Inventor： James S. Kamperman

IPC: H01L21/00 ,  H01L21/60 ,  H01L23/498 ,  H05K3/34

CPC classification number: H01L24/50 ,  H01L21/67144 ,  H01L23/4985 ,  H05K3/3421 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/14 ,  H05K2201/10681 ,  H05K2203/0195 ,  H05K2203/085 ,  Y02P70/613 ,  Y10T29/49121 ,  Y10T29/49144 ,  Y10T29/53178

Abstract: A fixture for mounting a flexible film electronic device carrier on or for separating the carrier from a substrate which includes a body portion that has a cavity deep enough to contain an electronic device attached to the carrier, a perimeter for contact with a lead bonding area of the film, a surface having openings through which a vacuum can be drawn for holding the flexible film carrier and electronic device attached thereto in the cavity, and a heating element in the perimeter of the body portion; and use thereof to mount a carrier on to separate a carrier from a substrate.

公开(公告)号：US4544238A

公开(公告)日：1985-10-01

申请号：US458396

申请日：1983-01-17

Applicant: Friedrich W. Nickol

Inventor： Friedrich W. Nickol

IPC: H05K1/02 ,  G02F1/1345 ,  H05K1/11 ,  H05K3/34 ,  G02F1/13

CPC classification number: G02F1/1345 ,  H05K1/111 ,  H05K3/3468 ,  H05K2201/09781 ,  H05K2201/10136 ,  H05K2201/10681 ,  H05K2203/044 ,  H05K2203/046 ,  H05K2203/0723 ,  Y02P70/611 ,  Y10S359/90

Abstract: A substrate having a conductor path of solderable material arranged thereon and having a solder layer applied to the conductor path by contact as the conductor path moves along molten solder material. In order to apply the solder material in uniform thickness with little deviation of tolerance onto the conductor path, another conductor path and/or a dummy conductor path of corresponding construction to the latter is arranged on the substrate closely alongside of the conductor path.

Abstract translation: 具有布置在其上的可焊接材料的导体路径的衬底，并且当导体路径沿着熔融焊料材料移动时，具有通过接触施加到导体路径的焊料层。 为了以均匀的厚度施加焊料材料，在导体路径上具有很小的公差偏差，在与导体路径紧密相邻的基板上布置另一个导体路径和/或与之相对应的构造的虚拟导体路径。

公开(公告)号：USRE31704E

公开(公告)日：1984-10-09

申请号：US376638

申请日：1982-05-10

Applicant: Thomas E. Hester

Inventor： Thomas E. Hester

IPC: H01F27/06 ,  H05K1/18

CPC classification number: H01F27/06 ,  H05K1/18 ,  H01F2027/065 ,  H05K2201/1003 ,  H05K2201/10356 ,  H05K2201/10681 ,  Y10T29/49071 ,  Y10T29/49073

Abstract: Electrical apparatus includes electrical coil means formed of multiple turns of enamel-covered electrical wire axially mounted on a core of magnetic material in electromagnetic energy coupling relationship therewith, and a relatively flat flexible electrical cable containing a plurality of spaced parallel conductors extending between the cable ends contains a loop shaped portion extending about an axis of said core over an arcuate distance greater than 180 degrees. The method of adding a plurality of electrical windings to an electrical transformer of the type containing electrical coil means having a primary winding and at least one secondary winding, with said coil means having a central axis and a central passage coaxial with said axis; a core of magnetic material with said core having a portion extending through said central passage to support said coil means thereon, includes the step of forming into a loop extending about the axis of said coil an elongated flat cable of the type containing a plurality of spaced parallel electrical conductors insulated from one another.