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    DISPLAY DEVICE
    111.
    发明申请
    DISPLAY DEVICE 有权
    显示设备

    公开(公告)号：US20100033443A1

    公开(公告)日：2010-02-11

    申请号：US12534921

    申请日：2009-08-04

    Applicant: Shinya HASHIMOTO

    Inventor： Shinya HASHIMOTO

    IPC: G06F3/041

    CPC classification number: G06F3/0416 ,  G02F1/133345 ,  G02F1/13338 ,  G02F1/13439 ,  G06F1/16 ,  G06F3/0412 ,  G06F3/0418 ,  G06F3/044 ,  G06F2203/04103 ,  G06F2203/04107 ,  G06F2203/04111 ,  H05K1/0216 ,  H05K1/11 ,  H05K1/118 ,  H05K3/361 ,  H05K2201/09245 ,  H05K2201/09254

    Abstract: A display device having a highly reliable electrostatic capacitive type touch panel which allows finger touch inputting and possesses excellent detection sensitivity is provided. With respect to X electrodes and Y electrodes which are formed on an electrostatic capacitive type touch panel, either one of the X electrodes and the Y electrodes is divided corresponding to a ratio between the number of X electrodes and the number of Y electrodes, and a floating electrode is formed in gaps formed along with the reduction of area of the electrode thus adjusting the area of the electrode. Due to the contraction of the area of the individual electrode, a noise level can be lowered more compared to lowering of a signal level and hence, an S/N ratio can be increased thus enhancing the detection sensitivity. Further, a line is branched on a flexible printed circuit board, intersecting lines are formed on a back surface of the flexible printed circuit board, and the intersecting lines are arranged to orthogonally intersect with lines formed on a front surface of the flexible printed circuit board thus lowering line capacitance.

    Abstract translation: 提供一种具有高度可靠的静电电容型触摸面板的显示装置，其允许手指触摸输入并且具有优异的检测灵敏度。 对于形成在静电电容型触摸面板上的X电极和Y电极，X电极和Y电极中的任一个根据X电极的数量与Y电极的数量相对应而分割， 浮动电极形成在与电极的面积减小形成的间隙中，从而调节电极的面积。 由于单个电极的面积的缩小，与信号电平的降低相比，可以降低噪声水平，因此可以增加S / N比，从而提高检测灵敏度。 此外，线在柔性印刷电路板上分支，在柔性印刷电路板的后表面上形成相交线，并且交叉线布置成与柔性印刷电路板的前表面上形成的线垂直相交 从而降低线路电容。

    METHOD FOR MANUFACTURING PRINTED-CIRCUIT BOARD
    112.
    发明申请
    METHOD FOR MANUFACTURING PRINTED-CIRCUIT BOARD 有权
    制造印刷电路板的方法

    公开(公告)号：US20090321266A1

    公开(公告)日：2009-12-31

    申请号：US12490470

    申请日：2009-06-24

    Applicant: Yoshimi Egawa ,  Harufumi Kobayashi

    Inventor： Yoshimi Egawa ,  Harufumi Kobayashi

    IPC: H05K3/00

    CPC classification number: H05K3/242 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/111 ,  H05K1/114 ,  H05K3/06 ,  H05K3/42 ,  H05K2201/09254 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2203/1572 ,  H05K2203/175 ,  Y10T29/49156 ,  Y10T29/49162 ,  H01L2924/00014

    Abstract: There is provided a method for manufacturing a printed circuit board having an insulative board and a plurality of electroconductive pads arranged in a grid shape on the insulative board, the method comprising: a step for forming an electroconductive film on the insulative board; a step for forming a pattern on the electroconductive film so as to form the electroconductive pads, a lead wire connected to at least one of the electroconductive pads, and inter-pad wiring for electrically connecting each of the electroconductive pads not connected to the lead wire to any of the electroconductive pads connected to the lead wire, the inter-pad wiring being disposed between mutually adjacent electroconductive pads; a step for plating each of the electroconductive pads by immersing the insulative board in a plating bath and energizing each of the electroconductive pads through the lead wire; and a step for removing the inter-pad wiring.

    Abstract translation: 提供了一种用于制造印刷电路板的方法，所述印刷电路板具有绝缘板和在所述绝缘板上排列成格子状的多个导电焊盘，所述方法包括：在所述绝缘板上形成导电膜的步骤; 用于在导电膜上形成图形以形成导电焊盘的步骤，连接到至少一个导电焊盘的引线和用于电连接未连接到引线的每个导电焊盘的衬垫布线 连接到引线的任何导电焊盘，衬垫布线设置在相互相邻的导电焊盘之间; 通过将绝缘板浸入电镀槽中并对每个导电焊盘进行电镀，并通过引线激励每个导电焊盘; 以及去除垫间布线的步骤。

    Placement and routing of ECC memory devices for improved signal timing
    113.
    发明申请
    Placement and routing of ECC memory devices for improved signal timing 有权
    ECC存储器件的放置和布线，以改善信号时序

    公开(公告)号：US20090154211A1

    公开(公告)日：2009-06-18

    申请号：US12000489

    申请日：2007-12-13

    Applicant: Pingyu Qu ,  Barrie Patrick Gahan

    Inventor： Pingyu Qu ,  Barrie Patrick Gahan

    IPC: G11C5/02 ,  H04S1/00

    CPC classification number: G11C5/025 ,  G06F11/1044 ,  G11C5/04 ,  H05K1/181 ,  H05K2201/09254 ,  H05K2201/10159 ,  Y02P70/611 ,  Y10T29/49002

    Abstract: Various exemplary embodiments are a printed circuit board and related method of manufacturing, the printed circuit board including a memory controller, a plurality of synchronous data memory devices, each synchronous memory device including at least one data pin and at least one address/command pin, an ECC memory device including at least one ECC data pin and at least one ECC address/command pin, and at least one surface. In various exemplary embodiments, the plurality of synchronous data memory devices are arranged around a central location on the at least one surface and each synchronous data memory device is oriented such that the at least one data pin is further from the memory controller than the at least one address/command pin.

    Abstract translation: 各种示例性实施例是印刷电路板和相关的制造方法，印刷电路板包括存储器控制器，多个同步数据存储器件，每个同步存储器件包括至少一个数据引脚和至少一个地址/命令引脚， ECC存储器件，其包括至少一个ECC数据引脚和至少一个ECC地址/命令引脚，以及至少一个表面。 在各种示例性实施例中，多个同步数据存储器设备围绕至少一个表面上的中心位置布置，并且每个同步数据存储器件被定向成使得至少一个数据引脚比至少一个数据引脚远离存储器控制器 一个地址/命令引脚。

    CIRCUIT TOPOLOGY FOR MULTIPLE LOADS
    114.
    发明申请
    CIRCUIT TOPOLOGY FOR MULTIPLE LOADS 有权
    多负载电路拓扑

    公开(公告)号：US20090146759A1

    公开(公告)日：2009-06-11

    申请号：US11965744

    申请日：2007-12-28

    Applicant: SHOU-KUO HSU ,  HSIAO-CHUAN TU ,  YU-CHANG PAI

    Inventor： SHOU-KUO HSU ,  HSIAO-CHUAN TU ,  YU-CHANG PAI

    IPC: H01P5/12

    CPC classification number: H01P5/12 ,  H05K1/0246 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10022

    Abstract: A circuit topology for multiple loads includes a driving terminal, a first node coupled to the driving terminal via a main transmission line, a second node coupled to the first node via a first branch transmission line, a first receiving terminal coupled to the first node via a second branch transmission line, a third node coupled to the second node via a third branch transmission line, and a second receiving terminal coupled to the second node via a fourth branch transmission line. The second branch transmission line is longer than the first transmission line, and a first resistor is connected in the second branch transmission line. The third branch transmission line is longer than the fourth branch transmission line, and a second resistor is connected in the third branch transmission line.

    Abstract translation: 用于多个负载的电路拓扑包括驱动终端，经由主传输线耦合到驱动终端的第一节点，经由第一分支传输线耦合到第一节点的第二节点，经由第一节点经由 第二分支传输线，经由第三分支传输线耦合到第二节点的第三节点，以及经由第四分支传输线耦合到第二节点的第二接收终端。 第二分支传输线比第一传输线长，并且第一电阻器连接在第二分支传输线路中。 第三分支传输线比第四分支传输线长，并且第二电阻器连接在第三分支传输线路中。

    PRINTED CIRCUIT BOARD
    116.
    发明申请
    PRINTED CIRCUIT BOARD 审中-公开
    印刷电路板

    公开(公告)号：US20080284538A1

    公开(公告)日：2008-11-20

    申请号：US11834705

    申请日：2007-08-07

    Applicant: SHOU-KUO HSU

    Inventor： SHOU-KUO HSU

    IPC: H03H7/38

    CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/09254 ,  H05K2201/0969

    Abstract: A printed circuit board includes a signal layer, a first reference plane layer, and a second reference plane layer. At least one transmission line is arranged on the signal layer. The transmission line includes a main transmission line, and two branch transmission lines connected to an end of the main transmission line. The first reference plane layer is disposed below the signal layer for the main transmission line. The second reference plane layer is disposed below the first reference plane layer for the branch transmission lines, to increase impedance of the two branch transmission lines.

    Abstract translation: 印刷电路板包括信号层，第一参考平面层和第二参考平面层。 在信号层上布置至少一条传输线。 传输线包括主传输线和连接到主传输线的一端的两条分支传输线。 第一参考平面层设置在用于主传输线的信号层下方。 第二参考平面层设置在用于分支传输线的第一参考平面层的下方，以增加两个分支传输线的阻抗。

    Surface mounting structure for a surface mounting electronic component
    117.
    发明申请
    Surface mounting structure for a surface mounting electronic component 有权
    表面安装电子部件的表面安装结构

    公开(公告)号：US20080066955A1

    公开(公告)日：2008-03-20

    申请号：US11901078

    申请日：2007-09-13

    Applicant: Takamasa Nodo ,  Haruo Takagi

    Inventor： Takamasa Nodo ,  Haruo Takagi

    IPC: H05K1/11

    CPC classification number: H05K1/111 ,  H05K3/3442 ,  H05K2201/09254 ,  H05K2201/09281 ,  H05K2201/09381 ,  H05K2201/09727 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y02P70/613

    Abstract: A surface mounting structure for a surface mounting electronic component comprises an electronic component a land, a wiring, and an electrical connection pattern. The electronic component has electrodes at opposite ends thereof. The land is connected to each electrode through a solder. The wiring is connected to the land and has a width which is smaller than a width of the electronic component in a width direction thereof. The wiring is connected to the electrical connection pattern. The electrical connection pattern has on a side on which the wiring is connected to the electrical connection pattern a width which is larger than the width of the electronic component in the width direction thereof.

    Abstract translation: 用于表面安装电子部件的表面安装结构包括电子部件，焊盘，布线和电连接图案。 电子部件在其相对端具有电极。 焊盘通过焊料连接到每个电极。 布线连接到台面，其宽度小于电子部件的宽度方向的宽度。 接线连接到电气连接图案。 电连接图案具有在电连接图案的与电子部件的宽度方向的宽度大的宽度上连接的一侧。

    Method and apparatus for distributing signals over jig-plates
    118.
    发明授权
    Method and apparatus for distributing signals over jig-plates 有权
    用于在夹具板上分配信号的方法和装置

    公开(公告)号：US07332919B1

    公开(公告)日：2008-02-19

    申请号：US11232843

    申请日：2005-09-21

    Applicant: Ronald Ho ,  Robert J. Drost ,  Arthur R. Zingher

    Inventor： Ronald Ho ,  Robert J. Drost ,  Arthur R. Zingher

    IPC: G01R31/02

    CPC classification number: H01L23/538 ,  H01L25/0655 ,  H01L2924/0002 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/183 ,  H05K2201/09254 ,  H05K2201/10674 ,  H01L2924/00

    Abstract: One embodiment of the present invention provides a system for distributing signals through a jig-plate in a computer system. The jig-plate contains alignment features that assist in positioning semiconductor chips in relation to the jig-plate. In addition, the jig-plate contains one or more embedded signal routing layers. These metal routing layers provide one or more signal routes for the distribution of signals through the jig-plate to semiconductor chips which have been aligned with the jig-plate. Note that routing the signals through the jig-plate facilitates the distribution of the signals without requiring that the signals be routed through the semiconductor chips in the jig-plate.

    Abstract translation: 本发明的一个实施例提供一种用于通过计算机系统中的夹具板来分配信号的系统。 夹具板包含有助于相对于夹具板定位半导体芯片的对准特征。 另外，夹具板包含一个或多个嵌入式信号路由层。 这些金属布线层提供了一个或多个用于将通过夹具板的信号分配到已经与夹具板对准的半导体芯片的信号路线。 注意，通过夹具板布置信号有助于信号的分配，而不需要信号通过夹具板中的半导体芯片布线。

    Printed circuit board including a notch filter for attenuating radio frequency interference
    120.
    发明授权
    Printed circuit board including a notch filter for attenuating radio frequency interference 有权
    印刷电路板包括用于衰减射频干扰的陷波滤波器

    公开(公告)号：US07327208B2

    公开(公告)日：2008-02-05

    申请号：US11066885

    申请日：2005-02-24

    Applicant: Wulin Shi ,  Frank Xiaohui Li

    Inventor： Wulin Shi ,  Frank Xiaohui Li

    IPC: H03H7/01 ,  H01P3/08 ,  H01P9/02

    CPC classification number: H01P1/203 ,  H05K1/0233 ,  H05K1/165 ,  H05K2201/09254 ,  H05K2201/1006

    Abstract: A printed circuit board (PCB) including a notch filter, or other suitable filter, is implemented in a communication device for attenuating RFI in transmissions sent from the communication device. The filter includes filter line that runs between at least two conductor layers on the PCB, in a substantially repeating pattern, which maximizes the space available on each conductor layer for additional uses.

    Abstract translation: 包括陷波滤波器或其它合适的滤波器的印刷电路板（PCB）被实现在用于衰减从通信设备发送的传输中的RFI的通信设备中。 滤波器包括在PCB上的至少两个导体层之间延伸的滤波器线，其基本上是重复的图案，其使每个导体层上的可用空间最大化以用于附加用途。

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