公开(公告)号：US20110083881A1

公开(公告)日：2011-04-14

申请号：US12969478

申请日：2010-12-15

Applicant: Vinh T. Nguyen ,  Claude A.S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A.S. Hamrick

IPC: H05K1/02 ,  H05K3/00

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayer circuit device having electrically isolated tightly spaced electrical current carrying traces and including a first nonconductive substrate having a first conductive material affixed to a first side thereof to form a first ground plane, a plurality of elongated first conductive traces formed on a second side of the first non-conductive substrate and having transverse widths of 50 microns or less and rising above the upper surface of the first substrate to a height equal to or greater than the widths thereof such that a transverse cross section of the first conductive traces has a height-to-width ratio equal to or exceeding 1, adjacent ones of the first traces being separated from each other by first elongated spaces, the first conductive traces being variously useful as ground lines, signal lines and/or power lines.

Abstract translation: 一种具有电隔离紧密间隔的电流载流迹线并包括第一非导电基底的多层电路器件，所述第一非导电基底具有固定到其第一侧的第一导电材料以形成第一接地平面;多个细长的第一导电迹线，形成在第二侧 第一非导电衬底并且具有50微米或更小的横向宽度并且在第一衬底的上表面上方升高到等于或大于其宽度的高度，使得第一导电迹线的横截面具有高度 宽度比等于或超过1，相邻的第一迹线通过第一细长空间彼此分开，第一导电迹线在各种不同地用作接地线，信号线和/或电力线。

公开(公告)号：US07874065B2

公开(公告)日：2011-01-25

申请号：US12263416

申请日：2008-10-31

Applicant: Vinh T. Nguyen ,  Claude A. S. Hamrick

Inventor： Vinh T. Nguyen ,  Claude A. S. Hamrick

IPC: H05K3/36

CPC classification number: H05K3/1258 ,  H05K3/108 ,  H05K3/125 ,  H05K3/243 ,  H05K3/4611 ,  H05K3/4623 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09536 ,  H05K2201/098 ,  H05K2203/013 ,  H05K2203/0568 ,  Y10T29/49002 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A process for making a multi-layered circuit board having electrical current traces includes providing a substrate having a 1st layer of conductive material to form a ground plane, plurality of metallic 1st traces on a 2nd side of the substrate having widths of approximately 25 microns or less, developing 1st ribs of photoresist forming 1st walls rising above upper surface of an adjacent seed layer trace, depositing 1st conductive signal traces having a thickness exceeding 25 microns into channels and over seed layer traces and stripping the ribs to leave 1st conductive traces having a height-to-transverse ratio exceeding 1.

Abstract translation: 用于制造具有电流迹线的多层电路板的方法包括提供具有第一层导电材料以形成接地平面的衬底，在衬底的第二面上的多个金属第一迹线具有约25微米的宽度或 在相邻的种子层迹线的上表面上方形成第一壁的第一肋形成第一肋，将厚度超过25微米的第一导电信号迹线沉积到通道中并且超过种子层迹线并剥离肋，以留下第一导电迹线， 高度与横向之比超过1。

公开(公告)号：US07800915B2

公开(公告)日：2010-09-21

申请号：US11812508

申请日：2007-06-19

Applicant: Lars Engblom ,  Mats Johansson ,  Peter Scott

Inventor： Lars Engblom ,  Mats Johansson ,  Peter Scott

IPC: H01R12/16

CPC classification number: H05K1/0218 ,  H05K1/0298 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09327

Abstract: The present invention relates to a method and a printed board assembly for use in a MicroTCA system, wherein backplane pin connectors of the printed board assembly are arranged to be received in receiving connectors of a backplane interconnect, characterized in that it comprises at least one switch unit which is arranged with physical output/input ports that have physical port numbers that can be overridden by logical port numbers, an optimal routing of a number of sets of conductive threads in the printed board assembly arranged so that none of the conductive threads cross over each other while connecting physical output/input ports of the switch units with the backplane pin connectors, and printed circuit board layers arranged to shield signals travelling in the conductive threads in conductive layers of the printed circuit board layers from any significant crosstalk.

Abstract translation: 本发明涉及一种用于MicroTCA系统的方法和印刷电路板组件，其中印刷电路板组件的背板针连接器被布置成接收在背板互连的接收连接器中，其特征在于，它包括至少一个开关 具有物理输出/输入端口的单元，物理输出/输入端口具有可被逻辑端口号覆盖的物理端口号，布置在印刷电路板组件中的多组导电螺纹的最佳布线，使得没有导电线交叉 彼此相连，同时将开关单元的物理输出/输入端口与背板引脚连接器连接，并且印刷电路板层布置成屏蔽在印刷电路板层的导电层中传导的导电线中的信号免于任何显着的串扰。

公开(公告)号：US20100062727A1

公开(公告)日：2010-03-11

申请号：US12520965

申请日：2007-12-27

Applicant: Shigeru Kemmochi ,  Keisuke Fukamachi ,  Kazuhiro Hagiwara

Inventor： Shigeru Kemmochi ,  Keisuke Fukamachi ,  Kazuhiro Hagiwara

IPC: H04B1/40

CPC classification number: H04B1/44 ,  H01L2924/0002 ,  H05K1/0243 ,  H05K2201/093 ,  H05K2201/09327 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A high-frequency device having high-frequency-signal-treating circuits in and on a laminate substrate comprising pluralities of dielectric layers having conductor patterns, the high-frequency-signal-treating circuits having amplifier circuits and switch circuits; terminals including input and output terminals of high-frequency signals, the power supply terminals of the amplifier circuits and the power supply terminals of the switch circuits being formed on one main surface of the laminate substrate; power supply lines each having one end connected to each of the power supply terminals of the amplifier circuits and power supply lines each having one end connected to each of the power supply terminals of the switch circuits being formed on one dielectric layer to constitute a power supply line layer; a first ground electrode being arranged on the side of the main surface with respect to the power supply line layer, the first ground electrode overlapping at least part of the power supply lines in a lamination direction; a second ground electrode being arranged on the opposite side of the first ground electrode with respect to the power supply line layer, the second ground electrode overlapping at least part of the power supply lines in a lamination direction; and the high-frequency-signal-treating circuits being arranged on the opposite side of the power supply line layer with respect to the second ground electrode.

Abstract translation: 一种具有高频信号处理电路的高频信号处理电路，包括具有导体图形的多个电介质层的层叠基板中及其上的高频信号处理电路，高频信号处理电路具有放大电路和开关电路; 包括高频信号的输入和输出端子的端子，放大器电路的电源端子和开关电路的电源端子形成在层叠基板的一个主表面上; 电源线各自具有连接到放大器电路的每个电源端的一端和各自具有连接到开关电路的每个电源端的一端的电源线，形成在一个电介质层上，以构成电源 线层; 第一接地电极相对于电源线层布置在主表面侧，第一接地电极在层叠方向上与至少一部分电源线重叠; 第二接地电极相对于电源线层布置在第一接地电极的相对侧上，第二接地电极在层叠方向上与至少一部分电源线重叠; 并且高频信号处理电路相对于第二接地电极布置在电源线层的相对侧上。

公开(公告)号：US07435912B1

公开(公告)日：2008-10-14

申请号：US10145436

申请日：2002-05-14

Applicant: Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

Inventor： Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

IPC: H01R12/04 ,  H05K1/11

CPC classification number: H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/09327 ,  H05K2201/09718 ,  Y10T29/49165

Abstract: A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.

Abstract translation: 电路板包括信号线路由的多个信号层以及提供功率参考平面的参考平面层。 为了在不同的信号层连接信号线，通孔通过至少一个信号层和至少一个参考平面层。 在一个信号层处，围绕通孔限定第一间隙（或抗焊盘）。 在参考平面层，围绕通孔限定第二间隙。 第二间隙的尺寸大于第一间隙，以使通孔的阻抗尽可能接近通孔电连接到的信号线的阻抗。

公开(公告)号：US20070102092A1

公开(公告)日：2007-05-10

申请号：US11272590

申请日：2005-11-10

Applicant: John Dangler ,  Matthew Doyle

Inventor： John Dangler ,  Matthew Doyle

IPC: B32B38/00 ,  B32B41/00

CPC classification number: B32B37/12 ,  B32B2457/08 ,  H05K1/0393 ,  H05K3/386 ,  H05K3/4611 ,  H05K3/4635 ,  H05K2201/0195 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09881

Abstract: A method for manufacturing multilayer flexible circuits is disclosed. The cross-sectional area of an unoccupied signal layer volume is initially determined. The unoccupied signal layer includes multiple conductive elements, and the unoccupied signal layer volume is formed between two of the conductive elements. Next, the thickness of an adhesive layer for filling the unoccupied signal layer volume is determined. Finally, the thickness of the adhesive layer is adjusted such that the adhesive layer only fills the unoccupied signal layer volume while the two conductive elements come in direct contact with a dielectric layer without any adhesive in between.

Abstract translation: 公开了一种制造多层柔性电路的方法。 初始确定未占用信号层体积的横截面面积。 未占用的信号层包括多个导电元件，并且在两个导电元件之间形成未占用的信号层体积。 接下来，确定用于填充未占用信号层体积的粘合剂层的厚度。 最后，调节粘合剂层的厚度，使得粘合剂层仅填充未占用的信号层体积，同时两个导电元件与电介质层直接接触，而两者之间没有任何粘合剂。

公开(公告)号：US20070069932A1

公开(公告)日：2007-03-29

申请号：US11515763

申请日：2006-09-06

Applicant: Hiroshi Isoda

Inventor： Hiroshi Isoda

IPC: H03M3/00

CPC classification number: H04B1/28 ,  H01L23/50 ,  H01L23/552 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6677 ,  H01L2224/16 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/0298 ,  H05K2201/0723 ,  H05K2201/09327

Abstract: A tuner section is provided on one surface of a multilayered substrate, and a demodulating section on another surface of the multilayered substrate. The multilayered substrate further includes: an analog GND layer connected to the tuner section; a digital GND layer connected to the demodulating section; a shield GND layer which is provided between the analog GND layer and the digital GND layer; and insulation layers each provided (i) between the analog GND layer and shield GND layer, or (ii) between the digital GND layer and shield GND layer so as to electrically disconnect the shield GND layer from the analog GND layer and the digital GND layer. This allows the tuner section and the demodulating section to be respectively arranged on different surfaces of the substrate, for the purpose of downsizing of the receiving device, and yet allows the tuner section from being influenced by a harmonic signal generated in the demodulating section.

Abstract translation: 调谐器部分设置在多层基板的一个表面上，以及在多层基板的另一表面上的解调部分。 多层基板还包括：连接到调谐器部分的模拟GND层; 连接到解调部分的数字GND层; 设置在模拟GND层和数字GND层之间的屏蔽GND层; 以及在模拟GND层和屏蔽GND层之间设置（i）的绝缘层，或者（ii）数字GND层和屏蔽GND层之间，以使屏蔽GND层与模拟GND层和数字GND层电连接 。 为了减小接收装置的尺寸，这使得调谐器部分和解调部分分别布置在基板的不同表面上，并且允许调谐器部分受到在解调部分中产生的谐波信号的影响。

公开(公告)号：US20050195583A1

公开(公告)日：2005-09-08

申请号：US10791291

申请日：2004-03-03

Applicant: Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

Inventor： Shadi AbuGhazaleh ,  Robert Baxter ,  Rehan Mahmood ,  Alan Miller ,  Michael O'Connor

IPC: H05K1/00 ,  H05K1/02 ,  H05K1/16 ,  H05K7/06

CPC classification number: H05K1/0228 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/0723 ,  H05K2201/09327 ,  H05K2201/10189 ,  H05K2201/10689 ,  Y10S439/941

Abstract: A compensating advanced feature patch panel that can include removable modular or fixed electronic components located directly on the patch panel which are separately or in combination capable of providing advanced features such as device detection and power insertion. The patch panel provides communications between an insulation displacement connector (IDC) at a PD/User end, and any standard interface type using unshielded twisted pair cables, such as an RJ45 connector at a switch end at performance levels of at least category 3, 5, 5e, 6 and/or higher (e.g. 6e or 7) and equivalent performance levels by compensating for the active electronics used in providing advanced features. Compensation is achieved in part through the separation and isolation of active and communication circuit elements.

Abstract translation: 补偿高级功能接线板，其可以包括直接位于接线板上的可拆卸模块或固定电子部件，其分开地或组合地能够提供诸如设备检测和功率插入的高级特征。 接线板提供PD /用户端的绝缘位移连接器（IDC）与使用非屏蔽双绞线电缆的任何标准接口类型之间的通信，例如在开关端的RJ45连接器，性能水平至少为3,5 ，5 e，6和/或更高（例如6 e或7）和等效的性能水平，通过补偿用于提供高级功能的有源电子元件。 补偿部分通过主动和通信电路元件的分离和隔离来实现。

公开(公告)号：US20050023241A1

公开(公告)日：2005-02-03

申请号：US10917553

申请日：2004-08-11

Applicant: Joel Goergen

Inventor： Joel Goergen

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/38 ,  H05K3/42 ,  H05K3/46 ,  H01B13/00

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

公开(公告)号：US20030177638A1

公开(公告)日：2003-09-25

申请号：US10068745

申请日：2002-02-05

Applicant: Force 10 Networks, Inc.

Inventor： Joel R. Goergen

IPC: H05K003/02 ,  H05K003/10

CPC classification number: H05K3/4688 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/0271 ,  H05K1/116 ,  H05K3/382 ,  H05K3/429 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/0209 ,  H05K2201/044 ,  H05K2201/0723 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09318 ,  H05K2201/09327 ,  H05K2201/09354 ,  H05K2201/09381 ,  H05K2201/09454 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/09718 ,  H05K2201/09781 ,  H05K2203/061 ,  Y10T29/49117 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49162 ,  Y10T29/49163 ,  Y10T29/49165

Abstract: The disclosed board fabrication techniques and design features enable the construction of a reliable, high-layer-count, and economical backplane for routers and the like that require a large number of signaling paths across the backplane at speeds of 2.5 Gbps or greater, as well as distribution of significant amounts of power to router components. The disclosed techniques and features allow relatively thick (e.g., three- or four-ounce copper) power distribution planes to be combined with large numbers of high-speed signaling layers in a common backplane. Using traditional techniques, such a construction would not be possible because of the number of layers required and the thickness of the power distribution layers. The disclosed embodiments use novel layer arrangements, material selection, processing techniques, and panel features to produce the desired high-speed layers and low-noise high-power distribution layers in a single mechanically stable board.

Abstract translation: 所公开的板制造技术和设计特征使得能够构建用于路由器等的可靠的，高层次的和经济的背板，其需要以2.5Gbps或更高的速度跨越背板的大量信令路径，以及 作为路由器组件的大量功率分配。 所公开的技术和特征允许相对较厚（例如，三或四盎司铜）功率分配平面与公共背板中的大量高速信号层组合。 使用传统技术，由于需要的层数和配电层的厚度，这种结构将是不可能的。 所公开的实施例使用新颖的层布置，材料选择，处理技术和面板特征来在单个机械稳定的板中产生期望的高速层和低噪声大功率分配层。