公开(公告)号：US20120211273A1

公开(公告)日：2012-08-23

申请号：US13417023

申请日：2012-03-09

Applicant: Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

Inventor： Joseph Kuczynski ,  Kevin Albert Splittstoesser ,  Timothy Jerome Tofil ,  Paul Alan Vermilyea

IPC: H05K1/11 ,  H05K3/00

CPC classification number: H05K3/429 ,  B33Y80/00 ,  H05K1/0237 ,  H05K1/115 ,  H05K3/0082 ,  H05K3/184 ,  H05K3/422 ,  H05K2201/09645 ,  H05K2203/056 ,  H05K2203/0565 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: An enhanced mechanism is disclosed for via stub elimination in printed wiring boards (PWBs) and other substrates. In one embodiment, the substrate includes a plurality of insulator layers and internal conductive traces. First and second through-holes extend completely through the substrate and respectively pass through first and second ones of the internal conductive traces, which are at different depths within the substrate. Photolithographic techniques are used to generate plated-through-hole (PTH) plugs of controlled, variable depth in the through-holes before first and second conductive vias are respectively plated onto the first and second through-holes. The depth of these PTH plugs is controlled (e.g., using a photomask and/or variable laser power) to prevent the first and second conductive vias from extending substantially beyond the first and second internal conductive traces, respectively, and thereby prevent via stubs from being formed in the first place.

Abstract translation: 公开了用于印刷电路板（PWB）和其它基板中的通孔短截线的增强机构。 在一个实施例中，衬底包括多个绝缘体层和内部导电迹线。 第一和第二通孔完全延伸穿过衬底并且分别穿过在衬底内的不同深度的第一和第二内部导电迹线。 光刻技术用于在将第一和第二导电通孔分别电镀到第一和第二通孔之前，在通孔中产生受控的可变深度的电镀通孔（PTH）插头。 控制这些PTH插头的深度（例如，使用光掩模和/或可变激光功率）来防止第一和第二导电通孔分别基本上延伸超出第一和第二内部导电迹线，从而防止通孔短路 形成在第一位。

公开(公告)号：US08227710B2

公开(公告)日：2012-07-24

申请号：US11987255

申请日：2007-11-28

Applicant: Kenji Nagase ,  Kenichi Kawabata

Inventor： Kenji Nagase ,  Kenichi Kawabata

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch.In a semiconductor-embedded substrate, a conductive pattern is formed on both sides of a core substrate and a semiconductor device is placed in a resin layer stacked over the core substrate. The resin layer has via-holes so that the conductive pattern and a bump of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

Abstract translation: 本发明提供一种布线结构等，其可以在将布线层完全连接到待布线的本体上，同时保持两个相邻布线层之间的绝缘，并且由于间距变窄而实现高密度封装。 在半导体嵌入式基板中，在芯基板的两面形成导体图案，将半导体装置配置在层叠在芯基板上的树脂层中。 树脂层具有通孔，使得导电图案和半导体器件的凸块从树脂层突出。 在通孔内部，凸块和导电图案分别连接到横截面积已经朝向通孔底部增加的通孔电极部分。 在通孔电极部分和通孔的内壁的上部之间限定空隙。

公开(公告)号：US08198548B2

公开(公告)日：2012-06-12

申请号：US12508158

申请日：2009-07-23

Applicant: Keith Bryan Hardin ,  John Thomas Fessler ,  Paul Kevin Hall ,  Robert Aaron Oglesbee

Inventor： Keith Bryan Hardin ,  John Thomas Fessler ,  Paul Kevin Hall ,  Robert Aaron Oglesbee

IPC: H05K1/16

CPC classification number: H05K3/4046 ,  H05K1/0231 ,  H05K1/0233 ,  H05K1/0248 ,  H05K1/0251 ,  H05K1/0298 ,  H05K1/184 ,  H05K2201/09645 ,  H05K2201/10984

Abstract: A Z-directed capacitor component for insertion into a printed circuit board while allowing electrical connection to internal conductive planes contained within the PCB. In one embodiment the Z-directed capacitor component utilizes semi-cylindrical metallic sheets. In another embodiment, stack annular metallic disks are used. The Z-directed capacitor component mounts within the thickness of the PCB allowing other components to be mounted over it. The body may contain one or more conductors and may include one or more surface channels or wells extending along at least a portion of the length of the body. Methods for mounting Z-directed components are also provided.

Abstract translation: 用于插入印刷电路板的Z导向电容器组件，同时允许电连接到包含在PCB内部的内部导电平面。 在一个实施例中，Z导向电容器部件使用半圆柱形金属片。 在另一个实施例中，使用堆叠的环形金属盘。 Z导向电容器组件安装在PCB的厚度内，允许其他组件安装在其上。 主体可以包含一个或多个导体并且可以包括沿着身体的长度的至少一部分延伸的一个或多个表面通道或孔。 还提供了用于安装Z向定向部件的方法。

公开(公告)号：US20110198723A1

公开(公告)日：2011-08-18

申请号：US13095317

申请日：2011-04-27

Applicant: Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

Inventor： Todd B. Myers ,  Nicholas R. Watts ,  Eric C. Palmer ,  Jui Min Lim

IPC: H01L29/92

CPC classification number: H01L21/76897 ,  H01L21/486 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/64 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/1902 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/06 ,  H05K3/4053 ,  H05K3/421 ,  H05K2201/086 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09663 ,  H05K2201/09763 ,  H05K2201/09809 ,  H05K2201/09827 ,  H05K2201/09981 ,  Y10S257/916 ,  Y10T29/435 ,  Y10T29/49002 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/49147 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a device associated with a via includes forming an opening or via, and forming at least a pair of conducting paths within the via. Also disclosed is a via having at pair of conducting paths therein.

Abstract translation: 形成与通孔相关的器件的方法包括形成开口或通孔，并在通孔内形成至少一对导电通路。 还公开了一种在其中具有一对导电路径的通孔。

公开(公告)号：US07935895B2

公开(公告)日：2011-05-03

申请号：US11535368

申请日：2006-09-26

Applicant: David D. Senk ,  Joe D. Dickson

Inventor： David D. Senk ,  Joe D. Dickson

IPC: H05K1/11 ,  H01K3/10

CPC classification number: H05K3/403 ,  H05K1/115 ,  H05K3/0032 ,  H05K3/0082 ,  H05K3/027 ,  H05K3/043 ,  H05K3/061 ,  H05K3/429 ,  H05K2201/09645 ,  Y10T29/49165

Abstract: Methods and apparatus for creating independent circuit connections within a through-hole of a substrate are described. According to one aspect of the present invention, a method includes defining a through-hole in a substrate, applying a conductive plating to a holewall of the through-hole, and selectively removing at least a first area of the plating. The through-hole has a height relative to a first axis, and the perimeter of the through-hole at each point along the first axis is approximately the same. Selectively removing the first area of the plating includes defining second areas of the plating. At least one of the plurality of second areas does not span a height of the hole.

Abstract translation: 描述了用于在衬底的通孔内形成独立电路连接的方法和装置。 根据本发明的一个方面，一种方法包括在衬底中限定通孔，将导电镀层施加到通孔的孔壁，以及选择性地去除电镀的至少第一区域。 通孔具有相对于第一轴线的高度，并且沿着第一轴线的每个点处的通孔的周边大致相同。 选择性地移除电镀的第一区域包括限定电镀的第二区域。 多个第二区域中的至少一个不跨越孔的高度。

公开(公告)号：US20100321900A1

公开(公告)日：2010-12-23

申请号：US12871072

申请日：2010-08-30

Applicant: Bok Kyu CHOI ,  Sang Joon LIM ,  Eul Chul JANG

Inventor： Bok Kyu CHOI ,  Sang Joon LIM ,  Eul Chul JANG

IPC: H05K7/00

CPC classification number: H01L25/0657 ,  H01L2224/16 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06572 ,  H05K1/0222 ,  H05K1/115 ,  H05K2201/09645 ,  H05K2201/09809

Abstract: A circuit board having a board body includes a via structure. The via structure includes a conductive connector passing through the board body and a conductive shield member surrounding at least a portion of the conductive connector. The shield member prevents distortion of a data signal applied to the conductive connector, and also intercepts electromagnetic waves generated by the conductive connector.

Abstract translation: 具有板主体的电路板包括通孔结构。 通孔结构包括穿过板体的导电连接器和围绕导电连接器的至少一部分的导电屏蔽构件。 屏蔽构件防止施加到导电连接器的数据信号的变形，并且还拦截由导电连接器产生的电磁波。

公开(公告)号：US07830018B2

公开(公告)日：2010-11-09

申请号：US11863579

申请日：2007-09-28

Applicant: Teck Kheng Lee

Inventor： Teck Kheng Lee

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H05K13/00 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/115 ,  H05K3/4602 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09645 ,  H05K2201/09854 ,  H01L2924/00

Abstract: Partitioned vias, interconnects, and substrates that include such vias and interconnects are disclosed herein. In one embodiment, a substrate has a non-conductive layer and a partitioned via formed in a portion of the non-conductive layer. The non-conductive layer includes a top side, a bottom side, and a via hole extending between the top and bottom sides and including a sidewall having a first section a second section. The partitioned via includes a first metal interconnect within the via on the first section of the sidewall and a second metal interconnect within the via hole on the second section of the sidewall and electrically isolated from the first metal interconnect. In another embodiment, the first metal interconnect is separated from the second metal interconnect by a gap within the via hole.

Abstract translation: 包括这种通孔和互连的分隔的过孔，互连和衬底在本文中公开。 在一个实施例中，衬底具有形成在非导电层的一部分中的非导电层和分隔通孔。 非导电层包括在顶侧和底侧之间延伸的顶侧，底侧和通孔，并且包括具有第一部分和第二部分的侧壁。 分隔通孔包括在侧壁的第一部分上的通孔内的第一金属互连和在侧壁的第二部分上的通孔内的第二金属互连，并与第一金属互连电隔离。 在另一个实施例中，第一金属互连通过通孔内的间隙与第二金属互连分开。

公开(公告)号：US20100163296A1

公开(公告)日：2010-07-01

申请号：US12468058

申请日：2009-05-19

Applicant: Cheng-Ta Ko ,  Min-Lin Lee ,  Wei-Chung Lo ,  Shur-Fen Liu ,  Jinn-Shing King ,  Shinn-Juh Lai ,  Yu-Hua Chen

Inventor： Cheng-Ta Ko ,  Min-Lin Lee ,  Wei-Chung Lo ,  Shur-Fen Liu ,  Jinn-Shing King ,  Shinn-Juh Lai ,  Yu-Hua Chen

IPC: H05K1/11 ,  B44C1/22

CPC classification number: H05K1/0222 ,  H05K3/429 ,  H05K2201/09636 ,  H05K2201/09645 ,  H05K2201/09809

Abstract: A plurality of coaxial leads is made within a single via in a circuit substrate to enhance the density of vertical interconnection so as to match the demand for higher density multi-layers circuit interconnection between top circuit layer and bottom circuit layer of the substrate. Coaxial leads provide electromagnetic interference shielding among the plurality of coaxial leads in a single via.

Abstract translation: 多个同轴引线在电路基板中的单个通孔内形成，以增强垂直互连的密度，以便匹配在衬底的顶层电路层和底层电路层之间的较高密度多层电路互连的需求。 同轴引线在单个通孔中的多个同轴引线之间提供电磁干扰屏蔽。

公开(公告)号：US07737025B2

公开(公告)日：2010-06-15

申请号：US11626606

申请日：2007-01-24

Applicant: Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Renee M Defeo ,  Jui Min Lim

Inventor： Todd B Myers ,  Nicholas R. Watts ,  Eric C Palmer ,  Renee M Defeo ,  Jui Min Lim

IPC: H01L21/00

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K1/115 ,  H05K3/064 ,  H05K3/403 ,  H05K3/4644 ,  H05K2201/09645 ,  H05K2201/09827 ,  H01L2924/00

Abstract: A method for forming an plurality of paths on a substrate includes drilling an opening for a via to a depth to expose a first pad and a second pad, lining the opening with a conductive material, and insulating a first portion of the lining in the opening from a second portion of the lining in the opening to form a first electrical path contacting the first pad and a second electrical path contacting the second pad.

Abstract translation: 一种用于在基板上形成多个路径的方法包括：将用于通孔的开口钻出一定深度，以暴露第一垫和第二垫，用导电材料衬套开口，并将开口的第一部分在开口 从开口中的衬里的第二部分形成接触第一焊盘的第一电路径和接触第二焊盘的第二电路径。

公开(公告)号：US07699672B2

公开(公告)日：2010-04-20

申请号：US11804081

申请日：2007-05-17

Applicant: Victor Zaderej ,  David L. Brunker ,  Phillip J. Dambach

Inventor： Victor Zaderej ,  David L. Brunker ,  Phillip J. Dambach

IPC: H01R9/24

CPC classification number: H01R43/24 ,  H01P1/04 ,  H01P3/02 ,  H01R12/724 ,  H01R13/405 ,  H01R13/6461 ,  H01R13/6474 ,  H05K1/024 ,  H05K3/107 ,  H05K3/308 ,  H05K3/403 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09118 ,  H05K2201/09645 ,  H05K2201/09981 ,  H05K2201/10893 ,  Y10S439/931 ,  Y10T29/4922 ,  Y10T29/49222

Abstract: A pedestal connector that incorporates one or more grouped element channel link transmission lines is seen to have a dielectric body and two opposing contact ends that are intended to contact opposing contacts or traces. The dielectric body has an S-shaped configuration such that the transmission lines supported thereon make at least one change in direction, thereby permitting the use of such connector to interconnect elements lying in two different planes. The transmission lines include slots that extend within the frame and which define opposing, conductive surfaces formed on the dielectric body which are separated by an intervening air gap.

Abstract translation: 包含一个或多个分组的元件通道连杆传输线的基座连接器被看到具有电介质体和旨在接触相对的触点或迹线的两个相对的接触端。 电介质体具有S形构造，使得支撑在其上的传输线至少一个方向改变，从而允许使用这种连接器来互连在两个不同平面中的元件。 传输线包括在框架内延伸并且限定形成在电介质体上的相对的导电表面的槽，它们由中间的气隙隔开。