公开(公告)号：US20070099443A1

公开(公告)日：2007-05-03

申请号：US11614213

申请日：2006-12-21

Applicant: George Pax

Inventor： George Pax

IPC: H05K1/00

CPC classification number: H05K1/117 ,  H05K2201/09145 ,  H05K2201/094 ,  H05K2201/097

Abstract: Memory modules and methods for manufacturing memory modules are disclosed herein. In one embodiment, a memory module includes a substrate, a microelectronic device carried by the substrate, and a plurality of external contact pads operably coupled to the microelectronic device. The substrate includes a first major surface with a first longitudinal edge and a second longitudinal edge. The external contact pads are disposed on the first major surface proximate to the second longitudinal edge. The contact pads include a first contact pad with a first end proximate to the second longitudinal edge and a second contact pad with a second end proximate to the second longitudinal edge. The first end is spaced apart from the first longitudinal edge by a first distance, and the second end is spaced apart from the first longitudinal edge by a second distance different than the first distance.

Abstract translation: 本文公开了用于制造存储器模块的存储器模块和方法。 在一个实施例中，存储器模块包括衬底，由衬底承载的微电子器件以及可操作地耦合到微电子器件的多个外部接触焊盘。 衬底包括具有第一纵向边缘和第二纵向边缘的第一主表面。 外部接触垫设置在靠近第二纵向边缘的第一主表面上。 接触焊盘包括第一接触垫，其具有靠近第二纵向边缘的第一端和第二接触垫，第二接触垫具有靠近第二纵向边缘的第二端。 第一端部与第一纵向边缘间隔开第一距离，并且第二端部与第一纵向边缘间隔开与第一距离不同的第二距离。

公开(公告)号：US20070096302A1

公开(公告)日：2007-05-03

申请号：US11439443

申请日：2006-05-24

Applicant: Josef Schuster

Inventor： Josef Schuster

IPC: H01L23/34

CPC classification number: H05K1/181 ,  G11C5/00 ,  H01L2924/0002 ,  H05K2201/09409 ,  H05K2201/097 ,  Y02P70/611 ,  Y10T29/49133 ,  H01L2924/00

Abstract: A semiconductor memory module includes an electronic printed circuit board with a contact strip and a plurality of semiconductor memory chips of identical type that are mounted on at least one external area of the printed circuit board. The semiconductor memory chips are rectangular in shape and are arranged, in at least two rows with the adjacent chips being oriented perpendicular to one another, such that the area used on the PC board is optimized.

Abstract translation: 半导体存储器模块包括具有接触条的电子印刷电路板和安装在印刷电路板的至少一个外部区域上的相同类型的多个半导体存储器芯片。 半导体存储器芯片的形状为矩形，并且布置成至少两行，其中相邻的芯片彼此垂直定向，使得在PC板上使用的区域被优化。

公开(公告)号：US20060279371A1

公开(公告)日：2006-12-14

申请号：US11300311

申请日：2005-12-15

Applicant: Koki Sato ,  Koichi Kiryu ,  Hideo Miyazawa

Inventor： Koki Sato ,  Koichi Kiryu ,  Hideo Miyazawa

IPC: H01P1/00

CPC classification number: H05K1/0219 ,  H05K1/118 ,  H05K2201/09236 ,  H05K2201/097

Abstract: A flexible print cable includes signal lines and ground lines. The signal lines and the ground lines are disposed alternately on each of an upper surface and an under surface of a film. The positions of the signal lines on the upper surface correspond to the positions of the ground lines on the under surface. The positions of the signal lines on the under surface correspond to the positions of the ground lines on the upper surface. The ground lines are wider than the signal lines. An edge part of one of the ground lines on the upper surface in a width direction overlaps a part of one of the ground lines on the under surface. Another edge part of the ground line on the upper surface in the width direction overlaps a part of another one of the ground lines on the under surface.

Abstract translation: 灵活的打印电缆包括信号线和接地线。 信号线和接地线交替地设置在膜的上表面和下表面中的每一个上。 上表面上的信号线的位置对应于下表面上的接地线的位置。 下表面上的信号线的位置对应于上表面上的接地线的位置。 接地线比信号线宽。 在宽度方向的上表面上的一条接地线的边缘部分与下表面上的一条接地线的一部分重叠。 在宽度方向的上表面上的地线的另一边缘部分与下表面上另一条接地线的一部分重叠。

公开(公告)号：US20060176135A1

公开(公告)日：2006-08-10

申请号：US11053520

申请日：2005-02-07

Applicant: Frank Winter ,  Harry Harberts ,  Julius Tolan

Inventor： Frank Winter ,  Harry Harberts ,  Julius Tolan

IPC: H01F5/00

CPC classification number: H01F17/0033 ,  H01F41/041 ,  H01F2017/002 ,  H05K1/165 ,  H05K2201/097 ,  Y10T29/4902

Abstract: A highly compact inductor formed on opposite faces of a dielectric substrate. Sets of parallel spaced conductive traces formed on the opposite faces of the substrate are interconnected by metallized vias through the substrate, in such a way as to form a continuous spiral conductive path. The inductor is preferably formed as two closely adjacent segments, each with conductive traces on each face of the substrate and each having metallized vias interconnecting the conductive traces. The segments are electrically connected in series and produce a magnetic field that extends through each segment in opposite directions and is closely coupled from one segment to the other. The inductor is, therefore, electromagnetically similar to a wire-wound toroidal inductor, providing high inductance and contourable Q values, but is highly compact, especially in the z-axis direction normal to the substrate.

Abstract translation: 形成在电介质基板的相对面上的高度紧凑的电感器。 在衬底的相对表面上形成的平行间隔的导电迹线的集合通过穿过衬底的金属化通孔互连，以形成连续的螺旋形导电路径。 电感器优选地形成为两个紧密相邻的段，每个具有在衬底的每个面上的导电迹线，并且每个具有互连导电迹线的金属化通孔。 这些段串联电连接并且产生一个磁场，该磁场沿相反方向延伸穿过每个段，并且从一个段紧密耦合到另一个段。 因此，电感器电磁地类似于绕线环形电感器，提供高电感和可轮廓的Q值，但是非常紧凑，特别是在垂直于衬底的z轴方向上。

公开(公告)号：US07081803B2

公开(公告)日：2006-07-25

申请号：US10767373

申请日：2004-01-30

Applicant: Minoru Takaya ,  Toshikazu Endo

Inventor： Minoru Takaya ,  Toshikazu Endo

IPC: H01F5/00

CPC classification number: H01F41/041 ,  H01F17/0033 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/19105 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/097 ,  H01L2924/00014

Abstract: A laminated electronic component including at least one inductance element and produced from a laminate having electrical insulators and electrical conductors laminated alternately. The inductance element is formed as a helical coil having a plurality of turns each constituted by four sides. The inductance element has pairs of parallel conductor pieces and pairs of bridging conductor pieces. Each pair of parallel conductor pieces form two of the four sides of one turn of the coil. Each pair of bridging conductor pieces form the other two sides of one turn of the coil. Grooves are formed in the laminate to thereby form the parallel conductor pieces. The grooves are filled with an electrically insulating material. The bridging conductor pieces are formed on the electrically insulating material.

Abstract translation: 一种层叠电子部件，包括至少一个电感元件，并且由具有电绝缘体和电导体的交替层压体制成。 电感元件形成为具有多个由四边构成的匝数的螺旋线圈。 电感元件具有成对的平行导体片和成对的桥接导体片。 每对平行的导体片形成线圈一圈的四个侧面中的两个。 每对桥接导体片形成线圈一圈的另外两侧。 在层叠体中形成槽，从而形成平行的导体片。 槽中填充有电绝缘材料。 桥接导体片形成在电绝缘材料上。

公开(公告)号：US07005735B2

公开(公告)日：2006-02-28

申请号：US10775070

申请日：2004-02-11

Applicant: Chang-Yong Park ,  Byung-Man Kim ,  Jong-Soo Choi ,  Kwang-Ho Chun ,  Se-Hyung Ryu

Inventor： Chang-Yong Park ,  Byung-Man Kim ,  Jong-Soo Choi ,  Kwang-Ho Chun ,  Se-Hyung Ryu

IPC: H01L23/02

CPC classification number: H05K1/181 ,  H01L23/49838 ,  H01L2924/0002 ,  H05K3/3415 ,  H05K2201/097 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00

Abstract: The array printed circuit board includes at least one circuit board having a first surface. A first layout of first and second chip mounting regions is formed on a first half of the first surface and a second layout of first, and second chip mounting regions is formed on a second half of the first surface. The first and second layouts have opposite first and second chip mounting region patterns.

Abstract translation: 阵列印刷电路板包括具有第一表面的至少一个电路板。 第一和第二芯片安装区域的第一布局形成在第一表面的第一半部分上，第一和第二芯片安装区域的第二布局形成在第一表面的第二半部分上。 第一和第二布局具有相反的第一和第二芯片安装区域图案。

公开(公告)号：US20050241854A1

公开(公告)日：2005-11-03

申请号：US10530656

申请日：2003-09-25

Applicant: Ulrik Mehr ,  Jesper Johansen

Inventor： Ulrik Mehr ,  Jesper Johansen

IPC: A61N1/04 ,  A61N1/16 ,  H05K1/00 ,  H05K1/02 ,  H05K1/11 ,  H01R12/04

CPC classification number: A61N1/16 ,  A61N1/04 ,  H05K1/0228 ,  H05K1/0245 ,  H05K1/0393 ,  H05K2201/097

Abstract: Layered structure for a head worn device, wherein electric signals are fed along metallic leads, which are adhered to a layer on or within the layered structure and where a first and a second lead for connecting a first and a second terminal of a component are provided and whereby the two leads are passed side by side and alternating on the two sides of this layer, and in such a manner that the first and second lead will cross one another at an angle but passing on each their side of the print layer.

Abstract translation: 用于头部磨损装置的分层结构，其中电信号沿着金属引线馈送，所述金属引线粘附到层状结构上或其内的层，并且其中提供用于连接部件的第一和第二端子的第一和第二引线 并且由此两个引线在该层的两侧并排并且交替，并且以这样的方式使得第一引线和第二引线将以一定角度彼此交叉，而是穿过其印刷层的每一侧。

公开(公告)号：US20050104206A1

公开(公告)日：2005-05-19

申请号：US10988390

申请日：2004-11-12

Applicant: Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

Inventor： Jeong-Hyeon Cho ,  Byung-Se So ,  Jin-Kyu Chang

IPC: H01L25/10 ,  G11C5/00 ,  H01L21/50 ,  H01L23/48 ,  H01L25/18 ,  H05K1/18

CPC classification number: H05K1/181 ,  H01L2924/0002 ,  H05K2201/097 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00

Abstract: Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.

Abstract translation: 本发明的实施例可以包括用于高密度安装的集成电路模块结构。 一个实施例可以包括布线​​板，具有在其至少一个表面上具有沿第一方向确定的安装长度的安装长度和在第二方向上确定的安装宽度的安装空间以及具有封装安装组合的多个集成电路封装 长度比布线板的安装长度长。 实施例还可以在直接安装在安装空间上的多个集成电路封装中具有一些封装，而其他封装间接安装在安装空间上。 本实施例可以具有水平和垂直地彼此重叠的封装。 即使在集成电路芯片或封装尺寸增加时，实施例允许多个芯片或封装被安装在有限的区域中而不改变集成电路模块的外形尺寸。

公开(公告)号：US20050093672A1

公开(公告)日：2005-05-05

申请号：US10994902

申请日：2004-11-22

Applicant: Philip Harding

Inventor： Philip Harding

IPC: H01F41/00 ,  H01F17/00 ,  H01F17/04 ,  H01F30/00 ,  H01F37/00 ,  H01F41/04 ,  H05K1/16 ,  H05K3/06 ,  H05K3/42 ,  H05K3/46 ,  H01F27/28

CPC classification number: H01F41/046 ,  H01F17/0033 ,  H05K1/165 ,  H05K3/06 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/086 ,  H05K2201/09063 ,  H05K2201/097 ,  H05K2201/10416 ,  Y10S29/016 ,  Y10T29/4902 ,  Y10T29/49073 ,  Y10T29/49075 ,  Y10T29/49165

Abstract: The present invention relates to the methods of construction for inductive components of, preferably, ferromagnetic materials such as inductors, chokes, and transformers when used as an integral part of the fabrication of PCB's or FLEX's. In one preferred embodiment, holes are formed through a ferromagnetic substrate and plated with conductive material. The arrangement of these holes, and the subsequent design that ensues, will form the inductive components within the plane of the media in which the device is formed; using the substrate for a magnetic core. By using this approach, the inductive components can be miniaturized to physical sizes compatible with the requirements of modem surface mount technology (SMT) for integrated circuitry (IC). This process also allows these components to be fabricated using mass production techniques, thereby avoiding the need to handle discrete devices during the manufacturing process. In another preferred embodiment, a series of thin, concentric high permeability rings are etched on a substrate to provide high permeability transformers and inductors having minimal eddy current effects.

Abstract translation: 本发明涉及当用作PCB或FLEX的制造的组成部分时，优选地，铁磁材料如电感器，扼流器和变压器的电感元件的构造方法。 在一个优选实施例中，孔通过铁磁基底形成并且镀有导电材料。 这些孔的布置以及随之而来的设计将在其中形成装置的介质的平面内形成感应部件; 使用用于磁芯的基板。 通过使用这种方法，电感元件可以小型化成符合集成电路（IC）调制解调器表面贴装技术（SMT）要求的物理尺寸。 该过程还允许使用大量生产技术来制造这些部件，从而避免了在制造过程中处理分立器件的需要。 在另一个优选实施例中，在衬底上蚀刻一系列薄的，同心的高磁导率环，以提供具有最小涡流效应的高磁导率变压器和电感器。

公开(公告)号：US06861899B2

公开(公告)日：2005-03-01

申请号：US10657178

申请日：2003-09-09

Applicant: Takanori Konishi

Inventor： Takanori Konishi

IPC: H03H7/01 ,  H03H7/06 ,  H03H7/075 ,  H05K1/02 ,  H01L25/00

CPC classification number: H05K1/0234 ,  H05K1/0231 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/097 ,  H05K2201/10022 ,  H05K2201/10166

Abstract: The respective ends of input wiring on a printed wiring board of a signal transmission circuit are connected to an input terminal section and a transistor. One terminal of a first capacitor and a first resistor are respectively connected to the input wiring. A leading-side transmission path from a connection point with the first capacitor to a connection point with the input terminal section is formed by only a conductive pattern. An intermediate transmission path from the connection point with the first capacitor to a connection point with the first resistor includes two or more through holes or via holes. The intermediate transmission path is placed near grounding wiring on the printed wiring board. When one terminal of a second capacitor is connected to the intermediate transmission path, a transmission path between the respective connection points with the two capacitors includes one or more through holes or via holes.

Abstract translation: 信号传输电路的印刷电路板上的输入布线的各个端部连接到输入端子部分和晶体管。 第一电容器和第一电阻器的一个端子分别连接到输入布线。 从第一电容器的连接点到与输入端子部分的连接点的引导侧传输路径仅由导电图案形成。 从与第一电容器的连接点到与第一电阻器的连接点的中间传输路径包括两个或更多个通孔或通孔。 中间传输路径放置在印刷线路板上的接地布线附近。 当第二电容器的一个端子连接到中间传输路径时，具有两个电容器的各个连接点之间的传输路径包括一个或多个通孔或通孔。