公开(公告)号：US08419924B2

公开(公告)日：2013-04-16

申请号：US12827343

申请日：2010-06-30

Applicant: Toru Nakai ,  Liyi Chen

Inventor： Toru Nakai ,  Liyi Chen

IPC: C25F3/14 ,  C25D11/02

CPC classification number: C25D1/04 ,  C25D5/022 ,  C25D11/02 ,  C25D11/026 ,  H05K1/0306 ,  H05K3/06 ,  H05K3/244 ,  H05K3/3484 ,  H05K3/4038 ,  H05K3/4605 ,  H05K2201/0116 ,  H05K2201/0209 ,  H05K2203/0315 ,  H05K2203/043 ,  H05K2203/1142 ,  H05K2203/1147

Abstract: [Subject Matter] To provide a method for manufacturing a wiring substrate where rigidity is enhanced in an insulative portion made by oxidizing aluminum.[Solution(s)] Aluminum oxide insulative portion 24 is formed on aluminum plate 20 as shown in FIG. 1(A) through anodic oxidation (FIG. 1(C)). Then, holes (nano-holes) (24h) in aluminum oxide 24 are filled with resin 30 (FIG. 1(E)). Accordingly, the rigidity (strength) of insulative portion 24 will be enhanced and cracking will not occur during heat cycles. Also, the insulation reliability of aluminum oxide will increase, and short circuiting may be prevented at through holes 26 (aluminum portions) separated by aluminum oxide 24.

Abstract translation: [主题]提供一种制造在通过氧化铝制成的绝缘部分中提高刚性的布线基板的方法。 [解决方案]如图1所示，在铝板20上形成氧化铝绝缘部24。 1（A）通过阳极氧化（图1（C））。 然后，在树脂30中填充氧化铝24中的孔（纳米孔）（24小时）（图1（E））。 因此，绝缘部24的刚性（强度）提高，并且在热循环期间不会发生开裂。 此外，氧化铝的绝缘可靠性将增加，并且可以防止由氧化铝24分离的通孔26（铝部分）的短路。

公开(公告)号：US20130081861A1

公开(公告)日：2013-04-04

申请号：US13627813

申请日：2012-09-26

Applicant: KYOCERA SLC Technologies Corporation

Inventor： Masaaki HARAZONO ,  Yoshihiro HOSOI

IPC: H05K1/03 ,  H05K3/10

CPC classification number: H05K1/0306 ,  H01L2224/16225 ,  H05K1/0366 ,  H05K3/0044 ,  H05K3/107 ,  H05K3/427 ,  H05K3/4644 ,  H05K2201/0209 ,  H05K2201/0959 ,  H05K2201/10674 ,  H05K2203/025 ,  Y10T29/49126 ,  Y10T428/2481 ,  Y10T428/24917

Abstract: A printed circuit board of the present invention includes a base body, a through-hole that penetrates through the base body in the thickness direction, and a through-hole conductor that covers an inner wall of the through-hole. The base body has a fiber layer including a plurality of glass fibers and a resin that covers the plurality of glass fibers. The glass fibers have a groove-shaped concavity on a surface exposed to the inner wall of the through-hole. The concavity is filled with a part of the through-hole conductor.

Abstract translation: 本发明的印刷电路板包括基体，在厚度方向穿过基体的通孔和覆盖通孔的内壁的通孔导体。 基体具有包含多个玻璃纤维的纤维层和覆盖多个玻璃纤维的树脂。 玻璃纤维在暴露于通孔的内壁的表面上具有凹槽形凹部。 凹部填充有通孔导体的一部分。

公开(公告)号：US08409704B2

公开(公告)日：2013-04-02

申请号：US12523775

申请日：2007-01-25

Applicant: Yasuo Fukuhara ,  Tomoaki Watanabe ,  Mao Yamaguchi ,  Yuki Kitai ,  Hiroaki Fujiwara

Inventor： Yasuo Fukuhara ,  Tomoaki Watanabe ,  Mao Yamaguchi ,  Yuki Kitai ,  Hiroaki Fujiwara

IPC: B32B7/12

CPC classification number: H05K3/4661 ,  B32B3/266 ,  B32B3/30 ,  B32B5/24 ,  B32B2255/205 ,  B32B2260/021 ,  B32B2260/028 ,  B32B2260/046 ,  B32B2262/101 ,  B32B2307/306 ,  B32B2307/3065 ,  B32B2457/08 ,  C08J5/24 ,  C08J2363/00 ,  H05K1/0373 ,  H05K2201/0209 ,  Y10T428/24917 ,  Y10T428/25 ,  Y10T428/256 ,  Y10T428/2804 ,  Y10T428/2852 ,  Y10T428/287 ,  Y10T428/31515 ,  Y10T428/31522

Abstract: The invention relates to a prepreg, obtained by impregnating a base material with an epoxy resin composition containing an epoxy resin (A), a curing agent (B), an accelerator (C), a phenoxy resin (D), and an inorganic filler (E) and semi-hardening the impregnated material, wherein the inorganic filler (E) has an average particle diameter of 3 μm or less. When a circuit with a narrow wire distance is formed on a surface of a insulator substrate composed of such a prepreg by using a method of forming the circuit by plating process, an amount of the plating remaining on the insulator substrate surface at the circuit contour periphery can be reduced. As a result, it leads to stabilization of inter-circuit insulation resistance and increase in a yield during production of printed wiring boards.

Abstract translation: 本发明涉及一种通过用环氧树脂（A），固化剂（B），促进剂（C），苯氧基树脂（D）和无机填料（A））的环氧树脂组合物浸渍基材而获得的预浸料 （E）和半硬化浸渍材料，其中无机填料（E）的平均粒径为3μm以下。 当通过使用通过电镀处理形成电路的方法在由这种预浸料组成的绝缘体基板的表面上形成具有窄线距离的电路时，在电路轮廓周边的绝缘体基板表面上残留的电镀量 可以减少 结果，导致印刷电路板的制造期间的电路间绝缘电阻的稳定性和产率的提高。

公开(公告)号：US08395056B2

公开(公告)日：2013-03-12

申请号：US12811800

申请日：2009-01-16

Applicant: Tadashi Nakamura ,  Fumio Echigo ,  Masaaki Katsumata

Inventor： Tadashi Nakamura ,  Fumio Echigo ,  Masaaki Katsumata

IPC: H05K9/00

CPC classification number: H05K3/4626 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K3/4069 ,  H05K3/462 ,  H05K2201/0129 ,  H05K2201/0133 ,  H05K2201/0209 ,  H05K2201/10121 ,  H05K2201/10378 ,  H05K2203/061 ,  Y10T29/49126 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A multilayer printed wiring board (11) is composed of a plurality of printed wiring boards (21a and 21b) each having wiring on its both sides, and a relaxing connection layer (15) for interconnecting the printed wiring boards (21a and 21b). The relaxing connection layer (15) contains an inorganic filler, a thermosetting resin, and a reliever for relieving internal stress. The multilayer printed wiring board (11) is prevented from warpage by making the relaxing connection layer (15) disposed inside it absorb internal stress caused by heating and cooling in a solder reflow process or other processes.

Abstract translation: 多层印刷电路板（11）由在其两侧具有布线的多个印刷电路板（21a和21b）和用于互连印刷电路板（21a和21b）的松弛连接层（15）组成。 松弛连接层（15）包含无机填料，热固性树脂和用于缓解内应力的缓冲器。 通过使位于其内部的松弛连接层（15）通过在回流焊或其它工序中的加热和冷却引起的内部应力来防止多层印刷线路板（11）发生翘曲。

公开(公告)号：US08371723B2

公开(公告)日：2013-02-12

申请号：US13303563

申请日：2011-11-23

Applicant: Jeffrey Nall ,  Matthew Mrakovich

Inventor： Jeffrey Nall ,  Matthew Mrakovich

IPC: F21V3/00 ,  F21V5/00

CPC classification number: H05K1/0203 ,  F21K9/90 ,  F21S4/10 ,  F21S4/20 ,  F21V3/02 ,  F21V3/0481 ,  F21V3/10 ,  F21V3/12 ,  F21V9/16 ,  F21V9/30 ,  F21V23/001 ,  F21V23/005 ,  F21V23/007 ,  F21V23/023 ,  F21V29/004 ,  F21V29/70 ,  F21V29/85 ,  F21V31/04 ,  F21Y2101/00 ,  F21Y2115/10 ,  G09F9/33 ,  H05K1/0209 ,  H05K1/181 ,  H05K3/284 ,  H05K3/32 ,  H05K2201/0129 ,  H05K2201/0209 ,  H05K2201/10106 ,  H05K2203/1316 ,  Y10T29/4913 ,  Y10T29/49146

Abstract: One or more light emitting diode diodes (LEDs) are attached to a printed circuit board. The attached LEDs are connectable with a power source via circuitry of the printed circuit board. An overmolding material is insert molded an over at least portions of the printed circuit board proximate to the LEDs to form a free standing high thermal conductivity material overmolding that covers at least portions of the printed circuit board proximate to the LEDs. The free standing high thermal conductivity material has a melting temperature greater than about 100° C. and has a thermal conductivity greater than or about 1 W/m·K. In some embodiments, the free standing high thermal conductivity material is a thermoplastic material.

Abstract translation: 一个或多个发光二极管二极管（LED）连接到印刷电路板。 所连接的LED可通过印刷电路板的电路与电源连接。 包覆成型材料在印刷电路板的靠近LED的至少部分上嵌入模制，以形成覆盖印刷电路板的靠近LED的至少部分的独立高导热材料。 独立的高导热性材料的熔化温度大于约100℃，并具有大于或约1W / m·K的导热系数。 在一些实施例中，自由高的导热材料是热塑性材料。

公开(公告)号：US20120318565A1

公开(公告)日：2012-12-20

申请号：US13595149

申请日：2012-08-27

Applicant: Houssam Jomaa ,  Omar J. Bchir

Inventor： Houssam Jomaa ,  Omar J. Bchir

IPC: H05K1/03

CPC classification number: H05K3/28 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5387 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1433 ,  H01L2924/15311 ,  H05K1/189 ,  H05K3/0035 ,  H05K3/3452 ,  H05K2201/0162 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/099 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49153 ,  Y10T29/49165 ,  Y10T29/49169 ,  H01L2224/05599

Abstract: A microelectronic device mounting substrate includes a bond pad with a side wall and an upper surface. A dielectric first layer is disposed on the mounting substrate and a solder mask second layer is disposed on the dielectric first layer. A uniform recess is disposed through the solder mask second layer and the dielectric first layer that exposes the portion of the bond pad upper surface.

Abstract translation: 微电子器件安装基板包括具有侧壁和上表面的接合焊盘。 电介质第一层设置在安装基板上，并且焊料掩模第二层设置在电介质第一层上。 通过焊接掩模第二层和暴露接合焊盘上表面的部分的电介质第一层设置均匀的凹部。

公开(公告)号：US20120312589A1

公开(公告)日：2012-12-13

申请号：US13154821

申请日：2011-06-07

Applicant: Gregory E. Balcome ,  Brett P. Krull ,  Joseph Kuczynski ,  Terry G. Ryks ,  Timothy J. Tofil

Inventor： Gregory E. Balcome ,  Brett P. Krull ,  Joseph Kuczynski ,  Terry G. Ryks ,  Timothy J. Tofil

IPC: H05K1/00 ,  B32B38/04 ,  H05K3/46 ,  G06F17/50

CPC classification number: H05K3/429 ,  G06F17/5077 ,  H05K1/0251 ,  H05K3/4626 ,  H05K2201/0209 ,  H05K2203/107 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T156/1057

Abstract: An enhanced mechanism for via stub elimination in printed wiring boards (PWBs) and other substrates employs laser resin activation to provide selective via plating. In one embodiment, the resin used in insulator layers of the PWB contains spinel-based non-conductive metal oxide. Preferably, only insulator layers through which vias will pass contain the metal oxide. Those layers are registered and laser irradiated at via formation locations to break down the metal oxide and release metal nuclei. Once these layers are irradiated, all layers of the PWB or subcomposite are laid up and laminated. The resulting composite or subcomposite is subsequently drilled through and subjected to conventional PWB fabrication processes prior to electroless copper plating and subsequent copper electroplating. Because metal nuclei were released only in the via formation locations of the appropriate layers, plating occurs in the via barrels only along those layers and partially plated vias are created without stubs.

Abstract translation: 印刷电路板（PWB）和其他基板中通过短截线消除的增强机制采用激光树脂激活来提供选择性通孔电镀。 在一个实施方案中，PWB的绝缘体层中使用的树脂含有尖晶石型非导电金属氧化物。 优选地，仅通孔所通过的绝缘体层将含有金属氧化物。 登记这些层并在通孔形成位置激光照射以分解金属氧化物并释放金属核。 一旦这些层被照射，PWB或亚复合材料的所有层被铺设和层压。 随后在化学镀铜和随后的铜电镀之前，将所得到的复合材料或副复合材料钻穿并经过常规PWB制造工艺。 因为金属核仅在适当层的通孔形成位置中释放，所以仅沿着这些层在通孔桶中进行电镀，并且在没有短截线的情况下产生部分镀覆的通孔。

公开(公告)号：US08329248B2

公开(公告)日：2012-12-11

申请号：US12557690

申请日：2009-09-11

Applicant: Merrill M. Jackson ,  David Humphrey

Inventor： Merrill M. Jackson ,  David Humphrey

IPC: B05D5/12 ,  B05D7/00

CPC classification number: C23C28/00 ,  C25D5/48 ,  C25D7/00 ,  H01L23/49586 ,  H01L2924/0002 ,  H05K3/244 ,  H05K3/28 ,  H05K3/285 ,  H05K2201/0209 ,  H05K2201/0769 ,  H05K2203/0292 ,  H05K2203/1355 ,  Y10T428/12438 ,  Y10T428/12535 ,  Y10T428/12556 ,  Y10T428/12569 ,  Y10T428/12576 ,  Y10T428/12611 ,  Y10T428/12625 ,  Y10T428/12715 ,  Y10T428/12722 ,  Y10T428/31678 ,  H01L2924/00

Abstract: An electrical component includes a conductive substrate, a tin layer formed on the substrate, and a barrier coating formed on the tin layer to impede tin whisker growth. The barrier coating includes a polymer matrix, and abrasive particles that are dispersed about the matrix.

Abstract translation: 电气部件包括导电基板，形成在基板上的锡层和形成在锡层上以阻止锡晶须生长的阻挡涂层。 阻隔涂层包括聚合物基质和分散在基质周围的磨料颗粒。

公开(公告)号：US08319111B2

公开(公告)日：2012-11-27

申请号：US11865919

申请日：2007-10-02

Applicant: Hajime Saiki ,  Mikiya Sakurai ,  Atsuhiko Sugimoto

Inventor： Hajime Saiki ,  Mikiya Sakurai ,  Atsuhiko Sugimoto

IPC: H05K1/03

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/0373 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/068 ,  H05K2201/09481 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A wiring board having a favorable electrical reliability and in which a crack is unlikely to occur at a connection interface of via conductors even though the number of via conductors in series, which constitutes the stacked via, becomes larger than that of a conventional wiring board.

Abstract translation: 即使构成堆叠通孔的串联的通孔导体的数量变得比常规的布线板大，因此具有良好的电气可靠性并且在通孔导体的连接界面处不可能发生裂纹的布线板。

公开(公告)号：US20120292092A1

公开(公告)日：2012-11-22

申请号：US13343347

申请日：2012-01-04

Applicant: Sang-min LEE ,  Soon-chul KWON

Inventor： Sang-min LEE ,  Soon-chul KWON

IPC: H05K1/11 ,  C03C15/00 ,  H05K3/00

CPC classification number: C03C15/00 ,  H05K3/4655 ,  H05K2201/0209 ,  Y10T156/1056

Abstract: A method of manufacturing a circuit board includes: providing a base substrate that comprises a first electrically conductive layer that has an inner circuit pattern formed on at least one surface of the base substrate; attaching a build-up material to the base substrate to insulate the first electrically conductive layer from outside; forming one or more holes at one time in the build-up material attached to the base substrate; forming a stack by curing the build-up material in which the one or more holes are formed; and forming a second electrically conductive layer that has an outer circuit pattern formed on at least one outer surface of the stack. The method may form the holes without drilling.

Abstract translation: 一种电路板的制造方法，其特征在于，具备：基底基板，其具有形成在所述基底基板的至少一个面上的内部电路图案的第一导电层; 将积层材料附接到基底基板以使第一导电层与外部绝缘; 在附着于基底基板的积层材料中一次形成一个或多个孔; 通过固化形成一个或多个孔的积聚材料形成堆叠; 以及形成具有形成在所述堆叠的至少一个外表面上的外部电路图案的第二导电层。 该方法可以在没有钻孔的情况下形成孔。