中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

713 records (took 0.015 seconds)

    High temperature circuit board
    121.
    发明授权
    High temperature circuit board 失效
    高温电路板

    公开(公告)号：US4424408A

    公开(公告)日：1984-01-03

    申请号：US299345

    申请日：1981-09-04

    Applicant: Vito D. Elarde

    Inventor： Vito D. Elarde

    IPC: H05K1/09 ,  H05K3/06 ,  H05K3/14 ,  H05K3/24 ,  H05K3/38

    CPC classification number: H05K3/24 ,  H05K1/09 ,  H05K3/14 ,  H05K2201/0338 ,  H05K2203/1344 ,  H05K3/06 ,  H05K3/143 ,  H05K3/388

    Abstract: A high temperature circuit board made by flame spraying a high temperature resistant metal film, such as aluminum, zinc or silver solder braze alloy, onto a high temperature resistant insulative substrate in which in one embodiment a reverse circuit image resist is layed on the board surface and the metal is flame sprayed onto the board surface and the reverse image resist screen is then removed leaving the circuit without etching. In the other embodiment aluminum is flame sprayed onto the substrate and then a silver solder braze alloy or copper or nickel is flame sprayed onto the aluminum film, and then resist and etching stops are applied to remove unwanted metal to the substrate and the resist is stripped providing the high temperature printed circuit board.

    Abstract translation: 通过将耐高温金属膜（例如铝，锌或银焊料钎焊合金）火焰喷涂到耐高温绝缘基板上制成的高温电路板，其中在一个实施例中将反向电路图像抗蚀剂铺设在板表面上 并且金属被火焰喷涂到板表面上，然后去除反向抗蚀剂屏幕，留下电路而没有蚀刻。 在另一实施例中，铝被火焰喷涂到基板上，然后将银焊料钎焊合金或铜或镍火焰喷涂到铝膜上，然后施加抗蚀和蚀刻停止以将不需要的金属去除到基板上，并且抗蚀剂被剥离 提供高温印刷电路板。

    Flatpack lead positioning device
    124.
    发明授权
    Flatpack lead positioning device 失效
    平板导向定位装置

    公开(公告)号：US3778530A

    公开(公告)日：1973-12-11

    申请号：US3778530D

    申请日：1972-07-05

    Applicant: REIMANN W

    Inventor： REIMANN W

    IPC: H05K1/11 ,  H05K3/06 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K7/10

    CPC classification number: H05K3/3421 ,  H05K1/111 ,  H05K3/062 ,  H05K3/064 ,  H05K3/108 ,  H05K3/243 ,  H05K7/1023 ,  H05K2201/0305 ,  H05K2201/0338 ,  H05K2201/09745 ,  H05K2201/10689 ,  H05K2203/0361 ,  H05K2203/0384 ,  H05K2203/048 ,  H05K2203/058 ,  H05K2203/167 ,  Y02P70/611 ,  Y02P70/613

    Abstract: A printed circuit board for mounting integrated circuit and resistor network packages commonly referred to as flatpack components and a process for fabricating the circuit board. The printed circuit board has a conductive pattern of electrical connection pads for connecting to electrical leads from flatpack components and electrical conductors for connecting the pads to circuitry external to the board. A channel for receiving and aligning each electrical lead from a flatpack component is formed by printed circuit techniques. The surface layer of each channel is formed of solder which simplifies the process of electrically connecting flatpack leads and reduces errors occuring in the soldering process.

    Abstract translation: 用于安装通常称为扁平封装部件的集成电路和电阻器网络封装的印刷电路板以及用于制造电路板的工艺。 印刷电路板具有电连接焊盘的导电图案，用于连接到来自扁平封装部件和电导体的电引线，用于将焊盘连接到板外部的电路。 用于通过印刷电路技术形成用于从扁平封装部件接收和对准每个电引线的通道。 每个通道的表面层由焊料形成，这简化了电连接扁平封装引线的过程，并减少了焊接过程中发生的错误。

    WIRING BOARD AND MANUFACTURING METHOD THEREFOR
    128.
    发明公开
    WIRING BOARD AND MANUFACTURING METHOD THEREFOR 审中-公开

    公开(公告)号：US20240357739A1

    公开(公告)日：2024-10-24

    申请号：US18639407

    申请日：2024-04-18

    Applicant: TOPPAN Holdings Inc.

    Inventor： Tomoyuki Ishii

    IPC: H05K1/03 ,  H05K3/00 ,  H05K3/46

    CPC classification number: H05K1/0306 ,  H05K3/0017 ,  H05K3/4644 ,  H05K2201/0266 ,  H05K2201/0338 ,  H05K2201/09154 ,  H05K2203/0548 ,  H05K2203/1105

    Abstract: A wiring board includes: a substrate; a first seed layer provided on the substrate; a first conductive layer provided on the first seed layer; a first insulating layer provided on the first conductive layer; a second seed layer provided on the first insulating layer; and a second conductive layer provided on the second seed layer. An area of the first insulating layer is smaller than an area of the first conductive layer. An area of the second conductive layer is smaller than the area of the first insulating layer. A region of the first insulating layer not overlapping the second conductive layer includes a first region surrounding the second conductive layer and a second region outside the first region. A surface roughness of the second region is larger than a surface roughness of the first region.

    WIRING SUBSTRATE
    129.
    发明公开
    WIRING SUBSTRATE 审中-公开

    公开(公告)号：US20240334598A1

    公开(公告)日：2024-10-03

    申请号：US18614865

    申请日：2024-03-25

    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

    Inventor： Yuki KOBAYASHI ,  Tomoo YAMASAKI

    IPC: H05K1/09 ,  H05K1/03 ,  H05K1/11 ,  H05K3/10

    CPC classification number: H05K1/09 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/108 ,  H05K2201/0209 ,  H05K2201/0338 ,  H05K2203/072 ,  H05K2203/0723

    Abstract: A wiring substrate includes a first wiring layer, an insulation layer covering a side surface of the first wiring layer and exposing part of the first wiring layer, and a second wiring layer formed on the first wiring layer exposed from the insulation layer. The insulation layer includes a resin and a filler. The insulation layer includes an upper surface having a structure in which the filler is exposed from the resin. The second wiring layer includes a first metal film, covering the upper surface of the insulation layer and the wiring layer exposed from the insulation layer, and a metal layer, formed above the first metal film. The first metal film is formed from a CuNiTi alloy and has a Ni content rate of 5 wt % or greater and 30 wt % or less and a Ti content rate of 5 wt % or greater and 15 wt % or less.

Patent Agency Ranking