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    DIGITAL PROTECTIVE RELAY
    122.
    发明申请
    DIGITAL PROTECTIVE RELAY 有权
    数字保护继电器

    公开(公告)号：US20130265675A1

    公开(公告)日：2013-10-10

    申请号：US13850998

    申请日：2013-03-26

    Applicant: LSIS CO., LTD.

    Inventor： Hong Seon AHN

    IPC: H02H7/20

    CPC classification number: H02H7/20 ,  H05K1/0215 ,  H05K1/0218 ,  H05K1/141 ,  H05K2201/044 ,  H05K2201/10295

    Abstract: A digital protective relay includes at least one daughter PCB having an electronic circuit which generates electromagnetic interference noise or high frequency noise; and a backplane printed circuit board having, on an upper surface thereof, a plurality of first connectors for connection with the daughter PCB, connected to the daughter PCB through the first connectors, and providing a noise discharge path along which the electromagnetic interference noise or the high frequency noise from the daughter PCB flows to an external ground.

    Abstract translation: 数字保护继电器包括至少一个子PCB，其具有产生电磁干扰噪声或高频噪声的电子电路; 以及背板印刷电路板，在其上表面上具有多个用于与子PCB连接的第一连接器，通过第一连接器与子PCB连接，并提供噪声放电路径，沿着该噪声放电路径，电磁干扰噪声或 子PCB的高频噪声流向外部地面。

    AMPLIFICATION MODULE FOR AN OPTICAL PRINTED CIRCUIT BOARD AND AN OPTICAL PRINTED CIRCUIT BOARD
    123.
    发明申请
    AMPLIFICATION MODULE FOR AN OPTICAL PRINTED CIRCUIT BOARD AND AN OPTICAL PRINTED CIRCUIT BOARD 有权
    光学印刷电路板和光电印刷电路板的放大模块

    公开(公告)号：US20130235450A1

    公开(公告)日：2013-09-12

    申请号：US13840095

    申请日：2013-03-15

    Applicant: XYRATEX TECHNOLOGY LIMITED

    Inventor： Richard Charles Alexander PITWON

    IPC: H01S3/091

    CPC classification number: H01S3/091 ,  G02B6/12004 ,  G02B6/1221 ,  H01S3/0637 ,  H01S3/0933 ,  H01S3/094049 ,  H01S3/0941 ,  H01S3/1603 ,  H01S3/1605 ,  H01S3/1606 ,  H01S3/168 ,  H01S3/178 ,  H01S3/2308 ,  H01S3/2383 ,  H01S5/4031 ,  H05K1/0274 ,  H05K1/142 ,  H05K2201/044

    Abstract: The invention provides an amplification module for an optical printed circuit board, the optical printed circuit board including plural polymer waveguide sections from independent waveguides, each of the sections being doped with an amplifying dopant, wherein the plural waveguide sections are routed so as to pass through an amplification zone in which the plural polymer waveguide sections are arranged close or adjacent to one another, the amplification module including: a pump source including plural light sources arranged to provide independently controllable levels of pump radiation to each of the plural waveguide sections. In an embodiment, the amplification module also includes plural polymer waveguide sections corresponding to the plural polymer waveguides of the printed circuit board on which in use the amplification module is to be arranged, each of the sections being doped with an amplifying dopant.

    Abstract translation: 本发明提供了一种用于光学印刷电路板的放大模块，该光学印刷电路板包括来自独立波导的多个聚合物波导部分，每个部分掺杂有放大掺杂剂，其中多个波导部分被路由以便通过 多个聚合物波导部分彼此靠近或相邻地布置的放大区，所述放大模块包括：泵源，包括多个光源，所述泵浦源设置成为所述多个波导段中的每一个提供可独立控制的泵浦辐射水平。 在一个实施例中，放大模块还包括对应于印刷电路板的多个聚合物波导的多个聚合物波导部分，在其上使用放大模块来布置每个部分，每个部分掺杂有放大掺杂剂。

    MOTHERBOARD INTERCONNECTION DEVICE AND MOTHERBOARD INTERCONNECTION METHOD
    127.
    发明申请
    MOTHERBOARD INTERCONNECTION DEVICE AND MOTHERBOARD INTERCONNECTION METHOD 审中-公开
    主板互连设备和主板互连方法

    公开(公告)号：US20120243193A1

    公开(公告)日：2012-09-27

    申请号：US13491526

    申请日：2012-06-07

    Applicant: CHIA-NAN PAI ,  SHOU-KUO HSU

    Inventor： CHIA-NAN PAI ,  SHOU-KUO HSU

    IPC: H05K1/18

    CPC classification number: H05K1/0295 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10015 ,  H05K2201/10545 ,  H05K2201/10636 ,  Y02P70/611

    Abstract: A motherboard interconnection method includes positioning a first and a third electronic elements on a top layer of a motherboard interconnection device, and positioning a second and a fourth electronic elements on a bottom layer of the motherboard interconnection device. The method connects a first end of the first electronic element on the top layer to the first end of the second electronic element on the bottom layer with a first via hole, and connects the first end of the third electronic element on the top layer to the first end of the fourth electronic element on the bottom layer with a second via hole. The method further connects a second ends of the two electronic elements on the top layer to a first part, and connects the second ends of the two electronic elements on the bottom layer to a second part.

    Abstract translation: 母板互连方法包括将第一和第三电子元件定位在母板互连装置的顶层上，并将第二和第四电子元件定位在母板互连装置的底层上。 该方法通过第一通孔将顶层上的第一电子元件的第一端与底层上的第二电子元件的第一端连接，并将顶层上的第三电子元件的第一端连接到 第四电子元件的第一端部具有第二通孔。 该方法还将顶层上的两个电子元件的第二端连接到第一部分，并且将底层上的两个电子元件的第二端连接到第二部分。

    BACKPLANES INCLUDING OPTICAL BYPASS SWITCHES, AND RELATED CIRCUIT BOARDS, COMPUTING SYSTEMS, BYPASS SWITCHES, AND METHODS
    128.
    发明申请
    BACKPLANES INCLUDING OPTICAL BYPASS SWITCHES, AND RELATED CIRCUIT BOARDS, COMPUTING SYSTEMS, BYPASS SWITCHES, AND METHODS 审中-公开
    背光源包括光学旁路开关及相关电路板，计算系统，旁路开关及方法

    公开(公告)号：US20120195548A1

    公开(公告)日：2012-08-02

    申请号：US13016501

    申请日：2011-01-28

    Applicant: Robert Brunner ,  Stephane Lessard

    Inventor： Robert Brunner ,  Stephane Lessard

    IPC: G02B6/26

    CPC classification number: G02B6/43 ,  G02B6/3514 ,  G02B6/3562 ,  G02B6/3598 ,  H04B10/803 ,  H05K1/0274 ,  H05K1/14 ,  H05K2201/044

    Abstract: A backplane for a computing system may include a connector configured to provide a detachable mechanical coupling with a circuit board, and an optical signal path configured to carry optical signals. In addition, an optical bypass switch may be configured to couple optical signals from the optical signal path to the circuit board and to couple optical signals from the circuit board to the optical signal path responsive to an enabling signal. The optical bypass switch may be further configured to transmit optical signals therethrough to bypass the circuit board responsive to an absence of the enabling signal. Related circuit boards, computing systems, bypass switches, and methods are also discussed.

    Abstract translation: 用于计算系统的背板可以包括被配置为提供与电路板的可拆卸机械耦合的连接器和被配置为承载光信号的光信号路径。 此外，光学旁路开关可以被配置为将光信号从光信号路径耦合到电路板，并且响应于使能信号将来自电路板的光信号耦合到光信号路径。 光学旁路开关可以被进一步配置成响应于不存在使能信号而透过光信号以绕过电路板。 还讨论了相关电路板，计算系统，旁路开关和方法。

    Midplane especially applicable to an orthogonal architecture electronic system
    129.
    发明授权
    Midplane especially applicable to an orthogonal architecture electronic system 有权
    中平面特别适用于正交架构电子系统

    公开(公告)号：US08226438B2

    公开(公告)日：2012-07-24

    申请号：US12789621

    申请日：2010-05-28

    Applicant: Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

    Inventor： Thomas S. Cohen ,  Marc B. Cartier, Jr. ,  Mark W. Gailus

    IPC: H01R13/648

    CPC classification number: H05K7/1445 ,  H01R13/514 ,  H01R13/6587 ,  H01R13/6591 ,  H05K1/0231 ,  H05K1/0237 ,  H05K1/116 ,  H05K1/14 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09718 ,  H05K2201/10189 ,  H05K2203/1572

    Abstract: A midplane has a first side to which contact ends of a first differential connector are connected and a second side opposite the first side to which contact ends of a second differential connector are connected. The midplane includes a plurality of vias extending from the first side to the second side, with the vias providing first signal launches on the first side and second signal launches on the second side. The first signal launches are provided in a plurality of rows, with each row having first signal launches along a first line and first signal launches along a second line substantially parallel to the first line. The second signal launches are provided in a plurality of columns, with each column having second signal launches along a third line and second signal launches along a fourth line substantially parallel to the third line.

    Abstract translation: 中平面具有连接第一差分连接器的接触端的第一侧和与第二差分连接器的接触端连接的第一侧相对的第二侧。 中平面包括从第一侧延伸到第二侧的多个通孔，其中通孔在第一侧上提供第一信号发射，而第二信号在第二侧上发射。 第一信号发射被设置成多行，每行具有沿着第一线的第一信号发射，并且第一信号沿着基本上平行于第一线的第二线发射。 第二信号发射被提供在多列中，每列具有沿着第三线的第二信号发射，而第二信号沿着基本上平行于第三线的第四线发射。

    Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at a Plurality of Memory Devices
    130.
    发明申请
    Memory Module Having Signal Lines Configured for Sequential Arrival of Signals at a Plurality of Memory Devices 有权
    具有配置信号线的存储器模块，用于在多个存储器件上顺序到达信号

    公开(公告)号：US20120144085A1

    公开(公告)日：2012-06-07

    申请号：US13366191

    申请日：2012-02-03

    Applicant: Haw-Jyh Liaw ,  David Nguyen

    Inventor： Haw-Jyh Liaw ,  David Nguyen

    IPC: G06F13/40

    CPC classification number: G11C5/063 ,  G06F13/1684 ,  G06F13/4086 ,  G06F13/409 ,  G06F13/4247 ,  G11C5/04 ,  G11C7/1048 ,  H05K1/023 ,  H05K1/0246 ,  H05K1/0248 ,  H05K1/14 ,  H05K7/1459 ,  H05K2201/044 ,  H05K2201/09263 ,  H05K2201/10022 ,  H05K2201/10159 ,  H05K2201/10689

    Abstract: A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.

    Abstract translation: 存储器模块包括衬底，多条信号线，时钟线和多个存储器件。 多条信号线包括彼此并行布置的第一和第二信号线，其中，对于第一和第二信号线中的每一条，从相应的第一边缘指状开始的相应信号依次穿过相应的第一段， 信号线，相应信号线的相应转弯部分以及相应信号线的相应第二部分。 时钟线是提供顺序穿过的时钟信号，第二边缘手指，时钟线的第一段，时钟线的转弯部分和时钟线的第二段。 相应的信号遍历并且时钟信号线依次到达多个存储器件。

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