公开(公告)号：US20060094267A1

公开(公告)日：2006-05-04

申请号：US11264637

申请日：2005-11-01

Applicant: Guoli Li

Inventor： Guoli Li

IPC: H05K1/00

CPC classification number: H01R13/6658 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09709 ,  H05K2201/10189

Abstract: The present invention discloses a plug, which matches a corresponding socket. The plug comprises a body, a shell, a plurality of terminals and a plurality of wires. The body has a first contact surface directing to the corresponding socket, a second contact surface corresponding to the first contact surface and a plurality of terminal channels formed between the first contact surface and the second contact surface. Each terminal has a connection end that extends from the second contact surface out of the terminal channel and is accepted by the shell. On one side of the shell, the wires connect to the shell and the connection direction is vertical to the first contact surface. A gold finger board, placed in the shell, has a plurality of leads, each lead having a soldering pad connecting to the corresponding terminal at one end and having a gold finger connecting to the corresponding wire at another end. The plug of present invention provides the advantages of avoiding twisting of the wire and saving space.

Abstract translation: 本发明公开了一种匹配相应插座的插头。 插头包括主体，外壳，多个端子和多根电线。 主体具有引导到对应的插座的第一接触表面，对应于第一接触表面的第二接触表面和形成在第一接触表面和第二接触表面之间的多个端子通道。 每个端子具有从第二接触表面延伸出端子通道并被外壳接受的连接端。 在壳的一侧，电线连接到外壳，连接方向垂直于第一接触面。 放置在壳体中的金指板具有多个引线，每个引线具有在一端连接到相应端子的焊盘，并且在另一端具有连接到相应导线的金手指。 本发明的插头具有避免线的扭曲和节省空间的优点。

公开(公告)号：US20060091558A1

公开(公告)日：2006-05-04

申请号：US11264000

申请日：2005-11-02

Applicant: Yao-Ting Huang ,  Shih-Ching Chang

Inventor： Yao-Ting Huang ,  Shih-Ching Chang

IPC: H01L23/48

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/09336 ,  H05K2201/10689 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuitized substrate with trace embedded inside ground layer mainly comprises a trace layer, a first dielectric layer, a ground layer, a second dielectric layer, and at least one embedded conductive trace. The embedded conductive trace is located between the first dielectric layer and the second dielectric layer. The embedded conductive trace is hidden inside a hollow portion of the ground layer, and is electrically insulated from the ground layer. Therefore, by utilizing the embedded conductive trace, the traces of the trace layer can be decreased and the product yield can be improved.

Abstract translation: 具有迹线嵌入内层的电路化基板主要包括迹线层，第一介电层，接地层，第二介质层和至少一个嵌入的导电迹线。 嵌入的导电迹线位于第一介电层和第二介电层之间。 嵌入的导电迹线被隐藏在接地层的中空部分内，并且与接地层电绝缘。 因此，通过利用嵌入的导电迹线，能够降低痕量的痕迹，提高产品的产率。

公开(公告)号：US07005753B2

公开(公告)日：2006-02-28

申请号：US10921181

申请日：2004-08-19

Applicant: Kevin L. Seaman ,  Vernon M. Wnek

Inventor： Kevin L. Seaman ,  Vernon M. Wnek

IPC: H01L23/48

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A method, system, and apparatus for optimizing routing layers and board space requirements for a ball grid array land pattern is described. The land pattern includes a plurality of conductive pads arranged in an array of rows and columns. The array of pads has at least one edge of a perimeter of the array not fully populated with conductive pads, whereby spaces are created in the at least one edge by the missing conductive pads. The spaces create additional routing channels for signals from conductive pads within the array to be routed externally to the array through the at least one edge.

Abstract translation: 描述了一种用于优化球栅阵列焊盘图案的布线层和板空间要求的方法，系统和装置。 所述焊盘图案包括排列成行和列的阵列的多个导电焊盘。 焊盘阵列具有阵列的周边的至少一个边缘不完全填充有导电焊盘，由此在缺少的导电焊盘的至少一个边缘中产生空间。 这些空间为阵列内的导电焊盘产生信号，从而通过至少一个边沿外部引导到阵列。

公开(公告)号：US20050230823A1

公开(公告)日：2005-10-20

申请号：US11094136

申请日：2005-03-31

Applicant: Tohru Ohsaka

Inventor： Tohru Ohsaka

IPC: H01L23/12 ,  H01L23/32 ,  H01L23/48 ,  H01L23/498 ,  H01L23/66 ,  H05K1/02 ,  H05K1/11 ,  H05K3/24

CPC classification number: H05K1/0243 ,  H01L23/49827 ,  H01L23/66 ,  H01L24/48 ,  H01L24/49 ,  H01L2223/6627 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49112 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/30111 ,  H05K1/023 ,  H05K1/112 ,  H05K3/242 ,  H05K2201/09227 ,  H05K2201/0979 ,  H05K2201/10022 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: For a multi-terminal semiconductor package, such as a BGA or a CSP, that handles high-speed differential signals, a high-speed signal is assigned to the innermost located electrode pad on an interposer substrate, and the electrode pad is connected to the outermost located ball pad on the interposer substrate. With this arrangement, the length of a plating stub can be considerably reduced, and the adverse affect on a signal waveform can be minimized. This arrangement is especially effective for differential signal lines.

Abstract translation: 对于处理高速差分信号的诸如BGA或CSP的多端子半导体封装，将高速信号分配给插入器基板上的最内侧定位的电极焊盘，并且电极焊盘连接到 位于内插器基板上的最外侧的球垫。 通过这种布置，可以显着地减少电镀短截线的长度，并且可以最小化对信号波形的不利影响。 这种布置对于差分信号线特别有效。

公开(公告)号：US20050207131A1

公开(公告)日：2005-09-22

申请号：US10804800

申请日：2004-03-19

Applicant: Victor Prokofiev ,  Cengiz Palanduz

Inventor： Victor Prokofiev ,  Cengiz Palanduz

IPC: H01L23/50 ,  H05K1/11 ,  H05K1/14 ,  H05K7/06 ,  H05K7/10

CPC classification number: H05K7/1092 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15312 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/141 ,  H05K1/147 ,  H05K2201/09227 ,  H05K2201/094 ,  H05K2201/10325 ,  H05K2201/10689 ,  H05K2201/10734 ,  H01L2924/00

Abstract: An integrated circuit (IC) package includes a chip carrier and a chip mounted to the chip carrier. The chip carrier has a centrally located power delivery region and a peripherally located input-output (I/O) delivery region disposed in partially surrounding relationship to the power delivery region. Power and ground paths are disposed in the power delivery region and I/O signal paths are disposed in the I/O delivery region.

Abstract translation: 集成电路（IC）封装包括芯片载体和安装到芯片载体的芯片。 芯片载体具有位于中心的电力输送区域和以与电力输送区域部分环绕的关系布置的外围定位的输入输出（I / O）输送区域。 电源和接地路径设置在电力输送区域中，I / O信号路径设置在I / O传送区域中。

公开(公告)号：US20050087868A1

公开(公告)日：2005-04-28

申请号：US10991622

申请日：2004-11-17

Applicant: William Cornelius ,  Paul Baker

Inventor： William Cornelius ,  Paul Baker

IPC: H01L23/498 ,  H05K1/02 ,  H05K1/11 ,  H01L29/40

CPC classification number: H01L23/50 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2223/6616 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15173 ,  H05K1/0231 ,  H05K1/114 ,  H05K2201/09227 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  Y10T29/49222 ,  H01L2924/00 ,  H01L2224/0401

Abstract: The present invention provides an apparatus and methods for the functionality of an integrated circuit. An exemplary embodiment according to an aspect of the present invention includes a ball grid array having open spaces therein. Within the open spaces, pairs of opposite polarity vias are clustered to minimize current path inductance by exploiting mutual inductance between vias of opposite current flow. In an illustrative embodiment, capacitors are coupled to the vias to further reduce current path inductance.

Abstract translation: 本发明提供了用于集成电路的功能的装置和方法。 根据本发明的一个方面的示例性实施例包括其中具有开放空间的球栅阵列。 在开放空间内，成对的相反极性通孔被聚集，以通过利用相反电流的通孔之间的互感来最小化电流路径电感。 在说明性实施例中，电容器耦合到通孔以进一步减小电流路径电感。

公开(公告)号：US06855626B2

公开(公告)日：2005-02-15

申请号：US10637552

申请日：2003-08-11

Applicant: Yukio Sato ,  Akihiro Oku ,  Masayoshi Aoki

Inventor： Yukio Sato ,  Akihiro Oku ,  Masayoshi Aoki

IPC: H01L21/66 ,  H01L23/544 ,  H05K1/02 ,  H05K3/00 ,  H05K3/24 ,  H01L21/4763

CPC classification number: H01L23/544 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/97 ,  H01L2223/54473 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/12042 ,  H01L2924/15173 ,  H01L2924/15183 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0266 ,  H05K3/0052 ,  H05K3/242 ,  H05K2201/09227 ,  H05K2201/09936 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2924/01004

Abstract: A method for producing a wiring board for a semiconductor package having a base substrate with first and second surfaces; a wiring layer including wiring patterns formed on at least one of the first and second surfaces; a plurality of semiconductor element mounting areas formed on the surface of the base substrate on which the wiring layer is formed; and individual patterns as position information formed for the respective semiconductor element mounting areas, the individual patterns having a different shape for each of the respective semiconductor element mounting areas. The individual patterns as position information are formed on peripheral regions of the respective semiconductor element mounting areas.

Abstract translation: 一种半导体封装用配线基板的制造方法，具有：具有第一表面和第二表面的基底基板; 布线层，其包括形成在所述第一表面和所述第二表面中的至少一个上的布线图案; 多个半导体元件安装区域，形成在其上形成有布线层的基底基板的表面上; 以及作为为各个半导体元件安装区域形成的位置信息的各个图案，各个图案对于各个半导体元件安装区域具有不同的形状。 作为位置信息的各个图案形成在各个半导体元件安装区域的周边区域上。

公开(公告)号：US20040164431A1

公开(公告)日：2004-08-26

申请号：US10651164

申请日：2003-08-29

Applicant: Broadcom Corporation

Inventor： Kevin L. Seaman ,  Vernon M. Wnek

IPC: H01L023/48 ,  H01L029/40 ,  H01L021/44

CPC classification number: H05K1/181 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/112 ,  H05K3/0005 ,  H05K2201/09227 ,  H05K2201/10734 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

Abstract: A method and apparatus for improved contact pad arrays and land patterns for integrated circuit packages are presented. A plurality of conductive pads are arranged in an array of rows and columns. At least one edge of a perimeter of the array is not fully populated with conductive pads. Spaces created in the edge by missing conductive pads create additional routing channels for signals from conductive pads within the array to be routed external to the array through the edge. A land pattern may have routing channels on one or more layers of a printed circuit board. In such a multi-layer land pattern, spaces can be created in edges on any number of the layers. Furthermore, corner pad arrangements having known routing channel characteristics can be used in any number of corners of a land pattern that incorporates spaces in an edge.

Abstract translation: 提出了一种用于集成电路封装的改进的接触焊盘阵列和焊盘图案的方法和装置。 多个导电焊盘被布置成行和列的阵列。 阵列的周边的至少一个边缘没有完全填充有导电焊盘。 通过缺少导电焊盘在边缘创建的空间为阵列内的导电焊盘产生的信号产生额外的布线通道，以通过边缘被布线到阵列外部。 焊盘图案可以在印刷电路板的一层或多层上具有布线通道。 在这样的多层纹理图案中，可以在任何数量的层上的边缘上创建空间。 此外，具有已知的路线通道特性的拐角垫布置可以用于在边缘中包含空间的陆地图案的任何数量的拐角中。

公开(公告)号：US20040099440A1

公开(公告)日：2004-05-27

申请号：US10716599

申请日：2003-11-20

Inventor： Herman Kwong ,  Luigi Difilippo ,  Guy Duxbury ,  Larry Marcanti

IPC: H05K007/06

CPC classification number: H05K1/112 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09263 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09627 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: A technique for accommodating electronic components on a multilayer signal routing device is disclosed. In one particular exemplary embodiment, the technique may be realized as a method for accommodating electronic components on a multilayer signal routing device. Such a method comprises determining a component space that is required to accommodate a plurality of electronic components on a surface of a multilayer signal routing device, and then forming at least one signal routing channel on at least the surface of the multilayer signal routing device, wherein the at least one signal routing channel has a channel space that is equal to or greater than the component space.

Abstract translation: 公开了一种用于在多层信号路由设备上容纳电子部件的技术。 在一个特定的示例性实施例中，该技术可以被实现为用于在多层信号路由设备上容纳电子部件的方法。 这种方法包括确定在多层信号路由设备的表面上容纳多个电子部件所需的组件空间，然后在多层信号路由设备的至少表面上形成至少一个信号路由选择信道，其中， 所述至少一个信号路由信道具有等于或大于所述分量空间的信道空间。

公开(公告)号：US20040047637A1

公开(公告)日：2004-03-11

申请号：US10237823

申请日：2002-09-06

Applicant: PARACER, INC.

Inventor： William Wang ,  Hengju Cheng ,  WeiZen Lo

IPC: H04B010/00

CPC classification number: G02B6/4292 ,  H05K1/114 ,  H05K1/148 ,  H05K1/181 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A transponder assembly for use with fiber optic digital communication cables having multiple parallel optic fiber elements. The transponder assembly features a transmitter port and receiver port for connection with separate parallel optic cables for separately transmitting and receiving data and an electrical connector for connecting with computer or communication systems. The transponder assembly includes a parallel optic transmitter module and a parallel optic receiver module having pluggable edge connecters. The assembly also includes a circuit board on which a semiconductor chip useful for signal processing and the electrical connector are mounted. A Flex circuit is used in connecting the circuit board to the parallel optic modules. The semiconductor chip and electrical connector are mounted directly across from one another on opposite surfaces of the circuit board using ball grid arrays having overlapping attachment structures.

Abstract translation: 一种用于具有多个平行光纤元件的光纤数字通信电缆的应答器组件。 应答器组件具有发射器端口和接收器端口，用于与用于单独发送和接收数据的单独的并行光缆连接，以及用于与计算机或通信系统连接的电连接器。 应答器组件包括并行光学发射器模块和具有可插拔边缘连接器的并行光纤接收器模块。 组件还包括其上安装用于信号处理的半导体芯片和电连接器的电路板。 Flex电路用于将电路板连接到并行光模块。 半导体芯片和电连接器使用具有重叠的附接结构的球栅阵列彼此直接地安装在电路板的相对表面上。