公开(公告)号：US20110081809A1

公开(公告)日：2011-04-07

申请号：US12572102

申请日：2009-10-01

Applicant: Chad W. Morgan

Inventor： Chad W. Morgan

IPC: H01R24/00 ,  H05K1/11

CPC classification number: H05K1/0219 ,  H05K1/0245 ,  H05K1/116 ,  H05K2201/09636 ,  H05K2201/10189

Abstract: A printed circuit includes a substrate having a pair of opposite sides. A signal via extends through at least one of the sides and at least partially through the substrate between the sides. Aggressor vias extend through at least one of the sides and at least partially through the substrate between the sides. The aggressor vias are arranged in a pattern around the signal via. Linear paths are defined between the signal via and the aggressor vias. At least some of the aggressor vias are arranged along the substrate directly adjacent the signal contact. Ground vias extend through at least one of the sides and at least partially through the substrate between the sides. The ground vias are arranged around the signal via. At least one ground via is positioned along each linear path between the signal via and each of the aggressor vias that is directly adjacent the signal via.

Abstract translation: 印刷电路包括具有一对相对侧的基板。 信号通孔延伸穿过至少一个侧面并且至少部分地穿过侧面之间的衬底。 侵略者通孔延伸穿过至少一个侧面并且至少部分地穿过两侧之间的基底。 侵略者通孔以信号通路周围的图案排列。 在信号通孔和侵略者通孔之间定义线性路径。 至少一些侵略者通孔沿着直接邻近信号触点的衬底排列。 接地通孔延伸穿过侧面中的至少一个并且至少部分地穿过侧面之间的衬底。 接地通孔围绕信号通道排列。 至少一个接地通孔沿着与信号通孔直接相邻的通道和每个侵略通道之间的每个线性路径定位。

公开(公告)号：US20090294168A1

公开(公告)日：2009-12-03

申请号：US12272797

申请日：2008-11-18

Applicant: YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU ,  YING-TSO LAI

Inventor： YU-CHANG PAI ,  SHOU-KUO HSU ,  CHIEN-HUNG LIU ,  YING-TSO LAI

IPC: H05K1/11

CPC classification number: H05K1/116 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/165 ,  H05K3/429 ,  H05K2201/09236 ,  H05K2201/09281 ,  H05K2201/09636

Abstract: A printed circuit board includes a first layout layer, a second layout layer, a copper foil layer, a first via and a second via. The first layout layer has a first signal line and a second signal line, each of which has a curved first portion. The second layout layer has a third signal line and a fourth signal line, each of which also has a curved first portion. The curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line are coupled to the first via and the second via. In this case, the curved first portions of the first signal line, the second signal line, the third signal line and the fourth signal line cooperatively generate spiral inductance characteristic.

Abstract translation: 印刷电路板包括第一布局层，第二布局层，铜箔层，第一通孔和第二通孔。 第一布局层具有第一信号线和第二信号线，每条信号线都具有弯曲的第一部分。 第二布局层具有第三信号线和第四信号线，每条信号线还具有弯曲的第一部分。 第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分耦合到第一通孔和第二通孔。 在这种情况下，第一信号线，第二信号线，第三信号线和第四信号线的弯曲的第一部分协同地产生螺旋电感特性。

公开(公告)号：US20090268369A1

公开(公告)日：2009-10-29

申请号：US12109356

申请日：2008-04-25

Applicant: Wei-Ting Chen ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Chang-Lin Wei ,  Cheng-Hua Tsai ,  Kuo-Chiang Chin

Inventor： Wei-Ting Chen ,  Chang-Sheng Chen ,  Chin-Sun Shyu ,  Chang-Lin Wei ,  Cheng-Hua Tsai ,  Kuo-Chiang Chin

IPC: H01G4/005

CPC classification number: H05K1/162 ,  H01G4/012 ,  H01G4/228 ,  H01G4/33 ,  H01L23/50 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/115 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/0969 ,  H05K2201/09718 ,  H01L2924/00

Abstract: A capacitor structure is provided. In the capacitor structure, a signal electrode plate and an extension ground electrode plate are disposed on the same plane to form a co-plane capacitor structure. Due to slow wave characteristic, the resonance frequency of the capacitor structure is effectively raised and the capacitor structure may be applied in high frequency.

Abstract translation: 提供电容器结构。 在电容器结构中，信号电极板和延伸接地电极板设置在同一平面上以形成共面电容器结构。 由于慢波特性，电容器结构的谐振频率有效提高，电容器结构可以高频应用。

公开(公告)号：US20090090465A1

公开(公告)日：2009-04-09

申请号：US12171658

申请日：2008-07-11

Applicant: Kalu K. Vasoya

Inventor： Kalu K. Vasoya

IPC: B32B37/00

CPC classification number: H05K3/4641 ,  H05K1/115 ,  H05K3/0005 ,  H05K3/0047 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4638 ,  H05K2201/0281 ,  H05K2201/0323 ,  H05K2201/068 ,  H05K2201/09236 ,  H05K2201/09636 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09718 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: Printed wiring boards and methods of manufacturing printed wiring boards are disclosed. In one aspect of the invention, the printed wiring boards include electrically conductive constraining cores having at least one resin filled channel. The resin filled channels perform a variety of functions that can be associated with electrical isolation and increased manufacturing yields.

Abstract translation: 公开了印刷电路板和制造印刷电路板的方法。 在本发明的一个方面，印刷电路板包括具有至少一个树脂填充通道的导电约束芯。 填充树脂的通道执行各种功能，可以与电气隔离和增加的制造产量相关联。

公开(公告)号：US20090031270A1

公开(公告)日：2009-01-29

申请号：US11829179

申请日：2007-07-27

Applicant: Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

Inventor： Daniel Douriet ,  Anand Haridass ,  Andreas Huber ,  Roger D. Weekly

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  H05K1/0216 ,  H05K1/115 ,  H05K3/0005 ,  H05K2201/09636

Abstract: A design method and system for minimizing blind via current loops provides for improvement of electrical interconnect structure design without requiring extensive electromagnetic analysis. Other vias in the vicinity of a blind via carrying a critical signal are checked for suitability to conduct return current corresponding to the critical signal that is disrupted by the transition from a layer between two metal planes to another layer. The distance to the return current via(s) is checked and the design is adjusted to reduce the distance if the distance is greater than a specified threshold. If the blind via transition is to an external layer, suitable vias connect the reference plane at the internal end of the blind via to an external terminal. If the transition is between internal layers, suitable vias are vias that connect the two reference planes surrounding the reference plane traversed by the blind via.

Abstract translation: 用于最小化盲通过电流回路的设计方法和系统提供了电互连结构设计的改进，而不需要广泛的电磁分析。 检查通过携带关键信号的盲目附近的其他通孔是否​​适合于进行对应于由两个金属平面之间的层到另一层之间的过渡而被破坏的关键信号的返回电流。 检查通过（s）的返回电流的距离，并且如果距离大于指定的阈值，则设计被调整以减小距离。 如果盲目通过转换到外部层，合适的通孔将盲通孔内部的参考平面连接到外部端子。 如果过渡在内层之间，合适的通孔是连接围绕由盲孔通过的参考平面的两个参考平面的通孔。

公开(公告)号：US20090015345A1

公开(公告)日：2009-01-15

申请号：US12281460

申请日：2007-03-02

Applicant: Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

Inventor： Taras Kushta ,  Kaoru Narita ,  Tomoyuki Kaneko ,  Shin-ichi Ogou

IPC: H03H7/38

CPC classification number: H05K1/116 ,  H05K1/0219 ,  H05K1/0222 ,  H05K1/0245 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/09718 ,  H05K2201/09727

Abstract: According to one embodiment, a broadband transition to joint a via structure and a planar transmission line in a multilayer substrate is formed as an intermediate connection between the signal via pad and the planar transmission line disposed at the same conductor layer. The transverse dimensions of the transition are equal to the via pad diameter at the one end and strip width at another end; The length of the transition can be equal to the characteristic dimensions of the clearance hole in the direction of the planar transmission line or defined as providing the minimal excess inductive reactance in time-domain according to numerical diagrams obtained by three-dimensional full-wave simulations.

Abstract translation: 根据一个实施例，形成在多层基板中连接通孔结构和平面传输线的宽带转变，作为信号通孔焊盘和布置在相同导体层处的平面传输线之间的中间连接。 过渡的横向尺寸等于一端的通孔焊盘直径和另一端的带宽度; 转换的长度可以等于平面传输线方向上的间隙孔的特征尺寸，或者定义为根据通过三维全波模拟获得的数值图在时域中提供最小的额外的电抗 。

公开(公告)号：US20070279878A1

公开(公告)日：2007-12-06

申请号：US11443763

申请日：2006-05-31

Applicant: Xingjian Cai ,  Ke Wang ,  Qing-lun Chen

Inventor： Xingjian Cai ,  Ke Wang ,  Qing-lun Chen

IPC: H05K7/00

CPC classification number: H05K1/115 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/112 ,  H05K3/3415 ,  H05K3/3421 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09236 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09709 ,  H05K2201/10189 ,  H05K2201/10659 ,  Y02P70/613

Abstract: A circuit board may include hybrid via structures configured to connect to components, such as connectors and electronic components, mounted on the circuit board. A hybrid via structure may include one or more micro-vias configured to provide an electrical connection to a signal trace in the circuit board and one or more through-vias configured to provide a ground connection to at least one reference plane in the circuit board. In one embodiment, a plurality of circuit boards including the hybrid via structures and signal traces may be connected to establish a channel supporting differential signaling and data transfer rates of at least about 5 Gb/s. Of course, many alternatives, variations, and modifications are possible without departing from this embodiment.

Abstract translation: 电路板可以包括被配置为连接到安装在电路板上的诸如连接器和电子部件的组件的混合通孔结构。 混合通孔结构可以包括一个或多个微通孔，其被配置为提供与电路板中的信号迹线的电连接以及被配置为提供到电路板中的至少一个参考平面的接地连接的一个或多个通孔。 在一个实施例中，可以连接包括混合通路结构和信号迹线的多个电路板，以建立支持至少约5Gb / s的差分信令和数据传输速率的信道。 当然，在不偏离本实施例的情况下，可以进行许多替代，变化和修改。

公开(公告)号：US20070258173A1

公开(公告)日：2007-11-08

申请号：US11430540

申请日：2006-05-08

Applicant: Houfei Chen ,  Shiyou Zhao

Inventor： Houfei Chen ,  Shiyou Zhao

IPC: H02H9/08

CPC classification number: H05K1/0216 ,  G11C5/04 ,  G11C5/063 ,  H05K1/0298 ,  H05K1/162 ,  H05K2201/09309 ,  H05K2201/09636 ,  H05K2201/09981 ,  H05K2203/0733 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: Substrates having power and ground planes, such as, for example, printed circuit boards, include at least one noise suppression structure configured to suppress electrical waves propagating through at least one of a power plane and a ground plane. The noise suppression structure may include a power plane extension that extends from the power plane generally towards the ground plane, and a ground plane extension that extends from the ground plane generally towards the power plane. The ground plane extension may be separated from the power plane extension by a distance that is less than the distance separating the power and ground planes. Electronic device assemblies and systems include such substrates. Methods for suppressing noise in at least one of a power plane and a ground plane include providing such noise suppression structures between power and ground planes.

Abstract translation: 具有电源和接地层的衬底，例如印刷电路板，包括至少一个噪声抑制结构，其被配置为抑制通过电力平面和接地平面中的至少一个传播的电波。 噪声抑制结构可以包括从功率平面大致朝向接地平面延伸的电源平面延伸部，以及从接地平面大致朝向电力平面延伸的接地平面延伸部。 接地平面延伸部可以与动力平面延伸部分离距离小于分离动力和接地平面的距离。 电子器件组件和系统包括这样的衬底。 用于抑制电力平面和接地平面中的至少一个中的噪声的方法包括在电源和接地层之间提供这种噪声抑制结构。

公开(公告)号：US20070257355A1

公开(公告)日：2007-11-08

申请号：US11797458

申请日：2007-05-03

Applicant: Norihito Suzuki ,  Akihiro Minoura

Inventor： Norihito Suzuki ,  Akihiro Minoura

IPC: H01L23/04

CPC classification number: H05K3/3447 ,  H05K1/0201 ,  H05K1/116 ,  H05K3/3468 ,  H05K2201/09572 ,  H05K2201/09636 ,  H05K2201/09781 ,  H05K2203/045

Abstract: In the vicinity of soldering through holes of lands for soldering a lead terminal in a multilayer printed board, electrically isolated lands are provided to form a thermal through hole. In the soldering, by the radiation and supply of heat of a lead-free solder filled in the thermal through hole, it is possible to suppress the radiation of heat of the soldering through hole. Thus, it is possible to achieve a sufficient solder rise and to obtain an excellent soldering property.

Abstract translation: 在用于焊接多层印刷电路板中的引线端子的焊盘通孔附近，设置电隔离焊盘以形成热通孔。 在焊接中，通过填充在热通孔中的无铅焊料的放射和供热，可以抑制焊接通孔的热辐射。 因此，可以实现足够的焊料上升并获得优异的焊接性能。

公开(公告)号：US20070194432A1

公开(公告)日：2007-08-23

申请号：US11443785

申请日：2006-05-30

Applicant: Hsing-Chou Hsu ,  Ying-Ni Lee

Inventor： Hsing-Chou Hsu ,  Ying-Ni Lee

IPC: H01L23/48 ,  H05K1/11

CPC classification number: H05K3/4602 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/0222 ,  H05K1/0263 ,  H05K1/112 ,  H05K1/115 ,  H05K2201/09536 ,  H05K2201/09636 ,  H05K2201/09781

Abstract: An arrangement of non-signal through vias suitable for a wiring board is provided. The wiring board has a contact surface, a core layer and pads. The contact pads are disposed on the contact surface, while the arrangement of non-signal through vias includes first non-signal through vias and a second non-signal through via. The first non-signal through vias pass through the core layer and are electrically connected to some of the contact pads. The second non-signal through via which passes through the core layer is disposed between the first non-signal through vias and is not electrically connected to the contact pads. The interval between the second non-signal through via and anyone of the surrounding first non-signal through vias is smaller than or equal to 0.72 times of the minimum interval between the second non-signal through via and one of the contact pads electrically connected to the corresponding first non-signal through vias.

Abstract translation: 提供了适用于布线板的非信号通孔的布置。 布线板具有接触表面，芯层和焊盘。 接触焊盘设置在接触表面上，而非信号通孔的布置包括第一非信号通孔和第二非信号通孔。 第一非信号通孔穿过芯层并电连接到一些接触垫。 穿过芯层的第二非信号通孔设置在第一非信号通孔之间，并且不电连接到接触焊盘。 第二非信号通孔之间的间隔与周围的第一非信号通孔中的任何一个之间的间隔小于或等于第二非信号通孔与电连接到第二非信号通孔之间的最小间隔的0.72倍 相应的第一个非信号通孔。