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    WIRE GRID POLARIZER AND METHOD OF FABRICATING THE SAME
    132.
    发明申请
    WIRE GRID POLARIZER AND METHOD OF FABRICATING THE SAME 有权
    电网极化器及其制造方法

    公开(公告)号：US20160077263A1

    公开(公告)日：2016-03-17

    申请号：US14623708

    申请日：2015-02-17

    Applicant: Samsung Display Co., Ltd.

    Inventor： Eun Ae KWAK ,  Min Hyuck KANG ,  Moon Gyu LEE

    IPC: G02B5/30 ,  G02F1/1335

    CPC classification number: G02B5/3058 ,  B81C1/00388 ,  B81C1/00404 ,  B81C2201/0149 ,  C09K13/00 ,  C23F4/00 ,  G02F2001/133548 ,  G03F7/0041 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3083 ,  H01L21/3086 ,  H01L21/3088

    Abstract: A method of fabricating a wire grid polarizer includes sequentially depositing a conductive wire pattern layer, and a plurality of guide patterns which forms one or more trenches therebetween on the conductive wire pattern layer, hydrophobically treating surfaces of the conductive wire pattern layer exposed in the trenches, and the guide patterns, coating the hydrophobically treated conductive wire pattern layer in the trenches with a neutral layer to partially fill the trenches, filling a remainder of the trenches with a block copolymer of two monomers with different etching rates, aligning the block copolymer filled in the trenches, selectively removing blocks of one monomer among the two monomers from the aligned block copolymer, and patterning the conductive wire pattern layer by using blocks of the other monomer among the two monomers remaining in the trenches and the guide patterns as a mask.

    Abstract translation: 制造线栅偏振器的方法包括依次沉积导线图案层和在导线图案层上形成一个或多个沟槽的多个引导图案，疏水处理暴露在沟槽中的导线图案层的表面 和引导图案，用中性层在沟槽中涂覆疏水处理的导线图案层以部分地填充沟槽，用不同蚀刻速率的两种单体的嵌段共聚物填充剩余的沟槽，使嵌段共聚物填充 在沟槽中，选择性地从对准的嵌段共聚物中除去两种单体中的一种单体的嵌段，并且通过使用留在沟槽中的两种单体中的其它单体的嵌段和导向图案作为掩模来对导电丝图案图案化。

    Pattern forming method
    133.
    发明授权
    Pattern forming method 有权
    图案形成方法

    公开(公告)号：US09279191B2

    公开(公告)日：2016-03-08

    申请号：US13784620

    申请日：2013-03-04

    Applicant: Kabushiki Kaisha Toshiba

    Inventor： Ayako Kawanishi

    IPC: C30B19/00 ,  H01L21/027 ,  H01L21/311 ,  B81C1/00

    CPC classification number: C30B19/00 ,  B81C1/00031 ,  B81C2201/0149 ,  B81C2201/0198 ,  G03F7/0002 ,  H01L21/0271 ,  H01L21/31144

    Abstract: According to one embodiment, a pattern forming method includes forming a graphoepitaxy on a substrate, a process of forming a first self-assembly material layer that contains a first segment and a second segment in a depressed portion of the graphoepitaxy, a process of forming a first self-assembly pattern that has a first region containing the first segment, and a second region containing the second segment by performing a phase separation of the first self-assembly material layer, a process of forming a second self-assembly material layer containing a third segment and a fourth segment on a projected portion of the graphoepitaxy, and the first self-assembly pattern, a process of forming a second self-assembly pattern that has a third region containing the third segment, and a fourth region containing the fourth segment by performing a phase separation of the second self-assembly material layer.

    Abstract translation: 根据一个实施例，图案形成方法包括在基底上形成划线蛋白石，形成第一自组装材料层的工艺，该第一自组装材料层包含第一部分和第二部分，所述第一部分和第二部分在凹凸部分中，形成 第一自组装图案，其具有包含第一段的第一区域，以及通过执行第一自组装材料层的相分离而包含第二区段的第二区域;形成包含第一自组装材料层的第二自组装材料层的工艺; 第三片段和第四片段，以及第一自组装图案，形成具有包含第三片段的第三区域的第二自组装图案的工艺，以及包含第四片段的第四片段 通过执行第二自组装材料层的相分离。

    Apparatus and method for forming self-assembly arrays
    134.
    发明授权
    Apparatus and method for forming self-assembly arrays 有权
    用于形成自组装阵列的装置和方法

    公开(公告)号：US09255002B2

    公开(公告)日：2016-02-09

    申请号：US12888146

    申请日：2010-09-22

    Applicant: Dan Luo ,  Wenlong Cheng

    Inventor： Dan Luo ,  Wenlong Cheng

    IPC: B82Y40/00 ,  B82Y30/00 ,  B81C99/00 ,  G03F7/004

    CPC classification number: B82Y40/00 ,  B81C99/0025 ,  B81C2201/0149 ,  B81C2201/0187 ,  B82Y30/00 ,  C07H21/00 ,  Y10S977/773 ,  Y10S977/774

    Abstract: Apparatus and methods for forming self-assembly arrays of substances, such as nanoparticles, on a substrate are disclosed. The apparatus may include a substrate supporting a liquid composition including the substance and a solvent, and a removable micro-mold placed over the substrate and the liquid composition. To form the self assembly arrays of the substance, the solvent may be evaporated through at least one evaporation channel formed between the micro-mold and the substrate. The evaporation channel may be adjustable by subjecting the micro-mold to a positive pressure.

    Abstract translation: 公开了用于在衬底上形成诸如纳米颗粒的物质自组装阵列的装置和方法。 该装置可以包括支撑包括物质和溶剂的液体组合物的基底和放置在基底和液体组合物上的可移除微型模具。 为了形成物质的自组装阵列，溶剂可以通过形成在微模和基底之间的至少一个蒸发通道蒸发。 可以通过使微型模具经受正压力来调节蒸发通道。

    Direct Current Superposition Curing for Resist Reflow Temperature Enhancement
    135.
    发明申请
    Direct Current Superposition Curing for Resist Reflow Temperature Enhancement 有权
    直流电流叠加固化抵抗回流温度增强

    公开(公告)号：US20160023238A1

    公开(公告)日：2016-01-28

    申请号：US14340721

    申请日：2014-07-25

    Applicant: Tokyo Electron Limited

    Inventor： Nihar Mohanty ,  Akiteru Ko ,  Chi-Chun Liu

    IPC: B05D1/32 ,  B05D3/02 ,  B05D1/00 ,  B05D3/06 ,  H01J37/32

    CPC classification number: H01J37/32091 ,  B81C1/00428 ,  B81C2201/0149 ,  G03F7/0002 ,  G03F7/40 ,  H01L21/0273 ,  H01L21/3065 ,  H01L21/3086 ,  H01L21/31058

    Abstract: Techniques herein include methods for curing a layer of material (such as a resist) on a substrate to enable relatively greater heat reflow resistance. Increasing reflow resistance enables successful directed self-assembly of block copolymers. Techniques include receiving a substrate having a patterned photoresist layer and positioning this substrate in a processing chamber of a capacitively coupled plasma system. The patterned photoresist layer is treated with a flux of electrons by coupling negative polarity direct current power to a top electrode of the plasma processing system during plasma processing. The flux of electrons is accelerated from the top electrode with sufficient energy to pass through a plasma and its sheath, and strike the substrate such that the patterned photoresist layer changes in physical properties, which can include an increased glass-liquid transition temperature.

    Abstract translation: 本文的技术包括用于固化衬底上的材料层（例如抗蚀剂）的方法，以使得能够相对更大的耐热回流性。 增加回流电阻使嵌段共聚物成功引导自组装。 技术包括接收具有图案化光致抗蚀剂层的衬底并将该衬底定位在电容耦合等离子体系统的处理室中。 通过在等离子体处理期间将负极性直流电力耦合到等离子体处理系统的顶部电极，用电子束来处理图案化的光致抗蚀剂层。 电子通量从顶部电极以足够的能量被加速以通过等离子体及其鞘，并撞击基板，使得图案化的光致抗蚀剂层的物理性质发生变化，这可能包括玻璃 - 液体转变温度升高。

    Methods of forming nanostructures including metal oxides
    138.
    发明授权
    Methods of forming nanostructures including metal oxides 有权
    形成纳米结构的方法，包括金属氧化物

    公开(公告)号：US09177795B2

    公开(公告)日：2015-11-03

    申请号：US14040245

    申请日：2013-09-27

    Applicant: Micron Technology, Inc.

    Inventor： Nicholas Hendricks ,  Adam L. Olson ,  William R. Brown ,  Ho Seop Eom ,  Xue Chen ,  Kaveri Jain ,  Scott Schuldenfrei

    IPC: H01L21/302 ,  H01L21/027 ,  C08G81/00

    CPC classification number: H01L21/0273 ,  B81C1/00031 ,  B81C2201/0149 ,  C08G81/00 ,  C08L53/005 ,  H01L21/02118 ,  H01L21/02175 ,  H01L21/02318 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31058

    Abstract: A method of forming nanostructures may include forming a block copolymer composition within a trench in a material on a substrate, wherein the block copolymer composition may comprise a block copolymer material and an activatable catalyst having a higher affinity for a first block of the block copolymer material compared to a second block of the block copolymer material; self-assembling the block copolymer composition into first domains comprising the first block and the activatable catalyst, and second domains comprising the second block; generating catalyst from the activatable catalyst in at least one portion of the first domains to produce a structure comprising catalyst-containing domains and the second domains, the catalyst-containing domains comprising the first block and the catalyst; and reacting a metal oxide precursor with the catalyst in the catalyst-containing domains to produce a metal oxide-containing structure comprising the first block and metal oxide.

    Abstract translation: 形成纳米结构的方法可以包括在衬底中的材料中的沟槽内形成嵌段共聚物组合物，其中嵌段共聚物组合物可以包含嵌段共聚物材料和对于嵌段共聚物材料的第一嵌段具有更高亲和力的可活化催化剂 与第二嵌段共聚物材料相比; 将嵌段共聚物组合物自组装成包含第一嵌段和可活化催化剂的第一畴，以及包含第二嵌段的第二畴; 在第一区域的至少一部分中从可活化催化剂产生催化剂以产生包含含催化剂的区域和第二区域的结构，所述含催化剂的区域包含第一嵌段和催化剂; 并使金属氧化物前体与含催化剂的区域中的催化剂反应，以制备包含第一嵌段和金属氧化物的含金属氧化物的结构。

    Sequential Infiltration Synthesis for Advanced Lithography
    139.
    发明申请
    Sequential Infiltration Synthesis for Advanced Lithography 有权
    高级光刻的顺序渗透合成

    公开(公告)号：US20150255298A1

    公开(公告)日：2015-09-10

    申请号：US14645162

    申请日：2015-03-11

    Applicant: UChicago Argonne LLC

    Inventor： Seth B. Darling ,  Jeffrey W. Elam ,  Yu-Chih Tseng ,  Qing Peng

    IPC: H01L21/308 ,  H01L21/3065 ,  H01L21/027

    CPC classification number: H01L21/3081 ,  B81C1/00428 ,  B81C2201/0149 ,  B82Y40/00 ,  G03F7/0041 ,  G03F7/405 ,  H01L21/0273 ,  H01L21/0274 ,  H01L21/0277 ,  H01L21/0279 ,  H01L21/3065 ,  H01L21/3086 ,  Y10T428/31522

    Abstract: A plasma etch resist material modified by an inorganic protective component via sequential infiltration synthesis (SIS) and methods of preparing the modified resist material. The modified resist material is characterized by an improved resistance to a plasma etching or related process relative to the unmodified resist material, thereby allowing formation of patterned features into a substrate material, which may be high-aspect ratio features. The SIS process forms the protective component within the bulk resist material through a plurality of alternating exposures to gas phase precursors which infiltrate the resist material. The plasma etch resist material may be initially patterned using photolithography, electron-beam lithography or a block copolymer self-assembly process.

    Abstract translation: 通过连续渗透合成（SIS）由无机保护组分改性的等离子体蚀刻抗蚀剂材料和制备改性抗蚀剂材料的方法。 改进的抗蚀剂材料的特征在于相对于未改性的抗蚀剂材料具有改进的抗等离子体蚀刻或相关工艺的耐受性，从而允许将图案化特征形成到基底材料中，该基材可以是高纵横比特征。 SIS工艺通过对渗透抗蚀剂材料的气相前体的多次交替曝光而在体抗蚀材料内形成保护组分。 可以使用光刻，电子束光刻或嵌段共聚物自组装工艺来初始图案化等离子体蚀刻抗蚀剂材料。

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