公开(公告)号：US20160262269A1

公开(公告)日：2016-09-08

申请号：US14640993

申请日：2015-03-06

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Chiao-Cheng Chang ,  Yi-Nong Lin

IPC: H05K3/18 ,  H05K3/06

CPC classification number: H05K3/205 ,  H05K2201/0376 ,  H05K2203/0376

Abstract: Disclosed is a copper etching method for manufacturing a circuit board, including steps of electroplating a metal copper support layer, coating a thermal sensitive photo resist layer, coating a photo resist layer, performing a process of pattern transfer, removing part of the photo resist layer to form a photo resist pattern, electroplating a metal copper layer to form a circuit pattern, peeling off the photo resist layer, pressing a stacked body composed of a stacked substrate and a stacked material layer onto the circuit pattern to embed the circuit pattern in the stacked material layer, removing the base layer, performing a copper etching process to removing the metal copper support layer, and removing the thermal sensitive photo resist layer to expose the circuit pattern. In particular, the circuit pattern protrudes from the stacked material layer so as to facilitate the subsequent process of forming solder balls.

Abstract translation: 公开了一种用于制造电路板的铜蚀刻方法，包括以下步骤：电镀金属铜支撑层，涂覆热敏光致抗蚀剂层，涂覆光致抗蚀剂层，执行图案转印工艺，去除部分光致抗蚀剂层 以形成光刻胶图形，电镀金属铜层以形成电路图案，剥离光致抗蚀剂层，将由堆叠的基板和堆叠的材料层组成的堆叠体压在电路图案上，以将电路图案嵌入到 层叠材料层，去除基底层，进行铜蚀刻工艺以除去金属铜载体层，以及去除热敏光刻胶层以暴露电路图案。 特别地，电路图案从堆叠的材料层突出，以便于随后的形成焊球的工艺。

公开(公告)号：US20160233152A1

公开(公告)日：2016-08-11

申请号：US15133244

申请日：2016-04-20

Applicant: IBIS Innotech Inc.

Inventor： Wen-Chun Liu

IPC: H01L23/495 ,  H01L21/768

CPC classification number: H01L23/49586 ,  H01L21/4828 ,  H01L21/76823 ,  H01L21/76825 ,  H01L23/13 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49558 ,  H01L23/49861 ,  H01L2224/48091 ,  H01L2924/181 ,  H05K1/0373 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00012 ,  H01L2924/00014

Abstract: A package structure includes a lead frame, a selective-electroplating epoxy compound, conductive vias and a patterned circuit layer. The lead frame includes a metal stud array having metal studs. The selective-electroplating epoxy compound covers the metal stud array. The selective-electroplating epoxy compound includes non-conductive metal complex. The conductive vias are directly embedded in the selective electroplating epoxy compound to be respectively connected to the metal studs and extended to a top surface of the selective-electroplating epoxy compound. Each of the conductive vias includes a lower segment connected to the corresponding metal stud and an upper segment connected to the lower segment and extended to the top surface, and a smallest diameter of the upper segment is greater than a largest diameter of the lower segment. The patterned circuit layer is directly disposed on the top surface and electrically connected to the conductive vias.

Abstract translation: 封装结构包括引线框，选择性电镀环氧化合物，导电通孔和图案化电路层。 引线框架包括具有金属螺柱的金属螺柱阵列。 选择性电镀环氧化合物覆盖金属螺柱阵列。 选择性电镀环氧化合物包括非导电金属络合物。 导电通孔直接嵌入选择性电镀环氧化合物中，以分别连接到金属螺柱并延伸到选择性电镀环氧化合物的顶表面。 每个导电通孔包括连接到相应的金属螺柱的下部段和连接到下部段并延伸到顶部表面的上段，并且上段的最小直径大于下段的最大直径。 图案化电路层直接设置在顶表面上并电连接到导电通孔。

公开(公告)号：US20160198571A1

公开(公告)日：2016-07-07

申请号：US14989412

申请日：2016-01-06

Applicant: INDUSTRY-ACADEMIC COOPERATION FOUNDATION, YONSEI UNIVERSITY

Inventor： Jin Woo PARK

IPC: H05K1/09 ,  H05K1/02 ,  H01M4/04 ,  H01L51/52

CPC classification number: H05K1/092 ,  H01L51/444 ,  H05K1/0274 ,  H05K3/0014 ,  H05K3/207 ,  H05K2201/0108 ,  H05K2201/026 ,  H05K2201/0376 ,  Y02E10/549 ,  Y02P70/521

Abstract: Disclosed is a transparent electrode including a transparent substrate 100, conductive nanowires 10 forming networks, nanoparticles bonding the nanowires 10, and a conductive layer embedded in the transparent substrate 100.

Abstract translation: 公开了一种透明电极，其包括透明基板100，形成网络的导电纳米线10，结合纳米线10的纳米线，以及嵌入在透明基板100中的导电层。

公开(公告)号：US20160043027A1

公开(公告)日：2016-02-11

申请号：US14820963

申请日：2015-08-07

Applicant: IBIDEN CO., LTD.

Inventor： Yasushi INAGAKI ,  Kota NODA

IPC: H01L23/498 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0278 ,  H05K1/111 ,  H05K3/4015 ,  H05K2201/0376 ,  H05K2201/09827 ,  H01L2924/00

Abstract: A printed wiring board includes an insulating layer, a first conductor layer embedded into first surface of the insulating layer and including multiple wirings such that the wirings include connecting portions positioned to connect an electronic component, respectively, a second conductor layer projecting from second surface of the insulating layer on the opposite side, a solder resist layer formed on the first surface of the insulating layer such that the solder resist layer is covering the first conductor layer and has an opening structure exposing the connecting portions of the wirings, and multiple metal posts formed on the connecting portions respectively such that each of the metal posts has a width which is larger than a width of a respective one of the wirings having the connecting portions. The wirings are formed such that the connecting portions are positioned side by side on every other adjacent one of the wirings.

Abstract translation: 印刷布线板包括绝缘层，第一导体层，其嵌入在绝缘层的第一表面中并且包括多个布线，使得布线包括分别定位成连接电子部件的连接部分，第二导体层从第二表面的第二表面突出 在相对侧的绝缘层，形成在绝缘层的第一表面上的阻焊层，使得阻焊层覆盖第一导体层并具有露出布线的连接部分的开口结构，以及多个金属柱 分别形成在连接部分上，使得每个金属柱的宽度大于具有连接部分的各个布线的宽度。 布线形成为使得连接部分并排布置在每隔一个相邻的布线之间。

公开(公告)号：US09230895B2

公开(公告)日：2016-01-05

申请号：US13191807

申请日：2011-07-27

Applicant: Pao-Hung Chou ,  Hsien-Min Chang

Inventor： Pao-Hung Chou ,  Hsien-Min Chang

IPC: H01L23/498 ,  H05K3/00 ,  H05K3/10 ,  C25D5/02 ,  C25D7/12 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31 ,  H05K1/11 ,  H05K3/28

CPC classification number: H01L23/49811 ,  C25D5/02 ,  C25D7/12 ,  H01L21/4853 ,  H01L23/3128 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48245 ,  H01L2224/48247 ,  H01L2924/00014 ,  H01L2924/181 ,  H05K1/111 ,  H05K3/0097 ,  H05K3/107 ,  H05K3/282 ,  H05K2201/0376 ,  H05K2203/1536 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A package substrate includes: a dielectric layer having two opposite surfaces; a wiring layer embedded in the dielectric layer and exposed from the two opposite surfaces of the dielectric layer, wherein the wiring layer has solder pads, conductive pads and circuit wires electrically connecting the solder pads and the conductive pads; and a first insulating protection layer disposed on one of the two opposite surfaces of the dielectric layer to cover the dielectric layer and the wiring layer and having a plurality of openings for exposing the conductive pads, respectively. The package substrate, by directly using the dielectric layer as a base, provides a package substrate having reduced thickness and lower fabrication costs compared to the prior art.

Abstract translation: 封装基板包括：具有两个相对表面的电介质层; 介于所述电介质层中并且从所述电介质层的两个相对表面露出的布线层，其中所述布线层具有焊接焊盘，导电焊盘和电连接所述焊盘和所述导电焊盘的电路线; 以及第一绝缘保护层，其设置在电介质层的两个相对表面之一上以覆盖电介质层和布线层，并且具有多个用于暴露导电焊盘的开口。 通过直接使用电介质层作为基底，封装衬底提供了与现有技术相比具有减小的厚度和较低制造成本的封装衬底。

公开(公告)号：US20150373849A1

公开(公告)日：2015-12-24

申请号：US14663447

申请日：2015-03-19

Applicant: IBIS Innotech Inc.

Inventor： Chih-Kung Huang ,  Wei-Jen Lai ,  Wen-Chun Liu

IPC: H05K1/11 ,  H05K1/18 ,  H05K1/03

CPC classification number: H05K1/0373 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/04 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1715 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface. The conductive vias are disposed at the selective-electroplating epoxy compound to electrically connect the second patterned circuit layers to the corresponding metal studs.

Abstract translation: 封装结构包括选择性电镀环氧化合物，第一图案化电路层，第二图案化电路层，金属柱，接触焊盘和导电通孔。 选择性电镀环氧化合物包括空腔，第一表面和第二表面。 排列在第一表面上的空腔。 选择性电镀环氧化合物通过组合非导电金属络合物形成。 金属螺柱分别设置在空腔中并从第一表面突出。 第一图案化电路层直接设置在第一表面上。 选择性电镀环氧化合物暴露图案化电路层的顶表面。 顶面低于或与第一表面共面。 第二图案化电路层直接设置在第二表面上。 导电通孔设置在选择性电镀环氧化合物处，以将第二图案化电路层电连接到相应的金属螺柱。

公开(公告)号：US09210808B2

公开(公告)日：2015-12-08

申请号：US13616348

申请日：2012-09-14

Applicant: Kentaro Kaneko ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

Inventor： Kentaro Kaneko ,  Toshimitsu Omiya ,  Kotaro Kodani ,  Junichi Nakamura ,  Kazuhiro Kobayashi

IPC: H05K1/11 ,  H05K3/46 ,  H01L23/00 ,  H01L23/544 ,  H01L21/683 ,  H01L23/13 ,  H01L23/498 ,  H01L21/48

CPC classification number: H05K3/188 ,  C25D5/022 ,  H01L21/4857 ,  H01L21/6835 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/544 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2221/68381 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/92125 ,  H01L2924/12042 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/0017 ,  H05K3/46 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2203/0369 ,  H05K2203/0376 ,  H05K2203/06 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A wiring substrate includes an insulating layer, a connection pad buried in the insulating layer in a state that an upper surface of the connection pad is exposed from an upper surface of the insulating layer and a lower surface and at least a part of a side surface of the connection pad contact the insulating layer, and a concave level difference portion formed in the insulating layer around an outer periphery part of the connection pad, wherein an upper surface of the connection pad and an upper surface of the insulating layer are arranged at a same height.

Abstract translation: 布线基板包括绝缘层，埋置在绝缘层中的连接焊盘，该连接焊盘处于连接焊盘的上表面从绝缘层的上表面露出的状态以及下表面和侧表面的至少一部分 所述连接焊盘与所述绝缘层接触，以及形成在所述绝缘层中的所述连接焊盘的外周部分的凹陷高度差部分，其中所述连接焊盘的上表面和所述绝缘层的上表面被布置在 相同的高度

公开(公告)号：US20150334826A1

公开(公告)日：2015-11-19

申请号：US14281631

申请日：2014-05-19

Applicant: Konstantine Karavakis ,  Kenneth S. Bahl ,  Steve Carney

Inventor： Konstantine Karavakis ,  Kenneth S. Bahl ,  Steve Carney

IPC: H05K1/03 ,  H05K3/40 ,  H05K3/08 ,  H05K3/10 ,  H05K1/09 ,  H05K1/11

CPC classification number: H05K1/0306 ,  H05K1/09 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/08 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4038 ,  H05K2201/017 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2203/025 ,  H05K2203/0716 ,  H05K2203/107

Abstract: A printed circuit board includes a laminate substrate. The laminate substrate includes catalytic material that resists metal plating except where a surface of the catalytic material is ablated. Metal traces are formed within in trace channels within the laminate substrate. The channels extend below the surface of the catalytic material.

Abstract translation: 印刷电路板包括层叠基板。 层压基板包括抵抗金属电镀的催化材料，除了催化材料的表面被烧蚀之外。 金属痕迹形成在层压基板内的痕迹通道内。 通道延伸到催化材料的表面之下。

公开(公告)号：US20150282314A1

公开(公告)日：2015-10-01

申请号：US14674301

申请日：2015-03-31

Applicant: IBIDEN CO., LTD.

Inventor： Toru FURUTA ,  Takeshi FURUSAWA ,  Tomoya TERAKURA

IPC: H05K1/11 ,  H05K3/42 ,  H05K3/40 ,  H05K1/09 ,  H05K3/06

CPC classification number: H05K3/4007 ,  H05K1/0271 ,  H05K1/111 ,  H05K3/0097 ,  H05K3/282 ,  H05K3/3436 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09745 ,  H05K2201/09772 ,  H05K2203/0369 ,  H05K2203/1536 ,  Y02P70/611 ,  Y10T29/49165

Abstract: A method for manufacturing a printed wiring board with conductive posts includes forming on a first foil provided on carrier a first conductive layer including mounting pattern to connect electronic component via conductive posts, forming on the first foil a laminate including an insulating layer and a second foil to form the laminate on the first conductive layer, removing the carrier, forming a metal film on the laminate and first film, forming resist on the metal film to have pattern exposing portion of the metal film corresponding to the mounting pattern and portion of the second foil for a second conductive layer, forming an electroplating layer on the portion of the metal film not covered by the resist, removing the resist, and applying etching to remove the first and second foils below the metal film exposed by the removing the resist and to form the posts on the mounting pattern.

Abstract translation: 一种用于制造具有导电柱的印刷线路板的方法，包括在载体上形成第一导电层，第一导电层包括安装图案，以经由导电柱连接电子部件，在第一箔上形成包括绝缘层和第二箔 在第一导电层上形成层压体，去除载体，在层压体上形成金属膜和第一膜，在金属膜上形成抗蚀剂，使金属膜的图案曝光部分对应于安装图案和第二导电层的部分 箔片用于第二导电层，在未被抗蚀剂覆盖的金属膜的部分上形成电镀层，去除抗蚀剂，并施加蚀刻以除去通过除去抗蚀剂暴露的金属膜下面的第一和第二箔，并且 形成安装模式上的柱。

公开(公告)号：US20150282306A1

公开(公告)日：2015-10-01

申请号：US14225671

申请日：2014-03-26

Applicant: KINSUS INTERCONNECT TECHNOLOGY CORP.

Inventor： Ting-Hao Lin ,  Yu-Te Lu

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09

CPC classification number: H05K3/4679 ,  H05K1/116 ,  H05K2201/0376

Abstract: A multilayer substrate structure includes a first plastic sheet, a second plastic sheet, a first circuit pattern layer, a second circuit pattern layer, and an interlayer connection pad. A first connection plug connected to the interlayer connection pad fills in a first opening of a first plastic sheet and is connected to a first connection pad of the first circuit pattern layer. A second connection plug fills a second opening of the second plastic sheet and is connected to a second connection pad of the second circuit pattern layer such that the second circuit pattern layer is electrically connected to the first circuit pattern layer via the interlayer connection pad. Therefore, even if there is little offset, it is possible to overcome the alignment tolerance and assure electrical connection between the circuit layers as desired.

Abstract translation: 多层基板结构包括第一塑料片，第二塑料片，第一电路图案层，第二电路图案层和层间连接垫。 连接到层间连接焊盘的第一连接插头填充第一塑料片的第一开口并连接到第一电路图案层的第一连接焊盘。 第二连接插头填充第二塑料片的第二开口并且连接到第二电路图案层的第二连接焊盘，使得第二电路图案层经由层间连接焊盘电连接到第一电路图案层。 因此，即使几乎没有偏移，也可以克服对准公差，并且根据需要确保电路层之间的电连接。