公开(公告)号：US20230354529A1

公开(公告)日：2023-11-02

申请号：US18124431

申请日：2023-03-21

Applicant: AT & S Austria Technologie & Systemtechnik AG

Inventor： Marco Gavagnin

IPC: H05K3/46 ,  H05K1/02

CPC classification number: H05K3/4644 ,  H05K1/0213 ,  H05K2201/026 ,  H05K2201/0379

Abstract: Described herein is a component carrier, wherein the component carrier comprises a stack comprising a plurality of electrically conductive layer structures and at least one electrically insulating layer structure, wherein a first of said electrically conductive layer structures comprises a first surface where a first plurality of conductive nanowires is connected and a second of said electrically conductive layer structures comprises a second surface where a second plurality of conductive nanowires is connected, wherein said first and second surfaces and said first and second pluralities of nanowires are configured to at least partially connect the nanowires of the first plurality of nanowires with the respective nanowires of the second plurality of nanowires.

公开(公告)号：US11728258B2

公开(公告)日：2023-08-15

申请号：US17536711

申请日：2021-11-29

Applicant: INTEL CORPORATION

Inventor： Aleksandar Aleksov ,  Veronica Strong ,  Kristof Darmawikarta ,  Arnab Sarkar

IPC: H05K1/02 ,  H05K1/03 ,  H05K1/09 ,  H05K3/02 ,  H05K3/06 ,  H05K3/07 ,  H05K3/10 ,  H01L21/00 ,  H01L21/48 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H05K1/11 ,  H05K3/18

CPC classification number: H01L23/49827 ,  H01L21/486 ,  H01L23/49866 ,  H05K1/113 ,  H05K3/184 ,  H05K2201/0379 ,  H05K2203/0565

Abstract: A package substrate, comprising a package comprising a substrate, the substrate comprising a dielectric layer, a via extending to a top surface of the dielectric layer; and a bond pad stack having a central axis and extending laterally from the via over the first layer. The bond pad stack is structurally integral with the via, wherein the bond pad stack comprises a first layer comprising a first metal disposed on the top of the via and extends laterally from the top of the via over the top surface of the dielectric layer adjacent to the via. The first layer is bonded to the top of the via and the dielectric layer, and a second layer is disposed over the first layer. A third layer is disposed over the second layer. The second layer comprises a second metal and the third layer comprises a third metal. The second layer and the third layer are electrically coupled to the via.

公开(公告)号：US09706668B2

公开(公告)日：2017-07-11

申请号：US14921633

申请日：2015-10-23

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Da-Hee Kim ,  Sung-Won Jeong ,  Gi-Ho Han

IPC: H05K7/20 ,  H05K3/40 ,  H05K1/02 ,  H01L23/473 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/4038 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/0035 ,  H05K3/0097 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/0391 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1536 ,  H01L2924/00014

Abstract: A printed circuit board, an electronic module and a method of manufacturing the printed circuit board are provided. The printed circuit board includes a plurality of insulation layers, metal layers formed on the plurality of insulation layers, a via formed for interlayer electrical connection of the metal layers, a trench penetrating the insulation layers, and a heat-transfer structure formed in the trench.

公开(公告)号：US20160381800A1

公开(公告)日：2016-12-29

申请号：US14748496

申请日：2015-06-24

Applicant: INTEL CORPORATION

Inventor： Naga Sivakumar Yagnamurthy ,  Huiyang Fei ,  Pramod Malatkar ,  Prasanna Raghavan ,  Robert Nickerson

IPC: H05K1/18 ,  B29C70/84 ,  B29C70/70 ,  G11C11/401 ,  B29C37/00 ,  B29C33/00 ,  B29C69/00 ,  H05K1/11 ,  B29C70/88

CPC classification number: H05K1/181 ,  B29C33/0033 ,  B29C37/0025 ,  B29C69/001 ,  B29C70/70 ,  B29C70/84 ,  B29C70/882 ,  B29K2063/00 ,  B29K2995/0005 ,  B29L2031/3481 ,  G11C5/04 ,  G11C11/401 ,  H01L23/48 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/1815 ,  H05K1/111 ,  H05K1/144 ,  H05K2201/0379 ,  H05K2201/09036 ,  H05K2201/10159 ,  H05K2203/041

Abstract: Methods of forming a package structures comprising a trench are described. An embodiment includes a first die disposed on a first substrate, and at least one interconnect structure disposed on a peripheral region of the first substrate. A molding compound is disposed on a portion of the first substrate and on the first die, wherein a trench opening is disposed in the molding compound that is located between the at least one interconnect structure and the first die.

Abstract translation: 描述形成包括沟槽的封装结构的方法。 实施例包括设置在第一基板上的第一管芯和设置在第一基板的周边区域上的至少一个互连结构。 在第一基板的一部分上和第一模具上设置模塑料，其中沟槽开口设置在位于至少一个互连结构和第一模之间的模塑料中。

公开(公告)号：US09351436B2

公开(公告)日：2016-05-24

申请号：US13790141

申请日：2013-03-08

Applicant: Milind Raje ,  Robert Bennett ,  Andrew Mudie ,  Gary Mark Ignacio

Inventor： Milind Raje ,  Robert Bennett ,  Andrew Mudie ,  Gary Mark Ignacio

IPC: B23K1/06 ,  B23K26/00 ,  H05K13/04 ,  B23K20/00 ,  A61N1/375 ,  H05K3/34 ,  H05K3/40 ,  A61N1/36

CPC classification number: H05K13/0465 ,  A61N1/36032 ,  A61N1/36036 ,  A61N1/3754 ,  B23K1/06 ,  B23K20/004 ,  B23K26/21 ,  H01L2224/78301 ,  H01L2924/0002 ,  H05K3/3478 ,  H05K3/4007 ,  H05K3/4015 ,  H05K2201/0379 ,  H05K2201/0979 ,  H05K2201/10318 ,  H05K2203/0285 ,  H05K2203/049 ,  H05K2203/107 ,  H01L2924/0001

Abstract: Presented herein are stud bump bonding techniques for electrically connecting an elongate conductor, such as a wire or pin, to a bonding pad. A plurality of stud bumps are bonded to a surface of a bonding pad and an elongate electrical conductor is positioned in proximity to the plurality of stud bumps. The elongate conductor is bonded to one or more of the stud bumps.

Abstract translation: 这里呈现的是用于将细长导体（例如导线或针）电连接到接合焊盘的凸起焊接技术。 多个柱形凸起结合到接合焊盘的表面上，并且细长电导体位于多个柱形凸起附近。 细长导体结合到一个或多个螺柱凸块。

公开(公告)号：US20160120060A1

公开(公告)日：2016-04-28

申请号：US14921633

申请日：2015-10-23

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Da-Hee KIM ,  Sung-Won JEONG ,  Gi-Ho HAN

IPC: H05K7/20 ,  H05K1/18 ,  H05K3/40 ,  H05K3/30 ,  H05K3/46 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K3/4038 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/0204 ,  H05K1/0206 ,  H05K3/0035 ,  H05K3/0097 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/0391 ,  H05K2203/0723 ,  H05K2203/1476 ,  H05K2203/1536 ,  H01L2924/00014

Abstract: A printed circuit board, an electronic module and a method of manufacturing the printed circuit board are provided. The printed circuit board includes a plurality of insulation layers, metal layers formed on the plurality of insulation layers, a via formed for interlayer electrical connection of the metal layers, a trench penetrating the insulation layers, and a heat-transfer structure formed in the trench.

Abstract translation: 提供印刷电路板，电子模块和制造印刷电路板的方法。 印刷电路板包括多个绝缘层，形成在多个绝缘层上的金属层，形成用于金属层的层间电连接的通孔，穿过绝缘层的沟槽以及形成在沟槽中的传热结构 。

公开(公告)号：US09226406B2

公开(公告)日：2015-12-29

申请号：US13377998

申请日：2010-06-04

Applicant: Masamichi Yamamoto ,  Kyouichirou Nakatsugi ,  Yasuhiro Okuda

Inventor： Masamichi Yamamoto ,  Kyouichirou Nakatsugi ,  Yasuhiro Okuda

IPC: B32B9/04 ,  H05K3/32 ,  C09J9/02 ,  H05K3/36 ,  H05K3/28

CPC classification number: H05K3/323 ,  C09J9/02 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/01005 ,  H01L2924/01027 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12044 ,  H05K3/282 ,  H05K3/361 ,  H05K2201/023 ,  H05K2201/0379 ,  Y10T156/10 ,  H01L2924/00

Abstract: By connecting together connecting electrodes having an organic film serving as an oxidation-preventing film using a conductive adhesive, the manufacturing process can be simplified, and a highly reliable connection structure can be constructed at low cost. An electrode connection method, in which a first connecting electrode 2 and a second connecting electrode 10 are connected together through a conductive adhesive 9 that is interposed between the electrodes, includes an organic film formation step in which an organic film 6 is formed on at least a surface of the first connecting electrode, and an electrode connection step in which the first connecting electrode and the second connecting electrode are connected together through the conductive adhesive. In the electrode connection step, by allowing an organic film decomposing component mixed in the conductive adhesive to act on the organic film, the organic film is decomposed, and thus connection between the connecting electrodes is performed.

Abstract translation: 通过使用导电粘合剂将具有用作防氧化膜的有机膜的连接电极连接在一起，可以简化制造工艺，并且可以以低成本构建高可靠性的连接结构。 一种电极连接方法，其中第一连接电极2和第二连接电极10通过介于电极之间的导电粘合剂9连接在一起，包括至少形成有机膜6的有机膜形成步骤 第一连接电极的表面和电极连接步骤，其中第一连接电极和第二连接电极通过导电粘合剂连接在一起。 在电极连接工序中，通过使在导电性粘合剂中混合的有机膜分解成分作用于有机膜，有机膜分解，从而进行连接电极之间的连接。

公开(公告)号：US09059070B2

公开(公告)日：2015-06-16

申请号：US14077126

申请日：2013-11-11

Applicant: SK hynix Inc.

Inventor： Peter C. Salmon

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46 ,  H05K3/00

CPC classification number: H01L24/16 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/25 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/1134 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/73204 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4682 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/29099 ,  H01L2924/20751 ,  H01L2924/00

Abstract: A circuit assembly includes a plurality of integrated circuits having stud bumps at each input/output pad, an interconnection circuit having wells filled with solder, said wells corresponding in a one-to-one relationship with said stud bumps of said integrated circuits, and electrical and mechanical bonding at each of said input/output pads, wherein each of said stud bumps connects with solder in each of said wells to form a permanent connection.

Abstract translation: 电路组件包括多个集成电路，每个集成电路在每个输入/输出焊盘处具有柱形突起，互连电路具有填充有焊料的阱，所述阱与所述集成电路的所述柱形突起以一对一关系对应， 以及在每个所述输入/输出焊盘处的机械接合，其中每个所述柱形凸块与每个所述孔中的焊料连接以形成永久连接。

公开(公告)号：US08841772B2

公开(公告)日：2014-09-23

申请号：US13777670

申请日：2013-02-26

Applicant: Panasonic Corporation

Inventor： Yoshiaki Shimizu ,  Yuichiro Yamada ,  Toshiyuki Fukuda

IPC: H01L23/00

CPC classification number: H05K3/38 ,  B29C43/18 ,  B29C45/02 ,  B29C45/14655 ,  H01L21/565 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/27 ,  H01L24/28 ,  H01L24/29 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/743 ,  H01L24/83 ,  H01L24/85 ,  H01L25/105 ,  H01L2224/05554 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/291 ,  H01L2224/29109 ,  H01L2224/29111 ,  H01L2224/29144 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29339 ,  H01L2224/32225 ,  H01L2224/32506 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4809 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/743 ,  H01L2224/83101 ,  H01L2224/83192 ,  H01L2224/83805 ,  H01L2224/83856 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01014 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/07802 ,  H01L2924/12042 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/20751 ,  H01L2924/20752 ,  H01L2924/20753 ,  H01L2924/3511 ,  H05K3/3457 ,  H05K2201/0379 ,  H05K2201/10515 ,  H05K2201/10977 ,  H05K2203/0278 ,  H01L2924/00014 ,  H01L2924/07025 ,  H01L2924/0635 ,  H01L2924/00 ,  H01L2924/01083 ,  H01L2924/01049 ,  H01L2924/00012 ,  H01L2924/0695

Abstract: A semiconductor device capable of realizing highly reliable three-dimensional mounting, and a method of manufacturing the same, are provided. A projected electrode 9 is formed in a region outside of an element mounting region of a substrate 5. The projected electrode 9 includes a protruding portion that protrudes from the front face of a molding resin portion 10. The distal end of the protruding portion is a flat face 13. In addition, a portion of the projected electrode 9 whose cross section is larger than the protruding portion is positioned inside the molding resin portion 10.

Abstract translation: 提供能够实现高度可靠的三维安装的半导体器件及其制造方法。 突起电极9形成在基板5的元件安装区域的外侧的区域中。突出电极9包括从模制树脂部分10的前表面突出的突出部分。突出部分的远端是 另外，突出电极9的横截面大于突出部分的部分位于模制树脂部分10的内部。

公开(公告)号：US08736064B2

公开(公告)日：2014-05-27

申请号：US12941511

申请日：2010-11-08

Applicant: Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

Inventor： Hideki Kotake ,  Kiyoshi Hyodo ,  Inetaro Kurosawa ,  Yukio Hashimoto ,  Toku Yoshino ,  Tomoo Iijima

IPC: H01L23/522

CPC classification number: H05K3/4038 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/20 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4647 ,  H05K3/4658 ,  H05K2201/0379 ,  H05K2201/09536 ,  H05K2201/096 ,  H05K2201/10378 ,  H05K2203/0376 ,  H05K2203/0384 ,  H05K2203/0733 ,  H05K2203/1536 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: An interconnect element is provided. A monolithic dielectric element has a first exposed major surface, a plurality of first recesses extending inwardly from the first major surface, and a second exposed major surface remote from the first major surface, a plurality of second recesses extending inwardly from the second major surface. A plurality of first metal interconnect patterns are embedded in the plurality of first recesses and extend in one or more directions along the first major surface. A plurality of second metal interconnect patterns are embedded in the plurality of second recesses and extend in one or more directions along the second major surface. A plurality of non-hollow metal posts extend through the dielectric element between at least some of the plurality of first metal interconnect patterns and at least some of the plurality of second metal interconnect patterns.

Abstract translation: 提供互连元件。 单片电介质元件具有第一暴露的主表面，从第一主表面向内延伸的多个第一凹槽和远离第一主表面的第二暴露的主表面，从第二主表面向内延伸的多个第二凹槽。 多个第一金属互连图案被嵌入在多个第一凹部中并沿着第一主表面沿一个或多个方向延伸。 多个第二金属互连图案被嵌入在多个第二凹部中并沿着第二主表面沿一个或多个方向延伸。 多个非中空金属柱在多个第一金属互连图案中的至少一些和多个第二金属互连图案中的至少一些之间延伸穿过介质元件。