公开(公告)号：US06622380B1

公开(公告)日：2003-09-23

申请号：US10076169

申请日：2002-02-12

Applicant: Ford B. Grigg

Inventor： Ford B. Grigg

IPC: H05K334

CPC classification number: H05K3/3436 ,  H01L2224/4824 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/14 ,  H05K3/3452 ,  H05K3/3478 ,  H05K3/3489 ,  H05K2201/09472 ,  H05K2201/0989 ,  H05K2201/10977 ,  H05K2203/0195 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/0537 ,  H05K2203/058 ,  Y02P70/613 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Packaged microelectronic devices, methods of manufacturing packaged microelectronic devices, and method of mounting packaged microelectronic devices to printed circuit boards. One embodiment can include a die, an interposer substrate, a solder-ball, and a dielectric compound. The die can have an integrated circuit and at least one bond-pad coupled to the integrated circuit. The interposer substrate is coupled to the die and can have at least one ball-pad electrically coupled to the bond-pad on the die. The interposer substrate can also have a trace line adjacent to the ball-pad, and a solder-mask having an opening over the ball-pad. The solder-ball can contact the ball-pad in the opening. The dielectric compound can insulate the ball-pad and the solder-ball from an exposed portion of the adjacent trace line in the opening.

Abstract translation: 封装的微电子器件，制造封装的微电子器件的方法以及将封装的微电子器件安装到印刷电路板的方法。 一个实施例可以包括管芯，插入器衬底，焊球和电介质化合物。 芯片可以具有集成电路和耦合到集成电路的至少一个接合焊盘。 插入器基板耦合到管芯并且可以具有至少一个电焊接到管芯上的焊盘的球焊盘。 插入器基板还可以具有与球垫相邻的迹线，以及在球垫上具有开口的焊接掩模。 焊球可以接触开口中的球垫。 电介质化合物可以使球垫和焊球与开口中的相邻轨迹线的暴露部分绝缘。

公开(公告)号：US06543676B2

公开(公告)日：2003-04-08

申请号：US09873616

申请日：2001-06-04

Applicant: I-Chung Tung ,  Shih-Ping Hsu

Inventor： I-Chung Tung ,  Shih-Ping Hsu

IPC: B23K3102

CPC classification number: H05K3/3421 ,  H01L21/4853 ,  H01L23/49811 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/1532 ,  H01L2924/181 ,  H05K3/3426 ,  H05K3/3452 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/0989 ,  H05K2201/10318 ,  H05K2201/10787 ,  Y02P70/613 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A pin attachment method for mounting the pins on a wiring substrate for fabricating a pin grid array package is disclosed. There is provided an organic wiring board including a surface bearing electrical circuitry which includes at least one contact pad for receiving a pin. A solder mask layer which is placed on the board surface and patterned to expose the pad. The solder mask layer which does not cover any portion of the pad and forms a well by the perimeter of the solder mask layer around the pad. Subsequently, a pin and a solder material which are placed over said pad in the well. The pin which is soldered to the pad by a temperature sufficient to melt the solder material.

公开(公告)号：US06541711B1

公开(公告)日：2003-04-01

申请号：US09576112

申请日：2000-05-22

Applicant: David J. Dube ,  Frederic Kozak

Inventor： David J. Dube ,  Frederic Kozak

IPC: H01R1204

CPC classification number: H05K1/0219 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/162 ,  H05K3/3421 ,  H05K2201/09472 ,  H05K2201/09672 ,  H05K2201/09781 ,  H05K2201/09809 ,  H05K2201/10356

Abstract: A circuit board apparatus for terminating shielded conductors having multiple different ground potential values is disclosed. In a signal interconnection region, a multi-layer laminated circuit board comprises a shield termination layer that is capacitively coupled to a separate ground reference layer by a dielectric layer. A signal layer is electrically isolated from both the ground reference layer and shield termination layer by a substrate. A shield of a shielded cable terminates at the shield termination layer of the interconnect region, and a signal conductor of the cable terminates at the signal layer. Buried capacitance is developed between the shield termination layer and the ground reference layer. As a result, RF emissions are minimized and an electrically safe termination of multiple ground sources is provided, without enlarging the surface area of an interconnection. In the specific context of E1/E3 equipment, buried capacitance may be incorporated into the back plane printed circuit board of a unit of telecommunications equipment. As a result, port density may be increased, while maintaining simplicity. The value of the capacitance can be varied by increasing or decreasing the physical area of the plane referenced to the shield of the cable through the connector.

Abstract translation: 公开了一种用于终止具有多个不同接地电位值的屏蔽导体的电路板装置。 在信号互连区域中，多层层叠电路板包括通过电介质层电容耦合到单独的接地参考层的屏蔽端接层。 信号层通过衬底与接地参考层和屏蔽端接层电隔离。 屏蔽电缆的屏蔽终止在互连区域的屏蔽端接层处，并且电缆的信号导体终止于信号层。 掩蔽电容在屏蔽端接层和接地参考层之间产生。 结果，RF辐射被最小化，并且提供了多个接地源的电安全终端，而不增加互连的表面积。 在E1 / E3设备的具体情况下，埋地电容可以并入到电信设备单元的背板印刷电路板中。 结果，端口密度可以增加，同时保持简单性。 电容的值可以通过增加或减小通过连接器参考电缆屏蔽的平面的物理面积来改变。

公开(公告)号：US06511347B2

公开(公告)日：2003-01-28

申请号：US09894496

申请日：2001-06-28

Applicant: Brian D. Chapman ,  Wai Mon Ma

Inventor： Brian D. Chapman ,  Wai Mon Ma

IPC: H01R1373

CPC classification number: H05K3/4046 ,  H01L2224/45147 ,  H01L2224/48235 ,  H01L2224/4899 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19107 ,  H05K1/0298 ,  H05K1/114 ,  H05K3/225 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/10734 ,  H05K2203/049 ,  H01L2924/00014

Abstract: This invention relates to electrically connecting a first electronic component to a second electronic component wherein at least one of the electronic components must undergo modifications or repair when, for example, there is a floating signal generated from the first electronic component which can cause problems in operation of the electronic component assembly. For this type assembly an opening is provided in the second electronic component proximate the site or sites to be electrically connected to the first electronic component, which opening extends to an internal plane of the second electronic component desired to be connected to the first electronic component. A wire having a melting point higher than the solder used to make the assembly is used to connect the internal plane of the second electronic component to the pad of the second electronic component which second electronic component is to be electrically connected to the first electronic component thereby avoiding a floating signal in the electronic component assembly.

Abstract translation: 本发明涉及将第一电子部件电连接到第二电子部件，其中当例如从第一电子部件产生的浮动信号可能导致操作问题时，电子部件中的至少一个必须进行修改或修理 的电子部件组件。 对于这种类型的组件，在第二电子部件中靠近电气连接到第一电子部件的部位设置开口，该开口延伸到期望连接到第一电子部件的第二电子部件的内部平面。 使用熔点高于用于制造组件的焊料的焊丝将第二电子部件的内平面连接到第二电子部件的电连接到第一电子部件的第二电子部件的焊盘，由此 避免电子部件组件中的浮动信号。

公开(公告)号：US20030013326A1

公开(公告)日：2003-01-16

申请号：US10194170

申请日：2002-07-12

Inventor： Allen Ronald Cox ,  Stephen Peter Legg ,  Neil Morris

IPC: H05K001/00

CPC classification number: G11B33/121 ,  H01R12/523 ,  H01R12/721 ,  H05K1/112 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2201/10704

Abstract: This invention relates to apparatus and a method for connecting a pin array and a circuit board. In particular, the invention relates to pin array connections used in connecting disk drives into disk drive enclosures. Connection is accomplished by using a multi-pinned plug connector which sequentially engages conductive surfaces at different levels within the receiving PCB. The plug connector is connected electrically at its opposing end to a second PCB.

公开(公告)号：US06506979B1

公开(公告)日：2003-01-14

申请号：US09570215

申请日：2000-05-12

Applicant: James G. Shelnut ,  Charles R. Shipley

Inventor： James G. Shelnut ,  Charles R. Shipley

IPC: H05K102

CPC classification number: H05K3/465 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/205 ,  H05K3/3473 ,  H05K3/423 ,  H05K3/4682 ,  H05K2201/09472 ,  H05K2203/0152 ,  H05K2203/0338 ,  H05K2203/0726 ,  H05K2203/0733

Abstract: A method for manufacture of a circuit board and the board formed by the novel method. The method comprises selective plating of metallic reinforcing members, solder mount pads, signal lines and interconnections sequentially. The resultant board is desirably free of glass fiber reinforcement.

Abstract translation: 一种用于制造电路板和通过该方法形成的板的方法。 该方法包括依次选择性地镀金属加强件，焊接垫，信号线和互连。 所得板最好不含玻璃纤维增​​强层。

公开(公告)号：US20020175410A1

公开(公告)日：2002-11-28

申请号：US10193394

申请日：2002-07-11

Inventor： Johnny Cheng ,  Joyce Hsu

IPC: H01L029/40

CPC classification number: H01L21/486 ,  H01L23/49816 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/3457 ,  H05K3/423 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2203/041 ,  H05K2203/0733 ,  H01L2924/00014

Abstract: Typically, primary electrical connection between a semiconductor chip and an external solder ball contact on a Ball Grid or Chip Scale Package is by way of a via extending through a dielectric substrate. The aspect ratio between via diameter and depth is critical for reliable and high yield solder ball attachment during printed circuit board assembly. Excellent ball adherence and reliability of BGA solder ball contacts is achieved through controlling the aspect ratio of the substrate vias by partially plating a solid solderable conductor core in each via. An improved via structure is disclosed wherein the depth of the via is reduced without the negative effects of alternate methods, such as thinner substrates, or wider vias.

Abstract translation: 通常，球栅或芯片级封装上的半导体芯片和外部焊球接触之间的主电连接是通过延伸穿过电介质衬底的通孔。 通孔直径和深度之间的纵横比对于在印刷电路板组装过程中可靠且高产量的焊球附着至关重要。 BGA焊球接触的良好的球粘附性和可靠性通过在每个通孔中部分镀覆可固化的可焊接导体芯来控制衬底通孔的纵横比来实现。 公开了一种改进的通孔结构，其中通孔的深度减小而没有替代方法的负面影响，例如较薄的衬底或较宽的通孔。

公开(公告)号：US06485814B1

公开(公告)日：2002-11-26

申请号：US09513162

申请日：2000-02-25

Applicant: Kiyokazu Moriizumi ,  Mikio Nishihara

Inventor： Kiyokazu Moriizumi ,  Mikio Nishihara

IPC: B32B300

CPC classification number: H01L23/49811 ,  H01L2224/1147 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/16152 ,  H05K1/0306 ,  H05K3/4038 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0305 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10318 ,  H05K2203/1581 ,  Y10T428/24926 ,  H01L2224/0401

Abstract: To provide electrical conduction between front and back surfaces of a thin film multi-layered circuit board, such as an MCM, at low cost without using a simultaneous firing process for ceramic. The thin film multi-layered circuit board has at least one thin film circuit layer on a first surface of a substrate, wherein a conductor layer is disposed in the lowermost layer of the thin film circuit layer in contact with the first surface of the substrate, and is characterized in that holes for providing the electrical conduction between front and back surfaces of the substrate are formed through the substrate from the first surface to a second surface thereof so that the conductor layer is exposed in the hole, wherein the diameter of the hole is gradually enlarged from the first surface to the second surface.

Abstract translation: 以低成本提供薄膜多层电路板（例如MCM）的前后表面之间的导电，而不需要使用陶瓷的同时烧制工艺。 薄膜多层电路板在基板的第一表面上具有至少一个薄膜电路层，其中导体层设置在与基板的第一表面接触的薄膜电路层的最下层中， 并且其特征在于，通过基板从基板的第一表面到第二表面形成用于提供基板的前表面和后表面之间的导电的孔，使得导体层暴露在孔中，其中孔的直径 从第一表面逐渐增大到第二表面。

公开(公告)号：US06483669B1

公开(公告)日：2002-11-19

申请号：US09397448

申请日：1999-09-17

Applicant: Todd A. Krinke

Inventor： Todd A. Krinke

IPC: G11B548

CPC classification number: G11B5/48 ,  G11B5/127 ,  G11B5/4833 ,  G11B5/484 ,  G11B5/486 ,  H01L23/5387 ,  H01L2224/16237 ,  H01L2924/00014 ,  H05K1/056 ,  H05K1/112 ,  H05K1/189 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10674 ,  Y10T29/49027 ,  Y10T29/49028 ,  Y10T29/4903 ,  Y10T29/49032 ,  Y10T29/49041 ,  Y10T29/49043 ,  Y10T29/49044 ,  Y10T29/49149 ,  Y10T29/49156 ,  Y10T29/49169 ,  H01L2224/0401

Abstract: An integrated lead suspension or flexure having an integrated circuit (IC) mounting region on which an IC chip with an array of solder-covered terminals can be mounted. The suspension or flexure include a stainless steel layer, integrated conductive leads and an insulating layer between the conductive leads and the stainless steel layer. The stainless steel layer has an IC window for receiving an array of terminals of an IC. The integrated conductive leads extend along the stainless steel layer into the IC window, and include an array of bond pads in the IC window corresponding to the array of terminals of the IC to be mounted to the suspension or flexure. The insulating layer extends into the IC window and includes an array of solder mask holes corresponding to the array of conductive lead bond pads. The IC chip can thereby be mounted to the suspension or flexure in the IC window and its array of terminals soldered to the corresponding array of conductive lead bond pads through the array of solder mask holes.

Abstract translation: 具有集成电路（IC）安装区域的集成引线悬架或挠曲件，可安装具有焊料覆盖端子阵列的IC芯片。 悬挂或挠曲包括不锈钢层，集成导电引线和导电引线与不锈钢层之间的绝缘层。 不锈钢层具有用于接收IC的端子阵列的IC窗口。 集成导电引线沿着不锈钢层延伸到IC窗口中，并且包括在IC窗口中的对应于要安装到悬架或挠曲件的IC的端子阵列的接合焊盘阵列。 绝缘层延伸到IC窗口中，并且包括对应于导电引线接合焊盘阵列的焊接掩模孔阵列。 因此，IC芯片可以安装在IC窗口中的悬挂或弯曲处，并且其阵列的端子通过焊接掩模孔的阵列焊接到相应的导电引线接合焊盘阵列。

公开(公告)号：US06460773B1

公开(公告)日：2002-10-08

申请号：US09660946

申请日：2000-09-13

Applicant: Hiroshi Kaiya ,  Toshiyuki Honda

Inventor： Hiroshi Kaiya ,  Toshiyuki Honda

IPC: G06K1906

CPC classification number: G06K19/07747 ,  G06K19/07745 ,  G06K19/07749 ,  G06K19/07769 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/48465 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/182 ,  H05K3/321 ,  H05K3/3436 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/10477 ,  H05K2201/10666 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A module of a combination card can be incorporated into a card body with solder being easily melted, and heat transmission to portions other than the antenna connection terminals is reduced. A card body is provided with an antenna. The module includes a substrate which has a terminal surface on which at least one external connection terminal is formed and a mounting surface opposite to the terminal surface. An IC chip is mounted on the mounting surface. The module includes at least one antenna connection terminal located on the mounting surface. The antenna connection terminal is connected to the antenna, and at least a part of the antenna connection terminal is exposed on the terminal surface.

Abstract translation: 组合卡的模块​​可以结合到卡体中，焊料容易熔化，并且减少对天线连接端子以外的部分的热传递。 卡体设有天线。 该模块包括具有端子表面的基板，至少一个外部连接端子形成在该端子表面和与端子表面相对的安装表面。 IC芯片安装在安装面上。 该模块包括位于安装表面上的至少一个天线连接端子。 天线连接端子连接到天线，天线连接端子的至少一部分露出在端子表面上。