公开(公告)号：US20080006439A1

公开(公告)日：2008-01-10

申请号：US11858740

申请日：2007-09-20

Applicant: Kok-Siang Ng ,  King Keong Wong ,  Michael Ryan

Inventor： Kok-Siang Ng ,  King Keong Wong ,  Michael Ryan

IPC: H05K1/00 ,  H05K3/10

CPC classification number: H05K1/0245 ,  H05K1/0224 ,  H05K1/0237 ,  H05K1/0253 ,  H05K2201/09236 ,  H05K2201/09681 ,  H05K2201/0969 ,  Y10T29/49155

Abstract: A component having reference layer openings to contribute towards achieving a differential impedance in a circuit, is described herein.

Abstract translation: 这里描述了具有参考层开口以有助于实现电路中的差分阻抗的部件。

公开(公告)号：US07304858B2

公开(公告)日：2007-12-04

申请号：US11023489

申请日：2004-12-29

Applicant: Akiyoshi Saitou

Inventor： Akiyoshi Saitou

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K1/0233 ,  H05K1/0215 ,  H05K1/0224 ,  H05K1/18 ,  H05K3/429 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/0969 ,  H05K2201/1003 ,  H05K2201/1006 ,  H05K2201/10189 ,  H05K2201/10409

Abstract: A printed circuit board has separate first, second and third sections arranged in a predetermined direction. A connector is mounted at the first section. A noise cut filter is mounted at the second section and connected to the connector. An electronic circuit component is mounted at the third section and connected to the noise cut filter. An electrically conductive power source layer is formed within the printed circuit board at a position outside a peripheral section adjacent the second section. The noise cut filter is allowed to operate without receiving any influence of noise from the power source layer. Noise is sufficiently removed at the noise cut filter. Noise is suppressed to the utmost in electric signals in the connector. Radiation of noise is reliably reduced at the connector. Electromagnetic interference can be suppressed.

Abstract translation: 印刷电路板具有沿预定方向布置的单独的第一，第二和第三部分。 连接器安装在第一部分。 噪声截止滤波器安装在第二部分并连接到连接器。 电子电路部件安装在第三部分并连接到噪声截止滤波器。 在印刷电路板的与第二部分相邻的周边部分外的位置处形成导电电源层。 允许噪声抑制滤波器工作，而不会受到来自电源层的噪声的任何影响。 噪声在噪音截止滤波器上被充分去除。 连接器中的电信号最大限度地抑制噪声。 连接器可靠地降低噪声辐射。 可以抑制电磁干扰。

公开(公告)号：US20070272437A1

公开(公告)日：2007-11-29

申请号：US11802758

申请日：2007-05-24

Applicant: Takeshi Kondo

Inventor： Takeshi Kondo

IPC: H05K1/16

CPC classification number: H05K1/111 ,  H01L23/49811 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/3511 ,  H05K3/3452 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611

Abstract: In a printed board having a wiring pattern and an NSMD type land, the present invention prevents disconnection between the land and the wiring pattern and separation of the land from the printed board. The printed circuit board has a main wiring pattern, a protective film covering the main wiring pattern and having an opening formed therein, and a land located inside of the opening of the protective film so that the land is spaced from a circumferential edge of the opening of the protective film. The printed circuit board also has an auxiliary wiring pattern including a first auxiliary wiring portion located under the protective film so as to surround the land and second auxiliary wiring portions radially extending from the land to the first auxiliary wiring portion.

Abstract translation: 在具有布线图案和NSMD型焊盘的印刷电路板中，本发明防止焊盘和布线图案之间的断开以及焊盘与印刷电路板的分离。 印刷电路板具有主布线图案，覆盖主布线图案并且具有形成在其中的开口的保护膜，以及位于保护膜的开口内部的平台，使得平台与开口的周边边缘间隔开 的保护膜。 印刷电路板还具有辅助布线图案，其包括位于保护膜下面的第一辅助布线部分，以围绕脊部和从脊部向第一辅助布线部分径向延伸的第二辅助布线部分。

公开(公告)号：US20070241764A1

公开(公告)日：2007-10-18

申请号：US11783999

申请日：2007-04-13

Applicant: Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

Inventor： Toshiki Naito ,  Tetsuya Ohsawa ,  Kouji Kataoka

IPC: G01R31/02

CPC classification number: H05K1/0269 ,  H05K1/056 ,  H05K3/0052 ,  H05K3/225 ,  H05K2201/0909 ,  H05K2201/09127 ,  H05K2201/0969 ,  H05K2201/09781 ,  Y10T29/4913 ,  Y10T29/49131 ,  Y10T29/49133 ,  Y10T29/53022 ,  Y10T29/53026 ,  Y10T29/5303 ,  Y10T29/53035 ,  Y10T29/53039 ,  Y10T29/53043

Abstract: A wired circuit board assembly sheet has a plurality of wired circuit boards, distinguishing marks for distinguishing defectiveness of the wired circuit boards, and a supporting sheet for supporting the plurality of wired circuit boards and the distinguishing marks. Each of the distinguishing marks has an indication portion for indicating a specified one of the wired circuit boards.

Abstract translation: 布线电路板组装片具有多个布线电路板，用于区分布线电路板的缺陷的区别标记和用于支撑多个布线电路板和区别标记的支撑片。 每个识别标记具有用于指示指定的一个有线电路板的指示部分。

公开(公告)号：US07276668B2

公开(公告)日：2007-10-02

申请号：US10964619

申请日：2004-10-15

Applicant: Sheng-Yuan Lee ,  Ya-Chi Liao

Inventor： Sheng-Yuan Lee ,  Ya-Chi Liao

IPC: H05K1/03

CPC classification number: H05K1/025 ,  H05K1/0224 ,  H05K1/0231 ,  H05K1/111 ,  H05K1/181 ,  H05K2201/0792 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/10636 ,  Y02P70/611

Abstract: A circuit board with mounting pads is described for improving the frequency response of routing traces. The present invention is used to etch an etching hole on ground layer corresponding to the surface-mounted devices (SMD) on a routing layer and therefore the parasitic effect from the stray capacitor is reduced, resulting in eliminating the parasitic effect in high-frequency and raising the quality of the PCB as well.

Abstract translation: 描述了具有安装焊盘的电路板，用于改善路由迹线的频率响应。 本发明用于蚀刻对应于路由层上的表面安装器件（SMD）的接地层上的蚀刻孔，因此来自杂散电容器的寄生效应降低，从而消除了高频下的寄生效应， 提高PCB的质量。

公开(公告)号：US20070222052A1

公开(公告)日：2007-09-27

申请号：US11690482

申请日：2007-03-23

Applicant: Masanao Kabumoto

Inventor： Masanao Kabumoto

IPC: H01L23/02

CPC classification number: H01L23/50 ,  H01L23/49822 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/093 ,  H05K2201/0969 ,  H01L2924/00

Abstract: A wiring structure includes a general signal line, a differential signal line having a pair of signal wiring lines and a reference potential layer. The signal wiring lines respectively transmit differential signals of which waveforms are inverted from each other. The reference potential layer is arranged to have a distance from the general signal line and the differential signal line, and has a non-formed portion in a region to be electromagnetically coupled to the differential signal line.

Abstract translation: 布线结构包括通用信号线，具有一对信号布线和参考电位层的差分信号线。 信号线分别发送波形彼此反转的差分信号。 参考电位层被布置成与一般信号线和差分信号线具有一定距离，并且在要被电磁耦合到差分信号线的区域中具有非形成部分。

公开(公告)号：US20070215991A1

公开(公告)日：2007-09-20

申请号：US11308868

申请日：2006-05-17

Applicant: Chyh-Yih Chang ,  Kun-Hsien Tsai

Inventor： Chyh-Yih Chang ,  Kun-Hsien Tsai

IPC: H01L23/495

CPC classification number: H05K1/0218 ,  H01L21/563 ,  H01L23/49838 ,  H01L23/4985 ,  H01L23/552 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H05K1/111 ,  H05K1/189 ,  H05K2201/0373 ,  H05K2201/0969 ,  H05K2201/09772 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A tape with a chip-bonding area is provided. The tape is suitable for a chip on film configuration, wherein a chip is suitable for being disposed on the tape and in the chip-bonding area. The tape includes a dielectric base film, a first wiring pattern, and at least a second wiring pattern. The first wiring pattern is disposed on the dielectric base film and has multiple inner leads disposed in the chip-bonding area. The second wiring pattern is disposed on the dielectric base film and in the chip-bonding area. The chip is suitable for being electrically connected to at least a part of the inner leads and being disposed above the second wiring pattern.

Abstract translation: 提供具有芯片接合区域的带。 该胶带适用于胶片配置的芯片，其中芯片适于布置在胶带和芯片粘合区域中。 带包括电介质基底膜，第一布线图案和至少第二布线图案。 第一布线图案设置在电介质基底膜上，并且具有设置在芯片接合区域中的多个内部引线。 第二布线图案设置在电介质基底膜和芯片接合区域中。 该芯片适用于与至少一部分内引线电连接并设置在第二布线图案之上。

公开(公告)号：US20070194434A1

公开(公告)日：2007-08-23

申请号：US11443764

申请日：2006-05-30

Applicant: Chin-Sung Lin ,  Hsing-Chou Hsu

Inventor： Chin-Sung Lin ,  Hsing-Chou Hsu

IPC: H01L23/12

CPC classification number: H01L23/49822 ,  H01L23/66 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2924/01087 ,  H01L2924/3011 ,  H05K1/0237 ,  H05K1/0245 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/09236 ,  H05K2201/0969

Abstract: A wiring board including a plurality of patterned conductive layers and a plurality of insulating layers is provided. The patterned conductive layers include a first patterned conductive layer and at least one second patterned conductive layer. The first patterned conductive layer has at least one pair of differential signal lines and the second patterned conductive layer has at least one non-wiring area. A projection of the pair of differential signal lines on the second patterned conductive layer at least partially overlaps the non-wiring area. In addition, the insulating layers are disposed between the adjacent patterned conductive layers respectively.

Abstract translation: 提供了包括多个图案化导电层和多个绝缘层的布线板。 图案化导电层包括第一图案化导电层和至少一个第二图案化导电层。 第一图案化导电层具有至少一对差分信号线，而第二图案化导电层具有至少一个非布线区域。 第二图案化导电层上的该对差分信号线的投影至少部分地与非布线区域重叠。 此外，绝缘层分别设置在相邻的图案化导电层之间。

公开(公告)号：US07259968B2

公开(公告)日：2007-08-21

申请号：US10437619

申请日：2003-05-14

Applicant: Mitchel E. Wright

Inventor： Mitchel E. Wright

IPC: H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K1/0298 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09972

Abstract: A multi-layer circuit board includes a first layer having at least first and second conductive traces of different widths and the same impedance. One of a first power plane and first ground plane has a void region such that the first conductive trace is spaced apart from the first power plane by a first thickness, and the second conductive trace is spaced apart from the first ground plane by a second, different thickness.

Abstract translation: 多层电路板包括具有不同宽度和相同阻抗的至少第一和第二导电迹线的第一层。 第一电力平面和第一接地平面中的一个具有空隙区域，使得第一导电迹线与第一电力平面间隔第一厚度，并且第二导电迹线与第一接地平面间隔开第二导电迹线， 不同厚度。

公开(公告)号：US20070167056A1

公开(公告)日：2007-07-19

申请号：US11332301

申请日：2006-01-17

Applicant: Ying-Chih Shen

Inventor： Ying-Chih Shen

IPC: H01R13/62

CPC classification number: H05K3/4638 ,  H05K1/0268 ,  H05K2201/0969 ,  H05K2201/09781

Abstract: A method for detecting errors in laminating order of layers of a multi-layer printed circuit board, includes: preparing a multi-layer printed circuit board including a plurality of conductive layers and a plurality of dielectric layers disposed alternately with the conductive layers; defining a conductive line, a conductive reference surface, and a through-hole on three adjacent ones of the conductive layers in such a manner that the conductive line, the conductive reference surface, and the through-hole are aligned in a normal direction relative to the multi-layer printed circuit board; coupling a Time Domain Reflectometer (TDR) to the conductive line and the conductive reference surface so as to form a signal transmission line; and sending a pulsed signal into the conductive line through the TDR so as to measure characteristic impedance of the signal transmission line.

Abstract translation: 一种用于检测多层印刷电路板的层的层叠顺序的错误的方法，包括：制备包括多个导电层和与导电层交替设置的多个电介质层的多层印刷电路板; 在三个相邻的导电层之间限定导电线，导电基准表面和通孔，使得导电线，导电参考表面和通孔在正常方向上相对于 多层印刷电路板; 将时域反射计（TDR）耦合到导线和导电参考表面，以形成信号传输线; 并通过TDR向脉冲信号发送脉冲信号，以测量信号传输线的特性阻抗。