公开(公告)号：US5838546A

公开(公告)日：1998-11-17

申请号：US834163

申请日：1997-04-14

Applicant: Tadayoshi Miyoshi

Inventor： Tadayoshi Miyoshi

IPC: H01L21/60 ,  H01L23/495 ,  H01L25/04 ,  H01L25/16 ,  H01L25/18 ,  H05K1/14 ,  H05K1/18 ,  H05K3/00 ,  H05K1/16

CPC classification number: H05K1/184 ,  H01L23/49572 ,  H01L25/16 ,  H05K1/189 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/50 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15312 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/141 ,  H05K1/181 ,  H05K2201/0397 ,  H05K2201/0919 ,  H05K2201/10674 ,  H05K2201/10704 ,  H05K3/4691

Abstract: In a tape carrier package applying a TAB technique, a flex rigid PWB is used as a tape carrier. A flexible portion is provided with a semiconductor connection terminal. An LSI is directly mounted to the flexible portion. A rigid portion is provided with an electrode for mounting a component and an electrode for an external input/output.

Abstract translation: 在应用TAB技术的带载包装中，柔性刚性PWB用作带载体。 柔性部分设置有半导体连接端子。 LSI直接安装在柔性部分上。 刚性部分设置有用于安装部件的电极和用于外部输入/输出的电极。

公开(公告)号：US5614698A

公开(公告)日：1997-03-25

申请号：US374315

申请日：1995-01-17

Applicant: H. Scott Estes

Inventor： H. Scott Estes

IPC: H05K1/02 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0266 ,  H05K2201/0919 ,  H05K2201/09927 ,  H05K3/4641 ,  Y10T29/49124 ,  Y10T29/49155

Abstract: The substrate member of a multi-tier circuit board is provided, during the construction thereof, with an integral bar code structure by extending spaced apart, parallel finger sections of an interior metal ground plane portion of a panel structure outwardly past the routing path along which the substrate member is to be separated from the panel structure. After the substrate member is routed from the panel structure it has a peripheral side edge portion upon which exposed end surface portions of the spaced ground plane finger sections are disposed in a mutually spaced bar code array representative of predetermined information relating to the completed circuit board. The ground-seeking probe portion of a conductive scanning device is moved along the bar-coded edge of the substrate member to read and decipher the integral ground plane bar code structure compactly incorporated thereon during the manufacture of the substrate member.

Abstract translation: 多层电路板的基板构件在其构造期间通过将面板结构的内部金属接地平面部分的间隔开的平行指部分向外延伸穿过路径路径而设置在整个条形码结构中 衬底构件将与面板结构分离。 在基板构件从面板结构布线之后，其具有外围侧边缘部分，间隔开的接地平面指状部分的露出端表面部分布置在表示与完成的电路板有关的预定信息的相互间隔的条形码阵列中。 导电扫描装置的寻址探针部分沿着基板构件的条形边缘移动，以读取和解密在制造基板构件期间紧凑地结合在其上的整体接地平面条形码结构。

公开(公告)号：US5461201A

公开(公告)日：1995-10-24

申请号：US185605

申请日：1994-01-21

Applicant: Eduard Schonberger ,  Stefan Gruber ,  Hermann Kasowski ,  Heinz Schmidt

Inventor： Eduard Schonberger ,  Stefan Gruber ,  Hermann Kasowski ,  Heinz Schmidt

IPC: H01L23/28 ,  H01L23/34 ,  H05K1/00 ,  H05K1/02 ,  H05K7/20

CPC classification number: H05K7/205 ,  H05K1/0207 ,  H05K1/0209 ,  H05K1/0206 ,  H05K1/0284 ,  H05K2201/09118 ,  H05K2201/09163 ,  H05K2201/0919 ,  H05K2201/09781 ,  H05K2201/10416 ,  H05K2201/10969

Abstract: An insulating part for an electronic device includes a body having a metallized outer surface and a heat sink arranged within the body. The heat sink is thermally coupled to an electronic component and to the metallized outer surface, and may also be either electrically coupled or electrically isolated from the electronic component. The insulating part is preferably made of plastic by an injection-molding process, while the heat sink is preferably a metal block integrally formed within the insulating part.

Abstract translation: 电子设备的绝缘部件包括具有金属化外表面的主体和布置在主体内的散热器。 散热器热耦合到电子部件和金属化的外表面，并且还可以与电子部件电耦合或电隔离。 绝缘部件优选通过注射成型工艺由塑料制成，而散热器优选地是在绝缘部件内整体形成的金属块。

公开(公告)号：US5092782A

公开(公告)日：1992-03-03

申请号：US648950

申请日：1991-02-01

Applicant: Brian S. Beaman

Inventor： Brian S. Beaman

IPC: H01R12/00 ,  H01R12/71 ,  H01R13/24 ,  H01R43/00 ,  H05K1/00 ,  H05K3/00 ,  H05K3/32 ,  H05K3/40 ,  H05K3/46

CPC classification number: H01R13/2414 ,  H01R12/714 ,  H01R43/007 ,  H05K3/326 ,  H05K3/4092 ,  H05K1/0298 ,  H05K2201/0133 ,  H05K2201/0397 ,  H05K2201/044 ,  H05K2201/0919 ,  H05K2201/10393 ,  H05K3/0017 ,  H05K3/4007 ,  Y10T29/49126

Abstract: An integral elastomeric card edge connector provides shorter signal paths through the contact with reduced interference. The card edge contact allows high density interconnection between several layers of multi-layer circuit card without routing signal paths to the card surface. Elastomeric contact tab supports provide positive contact pressure and the necessary wipe action to ensure electrical contact. The process for forming the integral contacts begins with a standard multi-layer card which is then beveled, etched to expose the contact tabs, filled with elastomeric material and processed to expose the tabs supported by elastomeric columns. The connector may be used in card on board technologies or for the connection of multi-chip organic substrates to boards or to other substrates.

公开(公告)号：US4908933A

公开(公告)日：1990-03-20

申请号：US344608

申请日：1989-04-28

Applicant: Katsumi Sagisaka ,  Atsushi Hiroi ,  Mitsuhiro Kondo ,  Takeshi Takeyama

Inventor： Katsumi Sagisaka ,  Atsushi Hiroi ,  Mitsuhiro Kondo ,  Takeshi Takeyama

IPC: H01L23/12 ,  H01L21/00 ,  H01L23/498 ,  H01L23/50 ,  H05K1/05 ,  H05K3/20 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: H01L21/67144 ,  H01L23/49861 ,  H05K3/4092 ,  H05K3/445 ,  H05K3/4641 ,  H01L2924/0002 ,  H05K1/056 ,  H05K2201/0352 ,  H05K2201/0397 ,  H05K2201/0919 ,  H05K2201/09754 ,  H05K2201/10924 ,  H05K2203/0264 ,  H05K3/202 ,  H05K3/427 ,  H05K3/429 ,  Y10T29/49121

Abstract: A method of manufacturing a substrate for mounting electronic components according to this invention comprises the steps of forming a mask on a portion to be electrically connected to an exterior of a lead frame, of forming resin layers on both side surfaces of the lead frame by prepregs or the like, of removing the resin layer on the mask, and of removing the mask, and in the substrate for mounting electronic components manufactured according to this method, the substrate is integrally formed with the lead frame, and the electrical connection of the substrate to the lead frame is performed by through hole plating without using fine metal wiring.

Abstract translation: 根据本发明的用于安装电子部件的基板的制造方法包括以下步骤：在引线框架的外部电连接的部分上形成掩模，通过预浸料在引线框架的两个侧表面上形成树脂层 等等，除去掩模上的树脂层和除去掩模，并且在用于安装根据该方法制造的电子部件的基板中，基板与引线框架一体地形成，并且基板的电连接 通过通孔电镀而不使用精细的金属布线来进行引线框。

公开(公告)号：US4879630A

公开(公告)日：1989-11-07

申请号：US239718

申请日：1988-09-01

Applicant: Michel Boucard ,  Christian Thirion ,  Christian Maurel

Inventor： Michel Boucard ,  Christian Thirion ,  Christian Maurel

IPC: H01L23/495 ,  H05K1/02 ,  H05K1/18 ,  H05K3/20 ,  H05K3/40 ,  H05K5/00 ,  H05K7/20

CPC classification number: H05K5/0091 ,  H01L23/49575 ,  H05K1/021 ,  H05K3/4092 ,  H05K7/20854 ,  H01L2224/48091 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K1/182 ,  H05K2201/0397 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2203/049 ,  H05K3/202

Abstract: The housing protects a circuit comprising active power components 10, 11, 12. A power electrode of the component 10 is welded onto the flush surface 15 of a radiator 13 accommodated in the base of the housing. The radiator is formed in one piece with an elongate part 14, the end 5 of which projects from the housing in the form of an external connecting pin. The radiator 13 may take various forms, including that of a grid.

Abstract translation: 壳体保护包括有源功率部件10,11,12的电路。组件10的功率电极被焊接到容纳在壳体的基座中的散热器13的齐平表面15上。 散热器与细长部件14形成为一体，其端部5以外部连接销的形式从外壳突出。 散热器13可以采取各种形式，包括电网的形式。

公开(公告)号：US4694123A

公开(公告)日：1987-09-15

申请号：US339034

申请日：1982-01-13

Applicant: Edwin M. Massey

Inventor： Edwin M. Massey

IPC: H02G5/00 ,  H05K1/02 ,  H05K3/42 ,  H05K3/46 ,  H01B7/08

CPC classification number: H02G5/005 ,  H05K3/4641 ,  H05K1/0263 ,  H05K2201/044 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09845 ,  H05K2201/10272 ,  H05K3/429

Abstract: A backplane power distribution system characterized by generally uniform current densities so as to be capable of handling very high levels of current. This is achieved with a stepped backplane construction. For example, in a system having, in order, a first conductive layer, a first dielectric layer, a second conductive layer, and a second dielectric layer, the second conductive and dielectric layers extend transversely beyond the first conductive and dielectric layers to present a substantial exposed area of the second conductive layer. Typically, a rectangular metal bus bar is bolted to the backplane to make contact with the exposed area, and power supply connections to the bus bar are made in any convenient manner.

Abstract translation: 背板配电系统，其特征在于具有大致均匀的电流密度，以便能够处理非常高水平的电流。 这是通过阶梯式背板结构实现的。 例如，在依次具有第一导电层，第一介电层，第二导电层和第二介电层的系统中，第二导电和介电层横向延伸超过第一导电层和介电层，以呈现 第二导电层的实质暴露面积。 通常，矩形金属母线被螺栓连接到背板以与暴露的区域接触，并且以任何方便的方式制造到母线的电源连接。

公开(公告)号：US4628411A

公开(公告)日：1986-12-09

申请号：US729831

申请日：1985-05-02

Applicant: Demetrios Balderes ,  Andrew J. Frankovsky ,  Robert A. Jarvela

Inventor： Demetrios Balderes ,  Andrew J. Frankovsky ,  Robert A. Jarvela

IPC: G06F1/18 ,  H05K1/02 ,  H05K3/46 ,  H05K5/00

CPC classification number: G06F1/189 ,  H05K1/0263 ,  H05K2201/0919 ,  H05K2201/10272 ,  H05K3/4641

Abstract: A direct module powering scheme is disclosed. A plurality of integrated circuit chips are mounted on a module. The module is mounted on a printed circuit board. A plurality of metallization layers are distributed in parallel fashion within the module. A voltage tab is mounted on the edge of the module substrate and in contact with the edge of the metallization layers. The voltage tab may be attached to a source of power for providing the necessary voltage and current to the module needed to power the chips mounted on the module. The metallization layers comprise voltage distribution layers and voltage reference (ground) layers. The voltage tab is connected to the edge of the voltage distribution layer. A plurality of plated vias are disposed through the module in contact with one or more of the metallization layers. A plurality of voltage distribution stripes are disposed on the bottom of the module substrate and in contact with the plated vias for providing the necessary voltage and current to remotely-located chips, relative to the voltage tab, needed to power the chips. The energizing current from the power source energizes the chips mounted on the module by way of the voltage tab, the voltage distribution layer, and a plated via. Alternatively, the energizing current from the power source energizes a remotely-located chip mounted on the module by way of the voltage tab, the voltage distribution layer, a plated via, a voltage distribution stripe, and another plated via connected to the remotely-located chip. As a result, the module is connected directly to the power source, rather than being connected to the power source by way of a plurality of power distribution planes disposed within the printed circuit board.

Abstract translation: 公开了一种直接模块供电方案。 多个集成电路芯片安装在模块上。 该模块安装在印刷电路板上。 多个金属化层在模块内以并行方式分布。 电压接头安装在模块基板的边缘上并与金属化层的边缘接触。 电压接头可以附接到电源上，以向安装在模块上的芯片供电所需的模块提供必要的电压和电流。 金属化层包括电压分布层和电压参考（接地）层。 电压接头连接到电压分布层的边缘。 多个电镀通孔通过模块设置成与一个或多个金属化层接触。 多个电压分布条被布置在模块基板的底部并与电镀通孔接触，以便为相对于电压片提供必要的电压和电流至相对于电压片供电所需的芯片。 来自电源的激励电流通过电压接头，电压分布层和电镀通孔激励安装在模块上的芯片。 或者，来自电源的激励电流通过电压接头，电压分配层，电镀通孔，电压分配条和连接到远程位置的另一个电镀通孔来激励安装在模块上的远程定位的芯片 芯片。 结果，模块直接连接到电源，而不是通过布置在印刷电路板内的多个配电平面连接到电源。

公开(公告)号：US4383270A

公开(公告)日：1983-05-10

申请号：US167367

申请日：1980-07-10

Applicant: Robert L. Schelhorn

Inventor： Robert L. Schelhorn

IPC: H01L23/14 ,  H01L23/36 ,  H05K1/02 ,  H05K1/05 ,  H05K1/09 ,  H05K3/34 ,  H05K7/20 ,  H01L23/48 ,  H01L23/02

CPC classification number: H05K1/0207 ,  H01L23/142 ,  H01L23/36 ,  H01L2224/16 ,  H01L2924/3025 ,  H05K1/0206 ,  H05K1/053 ,  H05K1/092 ,  H05K2201/09054 ,  H05K2201/0919 ,  H05K2201/10416 ,  H05K2201/10674 ,  H05K2201/10969 ,  H05K2203/0733 ,  H05K3/341

Abstract: A porcelain coated steel substrate for receiving thick film printed circuit thereon includes thermally and electrically conductive pedestals which are in thermal and electrical contact with the steel core. The pedestal surface is coplanar with the porcelain coating so that a substantially continuous plane surface is present. This permits semiconductor chips readily to be mounted on the substrate, the pedestals serving as heat and electrical conductors to the substrate, and serves also to facilitate the deposition of thick film elements.

Abstract translation: 用于在其上接收厚膜印刷电路的瓷涂层钢基材包括与钢芯热和电接触的导热导电基座。 基座表面与瓷器涂层共面，从而存在基本上连续的平面。 这允许半导体芯片容易地安装在基板上，基座用作热和电导体到基板，并且还用于促进厚膜元件的沉积。

公开(公告)号：US4372045A

公开(公告)日：1983-02-08

申请号：US233425

申请日：1981-02-11

Applicant: Pol A. G. J. Gustin ,  Raymond G. G. Schayes

Inventor： Pol A. G. J. Gustin ,  Raymond G. G. Schayes

IPC: B41J2/395 ,  H05K3/00 ,  H05K3/40 ,  H05K3/46

CPC classification number: B41J2/395 ,  H05K3/403 ,  H05K2201/0379 ,  H05K2201/0919 ,  H05K3/0052 ,  H05K3/4614 ,  Y10T29/49155

Abstract: A method of manufacturing an electrostatic write head comprises an insulating plate-shaped substrate having conductor tracks which extend as parallel conductor tracks in a strip-shaped region on the substrate. The substrate is divided into two plates along a dividing line which extends in the strip-shaped region, perpendicularly to the conductor strips. The two plates are subsequently joined so that their sides provided with conductor tracks face each other.

Abstract translation: 一种制造静电写入头的方法包括：绝缘板状基板，其具有在基板上的带状区域中作为平行导体轨迹延伸的导体轨迹。 基板沿着沿带状区域垂直于导体条延伸的分割线分成两个板。 两个板随后连接成使得它们的侧面设置有导体轨迹彼此面对。