公开(公告)号：US20020182903A1

公开(公告)日：2002-12-05

申请号：US10195865

申请日：2002-07-15

Inventor： Naoto Ishida ,  Kouji Asano

IPC: H01R012/00

CPC classification number: H01L23/49827 ,  H01L23/49816 ,  H01L23/49833 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/49109 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12033 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15173 ,  H01L2924/15312 ,  H01L2924/1532 ,  H05K3/308 ,  H05K3/3426 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/09481 ,  H05K2201/10234 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10666 ,  H05K2201/10871 ,  Y02P70/613 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/85399

Abstract: A printed wiring board has a circuit substrate 6 having a conductor circuit 5 and a through hole 60, and also has a joining pin 1 inserted into the through hole. The joining pin is manufactured by using a material unmelted at a heating temperature in joining the joining pin to an opposite party pad 81. The joining pin is constructed by a joining head portion 11 greater than an opening diameter of the through hole and forming a joining portion to the opposite party pad, and a leg portion 12 having a size capable of inserting this leg portion into the through hole. The leg portion is inserted into the through hole and is joined to the through hole by a conductive material such as a soldering material 20, etc. A joining ball approximately having a spherical shape instead of the joining pin can be also joined to the through hole by the conductive material.

Abstract translation: 印刷电路板具有电路基板6，电路基板6具有导体电路5和通孔60，并且还具有插入到通孔中的接合销1。 接合销通过使用在加热温度下未熔化的材料来制造，所述材料将接合销接合到相对方垫81.接合销由大于通孔的开口直径的接合头部11构成，并形成接合 以及具有能够将该腿部插入通孔的尺寸的腿部12。 脚部插入到通孔中，并且通过诸如焊接材料20等的导电材料接合到通孔。大体上具有球形而不是接合销的接合球也可以连接到通孔 由导电材料制成。

公开(公告)号：US06400019B1

公开(公告)日：2002-06-04

申请号：US09708597

申请日：2000-11-09

Applicant: Toshinori Hirashima ,  Yasushi Takahashi ,  Kenji Hanada ,  Takao Sonobe

Inventor： Toshinori Hirashima ,  Yasushi Takahashi ,  Kenji Hanada ,  Takao Sonobe

IPC: H01L2348

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05022 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05171 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/0558 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H05K1/0243 ,  H05K1/0263 ,  H05K1/111 ,  H05K2201/094 ,  H05K2201/09481 ,  H05K2201/0949 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2224/05655 ,  H01L2924/013

Abstract: The junction strength between the external terminals and the wiring substrate of a semiconductor device is improved without creating a large size semiconductor device. In the outer periphery of the back surface of an interposer substrate 1Bi on which a semiconductor chip constructing a CSP type semiconductor device 1 is mounted, there are arranged a plurality of bump electrodes 1BB1 whose size in the direction intersecting the sides of the interposer substrate 1B1 is larger than that in the direction along the sides of the interposer substrate 1Bi.

Abstract translation: 在不产生大尺寸半导体器件的情况下，可以提高外部端子与半导体器件的布线基板之间的结合强度。 在其上安装有构成CSP型半导体器件1的半导体芯片的插入件基板1Bi的背面的外周，布置有多个凸起电极1BB1，该突起电极1BB1在与插入件基板1B1的侧面相交的方向上的尺寸 大于沿着插​​入件基板1Bi的侧面方向的尺寸。

公开(公告)号：US06359337B1

公开(公告)日：2002-03-19

申请号：US09407151

申请日：1999-09-28

Applicant: Ronald Keukelaar ,  Leonard Nanis

Inventor： Ronald Keukelaar ,  Leonard Nanis

IPC: H01L2348

CPC classification number: G01R1/06761 ,  G01R3/00 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0104 ,  H01L2924/01041 ,  H01L2924/01042 ,  H01L2924/01044 ,  H01L2924/01045 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K3/241 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0209 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H01L2924/00

Abstract: An improved wear resistant bump contact is produced by the inclusion of small particles of hard materials in the conductive material of the contact bump, preferably by co-deposition at the time of electroplating of the bump bulk material. Desirable attributes of the small particles of hard material include small particle size, hardness greater than the hardness of the bulk material of the contact bump, compatibility with the plating conditions, and electrical conductivity. Nitride, borides, silicides, carbides are typical interstitial compounds suitable for use in satisfying these desirable attributes. In one preferred example, a nickel bulk material and silicon carbide particles are utilized. In one variation, the bump of metal-particle co-deposited material is coated by a thin cap layer of noble, non-oxidizing metal to prevent electrical erosion by arcing as contact is made and broken from the pad. Rhodium and ruthenium are suitable metals and can be electrodeposition over the composite bump structure.

Abstract translation: 通过在接触凸块的导电材料中包含硬质材料的小颗粒，优选通过在凸块块状材料的电镀时共沉积来制造改进的耐磨凸点接触。 硬质材料的小颗粒的理想特性包括小的颗粒尺寸，硬度大于接触凸块的散装材料的硬度，与电镀条件的兼容性和导电性。 氮化物，硼化物，硅化物，碳化物是适合用于满足这些所需属性的典型间隙化合物。 在一个优选实施例中，使用镍本体材料和碳化硅颗粒。 在一个实施例中，金属 - 颗粒共沉积材料的凸起由贵金属非氧化金属的薄盖层涂覆，以防止由于接触而从焊盘断开而导致电弧侵蚀。 铑和钌是合适的金属，可以电沉积在复合凸块结构上。

公开(公告)号：US20020031921A1

公开(公告)日：2002-03-14

申请号：US09902262

申请日：2001-07-11

Inventor： Toshio Okuno ,  Etsuji Suzuki

IPC: H05K001/00

CPC classification number: G01R1/06755 ,  G01R1/0735 ,  G01R3/00 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2203/0113 ,  H05K2203/0338 ,  Y10T29/49128

Abstract: To provide a contact structure of a lead in which a contract structure having a lead and a bump made of suitable metals, respectively, is formed easily and in which the bump and the lead are soundly connected together in terms of electricity and strength. A contact structure of a lead comprising a lead 12 formed by etching a conductive foil 11, a bump 5 formed by electric casting by means of plating, the bump 5 and the lead 12 being formed of different metals, respectively, the bump 5 being connected to a surface of the lead 12 through a conductive connecting material 10, the lead 12 being intimately contacted at a surface, on which the bump 5 is disposed, with a first main surface 15 of a holeless insulative sheet 8, a basal portion of the bump 5 being forcibly pierced into and extended all the way through the thickness of a material of the holeless insulative sheet 8 and a side surface of the basal portion of the bump 5 being fusion-adhered to an inner wall surface of the through-hole 17, and a distal portion of the bump 5 being projected from a second main surface 16 of the insulative sheet 8.

Abstract translation: 为了提供一种铅的接触结构，其中容易地形成具有由合适的金属制成的引线和凸块的接合结构，并且凸起和引线在电力和强度方面牢固地连接在一起。 引线的接触结构包括通过蚀刻导电箔11形成的引线12，通过电镀电铸形成的凸块5，凸块5和引线12分别由不同的金属形成，凸块5被连接 通过导电连接材料10到引线12的表面，引线12在其上设置有凸起5的表面与无孔绝缘片8的第一主表面15紧密接触，基底部分 突起5被强制地穿透并延伸穿过无孔绝缘片8的材料的厚度，并且凸起5的基部的侧表面被熔融粘附到通孔17的内壁表面 并且凸起5的远端部分从绝缘片8的第二主表面16突出。

公开(公告)号：US06350365B1

公开(公告)日：2002-02-26

申请号：US09634783

申请日：2000-08-09

Applicant: Toshinori Koyama ,  Noritaka Katagiri

Inventor： Toshinori Koyama ,  Noritaka Katagiri

IPC: C25D502

CPC classification number: H01L21/486 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/15311 ,  H05K3/28 ,  H05K3/426 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09481 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/0959 ,  H05K2201/096 ,  H01L2224/0401

Abstract: A method of producing a multilayer circuit board comprising a core substrate and a plurality of layers of wiring lines on both sides of the core substrate with an insulation layer being interposed therebetween; the layers of wiring lines on both sides being interconnected by conducting members provided on the inside walls of through holes going through the core substrate, and the interposed insulation layer. The method further comprising, wiring lines with an upper layer of wiring lines wherein the conducting member on the inside wall of the through hole and the via are formed in separate steps. The method can provide a multilayer circuit board which can advantageously be used to mount a chip or device thereon having an increased number of electrodes or terminals.

Abstract translation: 一种制造多层电路板的方法，所述多层电路板包括芯基板和在芯基板的两侧上的多层布线，绝缘层被插入其间; 两侧的布线层由设置在穿过芯基板的通孔的内壁上的导电构件和插入的绝缘层互连。 所述方法还包括：布线与布线的上层，其中通孔的内壁上的导电构件和通孔分开形成。 该方法可以提供可以有利地用于安装其上具有增加数量的电极或端子的芯片或器件的多层电路板。

公开(公告)号：US06222272B1

公开(公告)日：2001-04-24

申请号：US09173683

申请日：1998-10-16

Applicant: Yoshinari Takayama ,  Kazuo Ouchi ,  Atsushi Hino

Inventor： Yoshinari Takayama ,  Kazuo Ouchi ,  Atsushi Hino

IPC: H01L2941

CPC classification number: H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/15174 ,  H01L2924/15184 ,  H01L2924/15311 ,  H05K3/0035 ,  H05K3/0055 ,  H05K3/423 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09745 ,  H05K2203/0369 ,  H05K2203/095 ,  H05K2203/1572 ,  H01L2924/00 ,  H01L2224/05599

Abstract: In a film carrier with a conductive circuit formed, an opening is formed in a particular position relative to where the conductive path is to be formed. The opening is a through-hole, filled with a conductive material to form a conductive path. The conductive circuit has a concave face, provided according to certain formulae. The film carrier can cope with a fine-pitched and highly dense mounting, while prohibiting pulling out of the conductive path by an external force. The film carrier does not suffer from fallout of the conductive path, and has increased electrical connection reliability.

Abstract translation: 在形成有导电电路的薄膜载体中，相对于要形成导电路径的特定位置形成开口。 开口是通孔，填充有导电材料以形成导电路径。 导电电路具有根据某些公式提供的凹面。 薄膜载体可以处理细调和高度密集的安装，同时禁止通过外力从导电路径拉出。 电影载体不会受到导电路径的影响，并且具有增加的电连接可靠性。

公开(公告)号：US06219908B1

公开(公告)日：2001-04-24

申请号：US08975553

申请日：1997-11-20

Applicant: Warren Farnworth ,  Alan Wood

Inventor： Warren Farnworth ,  Alan Wood

IPC: H05K330

CPC classification number: H01L23/49838 ,  G01R1/0433 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/06711 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2863 ,  G01R31/287 ,  G01R31/2889 ,  G01R31/2893 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L24/80 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  Y10T29/49117 ,  Y10T29/49121 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49131 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method and apparatus for fabricating known good semiconductor dice are provided. The method includes the steps of: testing the gross functionality of dice contained on a semiconductor wafer; sawing the wafer to singulate a die; and then testing the die by assembly in a carrier having an interconnect adapted to establish electrical communication between the bond pads on the die and external test circuitry. The interconnect for the carrier can be formed using different contact technologies including: thick film contact members on a rigid substrate; self-limiting contact members on a silicon substrate; or microbump contact members with a textured surface. During assembly of the carrier, the die and interconnect are optically aligned and placed into contact with a predetermined contact force. This establishes an electrical connection between the contact members on the interconnect and the bond pads of the die. In the assembled carrier the die and interconnect are biased together by a force distribution mechanism that includes a bridge clamp, a pressure plate and a spring clip. Following testing of the die, the carrier is disassembled and the tested die is removed.

Abstract translation: 提供了一种用于制造已知的良好半导体晶片的方法和装置。 该方法包括以下步骤：测试包含在半导体晶片上的骰子的总功能; 锯切晶片以切割模具; 然后通过组装在具有适于建立管芯上的接合焊盘与外部测试电路之间的电连通的互连的载体中来测试管芯。 用于载体的互连可以使用不同的接触技术形成，包括：刚性基板上的厚膜接触构件; 硅衬底上的自限制接触构件; 或具有纹理表面的微型块接触构件。 在载体的组装期间，芯片和互连件被光学对准并且被放置成与预定的接触力接触。 这就建立了互连上的接触构件和管芯的接合垫之间的电连接。 在组装的载体中，管芯和互连件通过包括桥夹，压板和弹簧夹的力分配机构偏压在一起。 在对模具进行测试之后，拆下载体并且移除被测试的模具。

公开(公告)号：US6020624A

公开(公告)日：2000-02-01

申请号：US53273

申请日：1998-04-01

Applicant: Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

Inventor： Alan G. Wood ,  Salman Akram ,  Warren M. Farnworth

IPC: G01R1/04 ,  G01R1/067 ,  G01R1/073 ,  G01R3/00 ,  G01R31/28 ,  H01L21/60 ,  H01L21/66 ,  H01L21/68 ,  H01L23/13 ,  H01L23/498 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H01L29/06 ,  H01L23/02 ,  H01L23/28

CPC classification number: H05K3/4007 ,  G01R1/0466 ,  G01R1/0483 ,  H01L21/6835 ,  H01L22/20 ,  H01L23/13 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/80 ,  H01L24/85 ,  G01R1/06738 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2863 ,  H01L2224/16145 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/73207 ,  H01L2224/85001 ,  H01L2224/85205 ,  H01L2225/06562 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15151 ,  H01L2924/15174 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30105 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/423

Abstract: A method for forming an interconnect for semiconductor devices is provided. The interconnect includes raised contact structures covered with a conductive layer and having penetrating projections for penetrating contacts for the semiconductor devices. In an illustrative embodiment, the interconnect can be used to form a bi-substrate die. An interconnect substrate for the bi-substrate die includes control and logic circuitry and a memory substrate for the bi-substrate die includes a memory array. The interconnect can also be used to establish an electrical connection to microscopic contacts formed on a conventional die. In addition, the interconnect can be formed with three dimensional micro structures for contacting the microscopic contacts. Still further, the interconnect can be formed as wafer interconnect for electrically contacting dice contained on a wafer or for stacking multiple wafers.

Abstract translation: 提供一种用于形成用于半导体器件的互连的方法。 互连包括被导电层覆盖的凸起的接触结构，并且具有用于穿透用于半导体器件的触点的穿透突起。 在说明性实施例中，互连可用于形成双衬底裸片。 用于双衬底裸片的互连衬底包括控制和逻辑电路，并且用于双衬底裸片的存储器衬底包括存储器阵列。 互连还可用于建立与常规裸片上形成的微观触点的电连接。 此外，互连可以由用于接触微观触点的三维微结构形成。 此外，互连可以形成为用于电接触包含在晶片上的骰子或用于堆叠多个晶片的晶片互连。

公开(公告)号：US6011310A

公开(公告)日：2000-01-04

申请号：US722321

申请日：1996-09-27

Applicant: Toshiki Naito ,  Kazuo Ouchi

Inventor： Toshiki Naito ,  Kazuo Ouchi

IPC: H01L21/60 ,  H01L23/498 ,  H01L23/50 ,  H05K3/40 ,  H05K3/42 ,  H01L23/48 ,  H01L23/053 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/81 ,  H01L23/4985 ,  H05K3/4007 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/1572 ,  H05K3/423

Abstract: Disclosed are a film carrier comprising an insulating layer having laid therein an electrically conductive circuit such that the circuit is not exposed on the surface thereof, wherein conductive passages from the conductive circuit to one surface of the insulating layer are formed in the insulating layer and via holes from said conductive circuit to the other surface of the insulating layer are formed and a semiconductor device prepared by mounting a semiconductor element on the insulating layer of the film carrier. The film carrier can sufficiently correspond to pitch-fining and high-density mounting of a semiconductor element wiring, can surely perform the connecting operation of inner lead bonding and outer lead bonding and gives the mounting area of as small as possible.

Abstract translation: 公开了一种薄膜载体，其包括绝缘层，其中放置有导电电路，使得该电路不在其表面上露出，其中从导电电路到绝缘层的一个表面的导电通道形成在绝缘层中，并且经由 形成从所述导电电路到绝缘层的另一表面的孔，以及通过将半导体元件安装在膜载体的绝缘层上而制备的半导体器件。 薄膜载体可以充分地对应于半导体元件布线的节距精细和高密度安装，可以可靠地执行内引线接合和外引线接合的连接操作，并且使安装面积尽可能小。

公开(公告)号：US5838549A

公开(公告)日：1998-11-17

申请号：US788423

申请日：1997-01-27

Applicant: Tatsuya Nagata ,  Hiroya Shimizu ,  Atsushi Nakamura ,  Hideshi Fukumoto ,  Toshio Sugano

Inventor： Tatsuya Nagata ,  Hiroya Shimizu ,  Atsushi Nakamura ,  Hideshi Fukumoto ,  Toshio Sugano

IPC: H05K3/46 ,  H01L27/10 ,  H05K1/02 ,  H05K1/11 ,  H05K3/42 ,  H01R9/09

CPC classification number: H05K1/117 ,  H01R12/721 ,  H05K1/0216 ,  H01R23/6873 ,  H05K1/0224 ,  H05K2201/0191 ,  H05K2201/09327 ,  H05K2201/09336 ,  H05K2201/09481 ,  H05K2201/09681 ,  H05K2201/0969 ,  H05K2201/10159 ,  H05K2201/10689 ,  H05K3/429 ,  Y10S439/941

Abstract: In semiconductor modules having a plurality of semiconductor devices mounted on a multilayer printed circuit boards as the processing speed increases, a short circuit current flowing through CMOS devices in the semiconductor devices during operation can cause noise because of ground inductance or power supply inductance. This noise can result in erroneous operations. To solve this problem, the power supply layer or grand layer that is connected to either the power supply terminal Vcc or the ground terminal Gnd of each semiconductor memory, which is located farther from the connection terminals, is arranged closer to the semiconductor memories with this arrangement, the short circuit current flowing through the semiconductor memories is more strongly magnetically coupled with the power supply layer or ground layer arranged close to them. Thus, it is possible to reduce the effective inductance. This, in turn, reduces noise, making it possible to provide a semiconductor module with an increased processing speed.

Abstract translation: 在处理速度增加时，具有安装在多层印刷电路板上的多个半导体器件的半导体模块中，在工作期间流过半导体器件中的CMOS器件的短路电流可能由于接地电感或电源电感而引起噪声。 这种噪音可能导致错误的操作。 为了解决这个问题，连接到距连接端子更远的每个半导体存储器的电源端子Vcc或接地端子Gnd的电源层或者大层被布置成更靠近半导体存储器 布置时，流过半导体存储器的短路电流与靠近它们布置的电源层或接地层更牢固地磁耦合。 因此，可以降低有效电感。 这反过来降低了噪声，使得可以提供具有增加的处理速度的半导体模块。