公开(公告)号：US07444727B2

公开(公告)日：2008-11-04

申请号：US11276688

申请日：2006-03-10

Applicant: Jovica Savic ,  Remy J. Chelini ,  Gregory J. Dunn

Inventor： Jovica Savic ,  Remy J. Chelini ,  Gregory J. Dunn

IPC: H01G7/00 ,  H01L21/20

CPC classification number: H01G4/33 ,  H01G4/12 ,  H05K1/162 ,  H05K3/0044 ,  H05K2201/0175 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2203/025 ,  Y10T29/417 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming embedded capacitors on a printed circuit board is disclosed. The capacitor is formed on the printed circuit board by a depositing a first dielectric layer over one or more electrodes situated on the PCB. Another electrode is formed on top of the first dielectric layer and a second dielectric layer is deposited on top of that electrode. A third electrode is formed on top of the second dielectric layer. The two dielectric layers are abrasively delineated in a single step by a method such as sand blasting to define portions of the first and second dielectric layers to create a multilayer capacitive structure.

Abstract translation: 公开了一种在印刷电路板上形成嵌入式电容器的方法。 通过在位于PCB上的一个或多个电极上沉积第一介电层，在印刷电路板上形成电容器。 另一电极形成在第一电介质层的顶部，并且第二电介质层沉积在该电极的顶部上。 在第二电介质层的顶部形成第三电极。 通过诸如喷砂的方法在单个步骤中擦拭两个电介质层，以限定第一和第二电介质层的部分以产生多层电容结构。

公开(公告)号：US20080257480A1

公开(公告)日：2008-10-23

申请号：US11659973

申请日：2005-08-09

Applicant: Kensuke Nakamura

Inventor： Kensuke Nakamura

IPC: H05K3/46 ,  H05K3/30

CPC classification number: H05K1/162 ,  H05K3/002 ,  H05K3/0044 ,  H05K3/4626 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2203/025 ,  H05K2203/0554 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: The object of the present invention is to provide: a method for manufacturing a multilayer printed wiring board which enables the dielectric layers to have excellent thickness uniformity, the capacitor circuits to have high registration accuracy and the unnecessary dielectric layer is removed as large as possible; and a multilayer printed wiring board with an embedded capacitor circuit manufactured by the method. To achieve this object, a method is employed in which a multilayer printed wiring board with an embedded capacitor circuit is manufactured through: a first-conductive-metal-layer laminating step where a dielectric layer and a first conductive metal layer are provided on both sides of a core material having base electrode circuits; an top-electrode forming step where the first conductive metal layer(s) locating as outer layer(s) is(are) processed into top electrodes and the dielectric layer(s) in the area other than those of circuit portions is(are) exposed; a dielectric-layer removing step where the exposed dielectric layer(s), which is(are) in the area other than those of circuit portions, is(are) removed; a second-conductive-metal laminating step where the gaps among the top electrodes are filled in and an insulating layer and a second conductive metal layer are provided on the top electrodes; and an outer layer circuit forming step where the second conductive metal layer(s) is(are) processed into outer layer circuits.

Abstract translation: 本发明的目的是提供一种多层印刷电路板的制造方法，其能够使电介质层具有优异的厚度均匀性，使具有高配准精度的电容器电路和去除尽可能大的不需要的介电层; 以及通过该方法制造的具有嵌入式电容器电路的多层印刷线路板。 为了实现这个目的，采用了一种方法，其中通过以下方式制造具有嵌入式电容器电路的多层印刷线路板：第一导电金属层层压步骤，其两侧设置介电层和第一导电金属层 具有基极电极的芯材料; 其中将第一导电金属层定位为外层的顶电极形成步骤被处理成顶电极，并且除了电路部分之外的区域中的介电层是（） 裸露; 介质层去除步骤，其中除去除了电路部分以外的区域中的暴露介电层; 第二导电金属层叠步骤，其中顶部电极之间的间隙被填充，并且在顶部电极上设置绝缘层和第二导电金属层; 以及外层电路形成步骤，其中将第二导电金属层加工成外层电路。

公开(公告)号：US07436681B2

公开(公告)日：2008-10-14

申请号：US11970163

申请日：2008-01-07

Applicant: Hironori Tanaka

Inventor： Hironori Tanaka

IPC: H05K1/16

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/112 ,  H05K3/4602 ,  H05K3/4641 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/417 ,  Y10T29/4913 ,  H01L2924/00

Abstract: The invention provides a wiring board with built-in capacitors, that has a multilayer wiring structure and capable of mounting an IC chip thereon. The wiring board with built-in capacitors includes: a first capacitor that is built into the multilayer wiring structure and formed so that an overlapping area between a first lower electrode and a first upper electrode provided on respective surfaces of a first dielectric layer is a predetermined area; and a second capacitor that is built into the multilayer wiring structure along the same plane as the first dielectric layer and formed so that an overlapping area between a second lower electrode and a second upper electrode provided on respective surfaces of a second dielectric layer with the same thickness as the first dielectric layer is different from the predetermined area. The wiring board further includes: a line that electrically connects either one of a power pad for supplying power to the IC chip and a ground pad for grounding the IC chip to either one of the first lower electrode and the second lower electrode; and a line that electrically connects the other of the power pad and the ground pad to the other of the first upper electrode and the second upper electrode.

Abstract translation: 本发明提供一种具有内置电容器的布线板，其具有多层布线结构并且能够在其上安装IC芯片。 具有内置电容器的布线板包括：第一电容器，其内置在多层布线结构中，并且形成为使得设置在第一介电层的各个表面上的第一下电极和第一上电极之间的重叠区域是预定的 区; 以及第二电容器，其沿着与第一电介质层相同的平面内置在多层布线结构中，并且形成为使得第二下电极和第二上电极之间的重叠区域设置在具有该第二电介质层的第二电介质层的各个表面上 第一电介质层的厚度与预定面积不同。 所述布线基板还包括：将与所述IC芯片供电的功率垫中的任一个电连接的接线板和将所述IC芯片接地到所述第一下部电极和所述第二下部电极中的任一个的接地焊盘; 以及将所述电源焊盘和所述接地焊盘中的另一个电连接到所述第一上电极和所述第二上电极中的另一个的线。

公开(公告)号：US07432451B2

公开(公告)日：2008-10-07

申请号：US11337470

申请日：2006-01-24

Applicant: Kazuyuki Yamada

Inventor： Kazuyuki Yamada

IPC: H05K1/16

CPC classification number: G02F1/13452 ,  G02F2001/13456 ,  H05K1/113 ,  H05K1/189 ,  H05K2201/0394 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/10674

Abstract: An electro-optical device including an electro-optical panel, a flexible base member connected to the electro-optical panel, and an electronic component mounted on the flexible base member. The electronic component having conductive terminals electrically connected to a plurality of terminals disposed on the flexible base member, the plurality of terminals are disposed on one surface of the flexible base member, and the conductive terminals and the plurality of terminals two-dimensionally overlap each other. The flexible base member has first wires which are connected to the plurality of terminals and disposed on the one surface, hole portions formed in the flexible base member to correspond to at least one terminal, and second wires connected to the at least one terminal through connection members disposed in the hole portions and disposed on the other surface of the flexible base member opposite to the one surface.

Abstract translation: 一种电光学装置，包括电光面板，连接到电光面板的柔性基底构件和安装在柔性基底构件上的电子部件。 所述电子部件具有导电端子，电连接到设置在所述柔性基底部件上的多个端子，所述多个端子设置在所述柔性基底部件的一个表面上，并且所述导电端子和所述多个端子彼此二维重叠 。 柔性基体具有连接到多个端子并设置在一个表面上的第一导线，形成在柔性基底构件中的孔部分对应于至少一个端子，以及通过连接连接到至少一个端子的第二导线 设置在所述孔部分中并且设置在所述柔性基底构件的与所述一个表面相对的另一表面上的构件。

公开(公告)号：US20080238568A1

公开(公告)日：2008-10-02

申请号：US11729558

申请日：2007-03-29

Applicant: Emile Davies-venn ,  Telesphor Kamgaing

Inventor： Emile Davies-venn ,  Telesphor Kamgaing

IPC: H03H7/42

CPC classification number: H03H7/42 ,  H03H2001/0085 ,  H05K1/162 ,  H05K1/165 ,  H05K1/167 ,  H05K3/4602 ,  H05K2201/0187 ,  H05K2201/09509 ,  H05K2201/09536

Abstract: Methods and apparatus relating to package embedded three dimensional baluns are described. In one embodiment, components of one or more baluns may be embedded in a single semiconductor substrate. Other embodiments are also described.

Abstract translation: 描述了与封装嵌入式三维巴伦相关的方法和装置。 在一个实施例中，一个或多个巴伦的组件可以嵌入在单个半导体衬底中。 还描述了其它实施例。

公开(公告)号：US20080225502A1

公开(公告)日：2008-09-18

申请号：US12073931

申请日：2008-03-12

Applicant: Paul James Brown

Inventor： Paul James Brown

IPC: H05K1/18 ,  H05K1/00

CPC classification number: H05K1/114 ,  H01L21/50 ,  H01L23/49816 ,  H01L2924/0002 ,  H05K3/429 ,  H05K2201/09227 ,  H05K2201/09509 ,  H05K2201/097 ,  H05K2201/10734 ,  H01L2924/00

Abstract: A printed circuit board (PCB) assembly having a plurality of circuit layers including outer layers and intervening layers with through-vias and micro-vias used to translate a portion of the signal connections of the grid, thereby creating a set of diagonal routing channels between the vias on internal layers of the board and a BGA package mounted on the printed circuit board.

公开(公告)号：US07419382B2

公开(公告)日：2008-09-02

申请号：US11589332

申请日：2006-10-30

Applicant: Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

Inventor： Daigo Suzuki ,  Akihiko Happoya ,  Hidenori Tanaka

IPC: H01R12/00

CPC classification number: H01L24/11 ,  H01L24/742 ,  H01L24/81 ,  H01L2224/1131 ,  H01L2224/13099 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/81121 ,  H01L2224/81136 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/0269 ,  H05K1/112 ,  H05K1/186 ,  H05K3/303 ,  H05K3/4623 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09527 ,  H05K2201/10674 ,  H05K2203/166

Abstract: According to one embodiment, a printed circuit board includes a first dielectric layer, a circuit component mounted on the first dielectric layer, and a second dielectric layer. The first dielectric layer is provided with a via hole which opens at a surface thereof and in which a conductive layer is provided, and a conductive pattern connected electrically to the conductive layer of the via hole. The circuit component is provided with a bump at least a part of which is inserted in the via hole and bonded to an inner surface of the via hole. The second dielectric layer is formed provided with another conductive pattern and laminated to the first dielectric layer to cover the circuit component.

Abstract translation: 根据一个实施例，印刷电路板包括第一电介质层，安装在第一电介质层上的电路部件和第二电介质层。 第一介电层设置有在其表面开口并且其中设置有导电层的通孔以及与通孔的导电层电连接的导电图案。 电路部件设置有凸块，其中至少一部分插入通孔中并结合到通孔的内表面。 第二电介质层被形成为设置有另一个导电图案并层压到第一电介质层以覆盖电路部件。

公开(公告)号：US20080165515A1

公开(公告)日：2008-07-10

申请号：US11970112

申请日：2008-01-07

Applicant: Shih-Ping Hsu ,  Kan-Jung Chia

Inventor： Shih-Ping Hsu ,  Kan-Jung Chia

IPC: H05K7/00

CPC classification number: H05K1/185 ,  H01L23/50 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H01L2224/20 ,  H01L2224/73267 ,  H01L2924/01013 ,  H01L2924/01033 ,  H01L2924/15787 ,  H01L2924/18162 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H05K1/053 ,  H05K1/162 ,  H05K3/4608 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/10674 ,  H01L2924/00

Abstract: The present invention provides a circuit board having electronic components integrated therein, including a carrier board having an metallic oxide layer formed on each two surfaces of a metal layer, and having at least one through cavity; at least a semiconductor chip hold in the opening; at least a capacitor disposed on one surface of the carrier board, wherein the surface with the capacitor disposed thereon is at the same side with the active surface of the semiconductor chip. The capacitor is constituted of a first electrode plate disposed on partial surface of one side of the carrier board, a high dielectric material layer disposed on the surface of the first electrode plate, and a second electrode plate, paralleling and corresponding to the first electrode plate, disposed on the surface of the high dielectric material. The metal layer and the oxidation layer of the carrier board can enhance rigidity as well as tenacity and also integrate semiconductor chips and capacitors in the circuit board structure.

Abstract translation: 本发明提供了一种集成有电子部件的电路板，包括：载体板，其具有在金属层的每两个表面上形成的金属氧化物层，并具有至少一个通孔; 至少一个半导体芯片保持在开口中; 至少设置在所述载板的一个表面上的电容器，其中设置有所述电容器的所述表面与所述半导体芯片的有源表面处于同一侧。 电容器由设置在载板的一侧的部分表面上的第一电极板，设置在第一电极板的表面上的高介电材料层和与第一电极板相对应的第二电极板 ，设置在高电介质材料的表面上。 载体板的金属层和氧化层可以提高刚性和强度，并且还将半导体芯片和电容器集成在电路板结构中。

公开(公告)号：US07385144B2

公开(公告)日：2008-06-10

申请号：US11281797

申请日：2005-11-17

Applicant: Ronald J. Hash ,  Mitchell Percival

Inventor： Ronald J. Hash ,  Mitchell Percival

IPC: H05K1/03 ,  H05K3/10

CPC classification number: H05K3/366 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09145 ,  H05K2201/09181 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09709 ,  Y10T29/49165 ,  Y10T29/49798

Abstract: A method and apparatus is provided for forming a printed circuit board or other panel in which an array of vias are arranged in a desired connection grid within one or more layers of the board and then the board and vias are cut to form an edge of the board where a surface of the vias is exposed. The board may be orthogonally mounted on its edge to another thin circuit board or aperture sheet with the exposed surface of each via directly connected to such other board or sheet.

Abstract translation: 提供了一种用于形成印刷电路板或其他面板的方法和装置，其中通孔阵列布置在板的一层或多层内的所需连接格栅中，然后将板和通孔切割成形成 通孔的表面露出的板。 该板可以在其边缘上正交地安装到另一个薄的电路板或孔板上，每个通孔的暴露表面直接连接到这样的其它板或片。

公开(公告)号：US20080113466A1

公开(公告)日：2008-05-15

申请号：US11973193

申请日：2007-10-05

Applicant: Soichi Moriya ,  Takeo Kawase ,  Mitsuaki Harada ,  Takehisa Saeki ,  Tomoyuki Okuyama ,  Hirofumi Hokari ,  Takashi Aoki

Inventor： Soichi Moriya ,  Takeo Kawase ,  Mitsuaki Harada ,  Takehisa Saeki ,  Tomoyuki Okuyama ,  Hirofumi Hokari ,  Takashi Aoki

IPC: H01L31/18

CPC classification number: H05K3/0044 ,  H01L21/481 ,  H01L23/49811 ,  H01L51/0541 ,  H01L51/055 ,  H01L2924/0002 ,  H01L2924/19107 ,  H01L2924/3011 ,  H05K3/002 ,  H05K3/0035 ,  H05K3/28 ,  H05K2201/09509 ,  H05K2201/09827 ,  H05K2203/0126 ,  H05K2203/0195 ,  H05K2203/0221 ,  H05K2203/082 ,  H05K2203/087 ,  H05K2203/1105 ,  H05K2203/1189 ,  Y10T29/49126 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method of forming a contact hole includes forming a first conductive layer patterned so as to serve as an electrode or a wiring on a substrate, forming an insulation layer on the substrate and the first conductive layer, inserting a cutting instrument into the insulation layer at an angle to a surface of the insulation layer, the angle being in the range from #5#° to~ 80#°, and forming a tapered opening extending to the electrode or the wiring in the insulation layer by drawing out the cutting instrument.

Abstract translation: 形成接触孔的方法包括形成图案化以在基板上作为电极或布线的第一导电层，在基板上形成绝缘层和第一导电层，将切割仪器插入绝缘层中 与绝缘层的表面成一定角度，该角度在＃5°〜〜80°°的范围内，并且通过拉出切割器具形成延伸到绝缘层中的电极或布线的锥形开口。