公开(公告)号：US20030022477A1

公开(公告)日：2003-01-30

申请号：US10052989

申请日：2001-11-09

Inventor： Han-Kun Hsieh ,  Shing-Ru Wang ,  I-Chung Tung

IPC: H01L021/44

CPC classification number: H01L24/16 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/11502 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/81026 ,  H01L2224/81192 ,  H01L2224/81193 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01052 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/30107 ,  H01L2924/351 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/3473 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/025 ,  H05K2203/043 ,  H05K2203/054 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method of fabricating electroplate solder on an organic circuit board for forming flip chip joints and board to board solder joints is disclosed. In the method, there is initially provided an organic circuit board including a surface bearing electrical circuitry that includes at least one contact pad. A solder mask layer that is placed on the board surface and patterned to expose the pad. Subsequently, a metal seed layer is deposited by physical vapor deposition, chemical vapor deposition, electroless plating with the use of catalytic copper, or electroplating with the use of catalytic copper, over the board surface. A resist layer with at least an opening located at the pad is formed over the metal seed layer. A solder material is then formed in the opening by eletroplating. Finally, the resist and the metal seed layer beneath the resist are removed.

Abstract translation: 公开了一种在用于形成倒装芯片接头和板对板焊点的有机电路板上制造电镀焊料的方法。 在该方法中，最初提供了一种有机电路板，其包括具有至少一个接触垫的表面承载电路。 焊接掩模层，其被放置在板表面上并被图案化以暴露焊盘。 随后，在板表面上通过物理气相沉积，化学气相沉积，使用催化铜的化学镀或使用催化铜的电镀沉积金属种子层。 在金属种子层上形成具有至少位于焊盘处的开口的抗蚀剂层。 然后通过电镀在开口中形成焊料。 最后，去除抗蚀剂下的抗蚀剂和金属种子层。

公开(公告)号：US20020189849A1

公开(公告)日：2002-12-19

申请号：US10108628

申请日：2002-03-29

Applicant: IBIDEN Co., Ltd.

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H05K007/06

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90null in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract translation: 在布线图案58b，58c和58d的交叉部分X中，在构成拐角部分C等于或小于90°的部分加上一个纸条F，并形成布线图案58。 由于添加了纸张F，所以布线图案不会变薄，并且在交叉部分X中不会断开。另外，由于不会对交叉部分X集中的应力，因此布线图案中不会导致断线，也不会产生气泡 留在布线图案的交叉部分X和层间树脂绝缘层之间，从而提高了印刷线路板的可靠性

公开(公告)号：US20020182832A1

公开(公告)日：2002-12-05

申请号：US10198388

申请日：2002-07-17

Inventor： Donald S. Farquhar ,  Konstantinos I. Papathomas

IPC: H01L021/20

CPC classification number: H01L21/486 ,  H01L23/49883 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/4069 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0152 ,  H05K2203/0156 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0554 ,  H05K2203/1461 ,  H01L2924/00

Abstract: The present invention provides a method of filling an at least one aperture in a semiconductor substrate by placing a sacrificial carrier structure on a surface of the substrate, wherein the structure comprises, a first layer, a fill material over the first layer, and a mask over the fill material having at least one opening therein, such that the opening at least partially aligns with the aperture in the substrate. Thereafter, the fill material is forced into the aperture by the application of heat and pressure, and the sacrificial carrier structure is removed.

公开(公告)号：US06467160B1

公开(公告)日：2002-10-22

申请号：US09537960

申请日：2000-03-28

Applicant: Michael J. Cummings ,  Michael V. Longo ,  Curtis L. Miller ,  Thomas R. Miller ,  Michael Wozniak

Inventor： Michael J. Cummings ,  Michael V. Longo ,  Curtis L. Miller ,  Thomas R. Miller ,  Michael Wozniak

IPC: H01K310

CPC classification number: H05K3/427 ,  H05K3/0094 ,  H05K3/064 ,  H05K2201/0959 ,  H05K2203/1394 ,  Y10T29/49128 ,  Y10T29/49165

Abstract: A method of making a circuitized substrate having plated through holes free of filler material is provided. The method includes the steps of providing a dielectric substrate having first and second opposite faces. At least one via hole is formed from one face to the other. A first electrically conductive layer is applied onto the top and bottom faces of the dielectric member and onto the side wall of the via. First layers of photoresist are applied to each layer of conductive material and entering at least partially into the via hole. The first layers of photoresist are selectively exposed and developed to remove all of the photoresist, except that photoresist which is disposed in the via holes. Thereafter, a portion of the faces of the metal coatings on the surfaces of dielectric material and any photoresist remaining in the holes extending above the layers of electrically conductive material are removed to form a planar surface thinner than the thickness of the metal in the through hole. Thereafter, a second layer of photoresist material is applied to both the surfaces of the metal on both faces of the dielectric material and exposed to a desired circuit pattern. Thereafter, the second layers of the photoresist material are developed to reveal the underlying metal which is then etched to form a circuit pattern in the metal layer on both faces. Thereafter, the second layers of the remaining photoresist are stripped and also the photoresist remaining in the hole is stripped, thereby to provide a circuitized substrate with plated through holes having an opening extending from the upper face of the substrate to the lower face of the substrate.

Abstract translation: 提供了一种制造电路化基板的方法，该基板具有不含填料的电镀通孔。 该方法包括提供具有第一和第二相对面的电介质基板的步骤。 至少一个通孔从一个面到另一个形成。 将第一导电层施加到电介质构件的顶表面和底表面上并通过通孔的侧壁。 将第一层光致抗蚀剂施加到每个导电材料层并且至少部分地进入通孔。 除了设置在通孔中的光致抗蚀剂之外，第一层光致抗蚀剂被选择性地曝光和显影以除去所有光致抗蚀剂。 此后，介电材料表面上的金属涂层表面的一部分和残留在延伸到导电材料层之上的孔中的任何光致抗蚀剂被去除以形成比通孔中的金属厚度更薄的平面 。 此后，将第二层光致抗蚀剂材料施加到电介质材料的两个表面上的金属的两个表面上并暴露于期望的电路图案。 此后，第二层光致抗蚀剂材料被显影以露出下面的金属，然后将其蚀刻以在两面上的金属层中形成电路图案。 此后，残留的光致抗蚀剂的第二层被剥离，并且剥离残留在孔中的光致抗蚀剂，从而为电路化基板提供具有从基板的上表面延伸到基板的下表面的开口的电镀通孔 。

公开(公告)号：US20020135104A1

公开(公告)日：2002-09-26

申请号：US10026382

申请日：2001-12-20

Inventor： Jesse Pedigo ,  Timothy Meyer

IPC: B23K031/02

CPC classification number: H05K3/1233 ,  H05K3/0094 ,  H05K3/4053 ,  H05K3/4069 ,  H05K2201/0959 ,  H05K2201/10204 ,  H05K2203/0126 ,  H05K2203/0139 ,  H05K2203/0156 ,  H05K2203/0182 ,  H05K2203/0554 ,  H05K2203/1105

Abstract: A filling system includes a pressurized source of fill material and a pressure fill head wherein the fill head also includes a heating element positioned so as to transfer heat to fill material passing through the fill head. A method of filling holes using a fill material passing through a pressure fill head includes the steps of causing fill material to enter the fill head, modifying the viscosity of the fill material while it is within the fill head, and causing the modified viscosity fill material to exit the fill head and enter at least one hole.

Abstract translation: 填充系统包括加压填充源和压力填充头，其中填充头还包括加热元件，其被定位成传递热量以填充通过填充头的材料。 使用通过压力填充头的填充材料填充孔的方法包括以下步骤：使填充材料进入填充头，在填充头内部改变填充材料的粘度，并且使改性粘度填充材料 退出填充头并进入至少一个孔。

公开(公告)号：US20020100608A1

公开(公告)日：2002-08-01

申请号：US10003103

申请日：2001-12-06

Applicant: Hoya Corporation

Inventor： Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

IPC: H05K001/03

CPC classification number: H05K3/426 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 nullm thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract translation: 允许形成精细布线图案的多层印刷布线板，从而增加布线图案的密度。 使用具有与铜膜接近的热膨胀系数的感光性玻璃作为芯基板，通过光刻在感光性玻璃中形成通孔，形成溅射氧化硅层和溅射氮化硅层，以防止泄漏 形成来自感光玻璃的碱金属离子，溅射铬层，溅射铬 - 铜层和溅射铜层，以提高铜膜和溅射氧化硅层之间的粘合强度，并使铜膜为1〜20 形成了厚厚的妈妈。 当树脂填充到通孔的内部时，通过蚀刻对布线层进行图案化，形成绝缘层，并且表面被表面处理层和覆盖层覆盖。

公开(公告)号：US06426011B1

公开(公告)日：2002-07-30

申请号：US09540412

申请日：2000-03-31

Applicant: Takashi Katoh

Inventor： Takashi Katoh

IPC: H05K342

CPC classification number: H05K3/4623 ,  H05K3/0094 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/0353

Abstract: A method of making a printed circuit board whereby a fine wiring pattern can be formed. A through hole is formed in a substrate, both surfaces of the substrate being covered with copper foil. The substrate is treated with a catalyst and plated with copper. The through hole is filled with an insulating material, and the copper layer on the substrate is etched so that the catalyst layer is not exposed, leaving a thinned copper layer. Then, the substrate surfaces are ground and leveled by removing any projecting insulating material. Thereafter, another copper layer is deposited on the surface of the substrate, including surface regions on the fill material and is circuitized to form a wiring pattern. Since the catalyst layer is not exposed when the copper layer on the substrate is thinned, a fine wiring pattern can be obtained without the problem of subsequent peeling of the wiring conductors, or the entrapment of air.

Abstract translation: 一种制造印刷电路板的方法，由此可以形成精细的布线图案。 在基板上形成通孔，基板的两面被铜箔覆盖。 用催化剂处理基板并镀上铜。 通孔填充有绝缘材料，并且蚀刻基板上的铜层，使得催化剂层不被暴露，留下薄的铜层。 然后，通过去除任何突出的绝缘材料来研磨和调平基板表面。 此后，在衬底的表面上沉积另一个铜层，包括填充材料上的表面区域，并被电路化以形成布线图案。 由于当衬底上的铜层变薄时催化剂层不暴露，所以可以获得精细的布线图案，而不会导致布线导体随后的剥离或空气的夹带。

公开(公告)号：US06398099B1

公开(公告)日：2002-06-04

申请号：US09621166

申请日：2000-07-21

Applicant: Been-Yu Liaw

Inventor： Been-Yu Liaw

IPC: B23K100

CPC classification number: B29C39/10 ,  B29C67/08 ,  B29C2791/005 ,  H01L21/486 ,  H05K3/0094 ,  H05K3/1233 ,  H05K3/4053 ,  H05K2201/0959 ,  H05K2203/0126 ,  H05K2203/082 ,  H05K2203/1105 ,  Y10T29/49124

Abstract: An apparatus for manufacturing a plug and the manufacturing method. The method includes the following steps. A baseplate located in the bottom of a closed printing chamber is provided. A printed circuit board and a stencil are mounted on the baseplate in sequence. The stencil is aligned to the printed circuit board. An amount of preheated paste is placed on the stencil. A pressure of the closed printing chamber is adjusted to a first pressure. A printing step is performed to form plugs in the printed circuit board. The pressure of the closed printing chamber is adjusted to a second pressure to remove voids trapped in the plugs. The pressure of the closed printing chamber is adjusted to a third pressure. A scraping step is performed to remove the redundant paste.

Abstract translation: 一种用于制造插头的装置及其制造方法。 该方法包括以下步骤。 提供位于封闭印刷室底部的底板。 依次将印刷电路板和模板安装在底板上。 模板与印刷电路板对齐。 将一定量的预热膏放在模板上。 将封闭的印刷室的压力调节至第一压力。 执行打印步骤以在印刷电路板中形成插头。 将封闭的印刷室的压力调节至第二压力以除去捕获在插塞中的空隙。 将封闭的印刷室的压力调整到第三压力。 执行刮擦步骤以去除冗余浆料。

公开(公告)号：US20020020896A1

公开(公告)日：2002-02-21

申请号：US09855476

申请日：2001-05-14

Inventor： Kazumitsu Ishikawa ,  Hiroyuki Kudoh ,  Masayuki Sakurai

IPC: H01L029/06

CPC classification number: H01L23/49805 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/3011 ,  H05K3/0052 ,  H05K3/3442 ,  H05K3/366 ,  H05K3/368 ,  H05K3/403 ,  H05K3/427 ,  H05K2201/0215 ,  H05K2201/0236 ,  H05K2201/0347 ,  H05K2201/0959 ,  H01L2924/00

Abstract: An electronic component device includes a printed wiring board having a side surface terminal portion formed of a recessed groove, filler, and plating conductor. The recessed groove is formed in a side surface, or a corner adjacent to the side surface, of a board and extending from an upper surface to a lower surface. The filler fills the groove and has a plating catalytic function. The plating conductor covers an exposed surface of the filler. A method of manufacturing the electronic component device is also disclosed.

Abstract translation: 电子部件装置包括具有由凹槽，填充物和电镀导体形成的侧面端子部的印刷布线板。 凹槽形成在板的侧表面或与侧表面相邻的拐角处并且从上表面延伸到下表面。 填料填充槽并具有电镀催化功能。 电镀导体覆盖填料的暴露表面。 还公开了一种制造电子部件装置的方法。

公开(公告)号：US20010023780A1

公开(公告)日：2001-09-27

申请号：US09812817

申请日：2001-03-21

Applicant: NEC CORPORATION

Inventor： Shigeru Mori

IPC: H05K001/03

CPC classification number: H05K1/0271 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0278 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959

Abstract: A printed wiring board is formed by a printed wiring substrate having a plurality of a wiring layer, and a thermal expansion buffering sheet having lower coefficient of thermal expansion than that of said printed wiring substrate, which is integrally laminated on a surface of the printed wiring substrate.

Abstract translation: 印刷布线板由具有多个布线层的印刷布线基板和热膨胀系数比所述印刷布线基板的热膨胀系数低的热膨胀缓冲片形成，该片材整体层压在印刷布线的表面上 基质。