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    Multi-layer wiring board
    141.
    发明申请
    Multi-layer wiring board 失效
    多层接线板

    公开(公告)号：US20020181185A1

    公开(公告)日：2002-12-05

    申请号：US10132685

    申请日：2002-04-25

    Inventor： Masanao Kabumoto ,  Kouki Kawabata

    IPC: H01G004/228

    CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2223/6627 ,  H01L2224/16 ,  H01L2924/0102 ,  H01L2924/01025 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/1903 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0216 ,  H05K1/0289 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/09672

    Abstract: A multi-layer wiring board comprises an insulating substrate having, on a central part of its top surface, a semiconductor device mounting portion and having, on its under surface, an external electrode. The insulating substrate includes a multilayered wiring having a first group of parallel wiring lines; a second group of parallel wiring lines arranged orthogonal thereto; and a group of through conductors for providing electrical connection therebetween. Power is supplied from the external electrode to the semiconductor device through built-in capacitors formed therewithin. The built-in capacitors are connected in parallel that have different resonance frequencies within a range from an operating frequency band for the semiconductor device to a frequency band for a harmonic component, and at an anti-resonance frequency occurring between the different resonance frequencies, a composite impedance is equal to or below a predetermined value.

    Abstract translation: 多层布线基板包括绝缘基板，该绝缘基板在其顶表面的中心部分具有半导体器件安装部分，并且在其下表面上具有外部电极。 绝缘基板包括具有第一组平行布线的多层布线; 与其正交布置的第二组平行布线; 以及一组用于在它们之间提供电连接的通孔导体。 通过内部形成的电容器将功率从外部电极提供给半导体器件。 内置电容器并联连接，其在从半导体器件的工作频带到谐波分量的频带范围内以及在不同谐振频率之间出现的反共振频率范围内具有不同的谐振频率，a 复合阻抗等于或低于预定值。

    Filter circuit and electronic device using the same
    142.
    发明申请
    Filter circuit and electronic device using the same 有权
    滤波电路及使用其的电子设备

    公开(公告)号：US20020175748A1

    公开(公告)日：2002-11-28

    申请号：US10125532

    申请日：2002-04-19

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Hiroshi Nishikawa

    IPC: H03K005/00

    CPC classification number: H03H1/02 ,  H05K1/0306 ,  H05K1/16 ,  H05K1/162 ,  H05K1/167 ,  H05K3/4644 ,  H05K2201/09672 ,  H05K2201/10166

    Abstract: A filter circuit includes a first distributed parameter RC circuit having a first distributed parameter resistor and a first distributed parameter capacitance and a second distributed parameter RC circuit having a second distributed parameter resistor and a second distributed parameter capacitance, wherein one end of each of the first and second distributed parameter resistors connected in parallel is connected to an input terminal of a buffer circuit and the second distributed parameter capacitance is connected to an output terminal of the buffer circuit, and when the number of distributed parameter RC circuits connected in parallel is n, which can be two or more, the number of distributed parameter capacitances connected to the output terminal of the buffer circuit is one to nnull1.

    Abstract translation: 滤波器电路包括具有第一分布参数电阻器和第一分布参数电容器的第一分布参数RC电路和具有第二分布参数电阻器和第二分布参数电容器的第二分布参数RC电路，其中第一分配参数电阻器 并联连接的第二分布式参数电阻器连接到缓冲电路的输入端，第二分布参数电容连接到缓冲电路的输出端，并联并联的分布参数RC电路的数量为n， 连接到缓冲电路的输出端的分布参数电容的数量可以是两个以上，为1〜n-1。

    Electric component
    143.
    发明授权
    Electric component 有权
    电气部件

    公开(公告)号：US06421225B2

    公开(公告)日：2002-07-16

    申请号：US09333880

    申请日：1999-06-15

    Applicant: Leif Bergstedt

    Inventor： Leif Bergstedt

    IPC: H01G420

    CPC classification number: H05K1/162 ,  H05K1/167 ,  H05K3/386 ,  H05K3/4626 ,  H05K2201/015 ,  H05K2201/0191 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/09672

    Abstract: Invention refers to an electric component, preferably a component buried in a Printed Circuit Board (PCB) including at least two conductive layers (13,21, 36; 15, 35) and an intermediate layer (14, 37). The intermediate layer (14, 37) further consists of at least two layers (16, 17, 22, 23, 38, 39, 40): at least a first layer (17, 23, 39) and a second layer (16, 22, 38, 40), which at least first layer has more elastic characteristic than the second layer (16, 22, 38, 40) at a certain temperature and/or pressure.

    Abstract translation: 本发明涉及一种电子部件，优选埋入包括至少两个导电层（13,21,36; 15,35）和中间层（14,37）的印刷电路板（PCB）中的部件。 中间层（14,37）还包括至少两层（16,17,22,23,38,39,40）：至少第一层（17,23,39）和第二层（16， 22,38,40），其至少第一层在一定温度和/或压力下具有比第二层（16,22,38,40）更具弹性的特性。

    Two-layered embedded capacitor
    144.
    发明申请
    Two-layered embedded capacitor 审中-公开
    两层嵌入式电容器

    公开(公告)号：US20020048137A1

    公开(公告)日：2002-04-25

    申请号：US09538823

    申请日：2000-03-30

    Inventor： Thomas J. Williams ,  William D. Varnell ,  Robert J. Sanville

    IPC: H01G004/35

    CPC classification number: H05K1/162 ,  H05K3/386 ,  H05K3/4652 ,  H05K3/4655 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/09672

    Abstract: A novel capacitor foil and printed circuit board intermediate made using that foil are disclosed. The capacitor foil is a two-layer construction having a conductive layer and a partially cured bonding layer having a high dielectric constant. The high dielectric bonding layer is formed with epoxy or other polymer and is loaded with capacitive ceramic particles or pre-fired ceramic forming particles. The resulting capacitor foil may be applied to a laminate having copper patterns thereon to define a PCB intermediate containing at least one buried capacitor device. Multiple layers of capacitance material also can be used to increase the overall capacitance of the board.

    Abstract translation: 公开了一种新颖的电容器箔和使用该箔制成的印刷电路板中间体。 电容器箔是具有导电层和具有高介电常数的部分固化的结合层的双层结构。 高介电接合层由环氧树脂或其它聚合物形成，并装载有电容陶瓷颗粒或预焙烧陶瓷形成颗粒。 所得到的电容器箔可以被施加到其上具有铜图案的层压体以限定包含至少一个埋入电容器装置的PCB中间体。 多层电容材料也可用于增加电路板的整体电容。

    Interconnect structure
    145.
    发明申请
    Interconnect structure 失效
    互连结构

    公开(公告)号：US20020037656A1

    公开(公告)日：2002-03-28

    申请号：US09955302

    申请日：2001-09-19

    Inventor： Yoshinori Murakami

    IPC: H05K001/00

    CPC classification number: H05K3/368 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2924/13091 ,  H01R12/52 ,  H05K1/0216 ,  H05K1/145 ,  H05K1/148 ,  H05K1/162 ,  H05K3/36 ,  H05K2201/0792 ,  H05K2201/09672 ,  H05K2201/1028 ,  H05K2201/10818 ,  H05K2201/10893 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: An interconnect structure has a plurality of planar interconnects (1, 2) mutually superposed with a prescribed distance therebetween and serving as interconnects between two circuit boards (A, B), each of the planar interconnects (1, 2) having at least two connection terminals (1A, 1B, 2A, 2B) at the circuit boards (1, 2). Rather than using rigid wire interconnects as done in the past to make interconnections, planar interconnects having relatively large surface areas are used to increase the line-to-line capacitance, thereby enhancing the filtering function that reduces high-frequency noise.

    Abstract translation: 互连结构具有多个平面互连（1,2），它们之间以规定距离相互重叠并且用作两个电路板（A，B）之间的互连，每个平面互连（1,2）具有至少两个连接 电路板（1,2）上的端子（1A，1B，2A，2B）。 不像以前那样使用刚性的电线互连来做互连，而是使用具有相对大的表面积的平面互连来增加线对线电容，从而增强降低高频噪声的滤波功能。

    Wiring substrate and process for producing the same
    148.
    发明申请
    Wiring substrate and process for producing the same 有权
    接线基板及其制造方法

    公开(公告)号：US20010010272A1

    公开(公告)日：2001-08-02

    申请号：US09731933

    申请日：2000-12-08

    Inventor： Kanji Otsuka ,  Tamotsu Usami

    IPC: H05K001/00

    CPC classification number: H05K1/0245 ,  H01L2924/0002 ,  H05K1/024 ,  H05K1/0242 ,  H05K3/0023 ,  H05K3/429 ,  H05K3/4623 ,  H05K3/4697 ,  H05K2201/09672 ,  H05K2203/086 ,  H01L2924/00

    Abstract: Signal wirings 22, 23 are formed on a pair of substrates 20, 21, and the substrates are joined together through an insulating layer 24 so that the signal wirings 22, 23 are placed in parallel and facing to each other. The surfaces of the overlapping faces of the signal wirings 22, 23 are made smooth, and the roughness of the same surfaces is smaller than the skin depth nulls due to the skin effect, preferably less than one third, for minimizing the increase in the electric resistance due to the skin effect.

    Abstract translation: 信号布线22,23形成在一对基板20,21上，并且基板通过绝缘层24接合在一起，使得信号布线22,23平行放置并彼此面对。 信号布线22,23的重叠面的表面是光滑的，并且由于皮肤效应，相同表面的粗糙度比皮肤效应小，优选小于三分之一，用于最小化电的增加 由于皮肤效应的抵抗力。

    Multi-layer printed wiring board having integrated broadside microwave coupled baluns
    149.
    发明授权
    Multi-layer printed wiring board having integrated broadside microwave coupled baluns 失效
    具有集成宽边微波耦合巴伦的多层印刷线路板

    公开(公告)号：US06263198B1

    公开(公告)日：2001-07-17

    申请号：US08661334

    申请日：1996-06-14

    Applicant: Frank Xiaohui Li

    Inventor： Frank Xiaohui Li

    IPC: H04B126

    CPC classification number: H05K1/0239 ,  H01P5/10 ,  H03D7/1408 ,  H03D9/0633 ,  H05K1/162 ,  H05K2201/09672 ,  H05K2201/10174

    Abstract: A microwave broadside coupled balun integral in a multi-layer printed wiring board formed by broadside coupled conductors embedded in the multi-layer printed wiring board. The balun may be used to form components which are integrated into the multi-layer printed wiring board, such as a microwave mixer formed by two of said broadside coupled baluns embedded in a multi-layer printed wiring board and connected to a diode ring quad.

    Abstract translation: 在由多层印刷线路板嵌入的宽边耦合导体形成的多层印刷线路板中的微波宽边耦合平衡 - 不平衡变换器。 平衡 - 不平衡变换器可以用于形成集成到多层印刷线路板中的组件，例如由嵌入在多层印刷线路板中并连接到二极管环四边形的两个所述宽边耦合平衡不平衡器形成的微波混频器。

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