中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

292 records (took 0.02 seconds)

    Semiconductor package and semiconductor package mounting method
    142.
    发明申请
    Semiconductor package and semiconductor package mounting method 有权
    半导体封装和半导体封装安装方法

    公开(公告)号：US20020167076A1

    公开(公告)日：2002-11-14

    申请号：US10119315

    申请日：2002-04-10

    Inventor： Kenichi Shirasaka

    IPC: H01L023/02

    CPC classification number: H05K3/303 ,  H01L23/544 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54473 ,  H01L2223/54486 ,  H01L2924/1815 ,  H05K1/0269 ,  H05K2201/09936 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2203/168 ,  Y02P70/613 ,  Y10S438/975

    Abstract: To provide a semiconductor package mounting method, with excellent work efficiency, wherein the direction of a semiconductor package can be verified by a simple method before mounting. One corner of a square shaped display section provided on the surface of a semiconductor package body is chamfered such that the chamfer dimensions are different from those of the other corners. If image recognition by a camera determines that this chamfered part is located correctly, the orientation of a semiconductor package is determined to be correct. On the other hand, if image recognition determines that it is not located correctly, the orientation of the semiconductor package is adjusted until it is correct.

    Abstract translation: 为了提供具有优异的工作效率的半导体封装安装方法，其中可以通过在安装之前的简单方法来验证半导体封装的方向。 设置在半导体封装体的表面上的方形显示部分的一个角部被倒角，使得倒角尺寸与其他角部的尺寸不同。 如果照相机的图像识别确定该倒角部分正确定位，则确定半导体封装的取向是正确的。 另一方面，如果图像识别确定其不正确定位，则调整半导体封装的取向直到其正确。

    Multifunctional laminate structure and process
    144.
    发明授权
    Multifunctional laminate structure and process 失效
    多功能层压结构和工艺

    公开(公告)号：US06399903B1

    公开(公告)日：2002-06-04

    申请号：US09500957

    申请日：2000-02-15

    Applicant: James F. Stevenson

    Inventor： James F. Stevenson

    IPC: H01H13705

    CPC classification number: H05K9/0084 ,  G06F1/182 ,  H01Q1/242 ,  H01Q1/42 ,  H04B15/00 ,  H05K1/0218 ,  H05K1/0393 ,  H05K3/0064 ,  H05K2201/0195 ,  H05K2201/09936

    Abstract: A multilayered structural element which is useful for forming housings for electronic devices such as cellular telephones. The multilayered structural element has sequentially attached layers: (a) thin, flexible polymeric outer film layer, (b) an electronic interface layer, the electronic interface layer comprising a thin, flexible polymeric film layer having a pattern of electrically conductive lines on at least one side thereof; (c) a rigid structural layer; (d) an electromagnetic interference shielding layer; and (e) an optional protective layer.

    Abstract translation: 一种多层结构元件，其可用于形成诸如蜂窝电话之类的电子设备的外壳。 所述多层结构元件具有顺序地附着的层：（a）薄的柔性聚合物外膜层，（b）电子界面层，所述电子界面层包含至少具有导电线图案的薄的柔性聚合物膜层 （c）刚性结构层;（d）电磁干扰屏蔽层; 和（e）可选的保护层。

    Method and apparatus for indicating degree of manufacture of an article
    145.
    发明授权
    Method and apparatus for indicating degree of manufacture of an article 失效
    用于指示制品的制造程度的方法和装置

    公开(公告)号：US06248424B1

    公开(公告)日：2001-06-19

    申请号：US08819589

    申请日：1997-03-17

    Applicant: Ernest H. Lindsay, Jr. ,  Jon M. Patterson

    Inventor： Ernest H. Lindsay, Jr. ,  Jon M. Patterson

    IPC: B32B302

    CPC classification number: B29C69/00 ,  B29C47/003 ,  B29C47/0038 ,  B29C47/004 ,  B29C2037/90 ,  H01R43/24 ,  H01R2201/20 ,  H05K1/0266 ,  H05K3/202 ,  H05K2201/09118 ,  H05K2201/09127 ,  H05K2201/09936 ,  H05K2203/162 ,  Y10S428/901 ,  Y10T29/49004 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T428/24174 ,  Y10T428/24273 ,  Y10T428/24777 ,  Y10T428/24802

    Abstract: A novel method and apparatus for indicating a degree of manufacture of an insert molded component useable in an end use assembly by forming a removable appendage protruding from the insert molded component, or article, manufactured to an intermediate degree, the insert molded component having a lead frame at least partially embedded in a molded housing member, and the removable appendage coupled to at least one or both of the lead frame and the molded housing member, the lead frame having at least two electrical conductors coupled separably by a tie member, the removable appendage removable upon or after electrical isolation of the electrical conductors in a subsequent processing step, whereby the presence of the removable appendage is indicative that the electrical conductors are not electrically isolated, or that the insert molded component has not been tested or inspected subsequent to electrical isolation of the electrical conductors, and whereby the removable appendage is configured to prevent use of the article manufactured to the intermediate degree in the end use assembly.

    Abstract translation: 一种新型的方法和装置，用于通过形成从中间程度制造的插入成型部件或制品突出的可移除附件来指示可用于最终使用组件的嵌入成型部件的制造程度，所述插入成型部件具有引线 框架至少部分地嵌入在模制的壳体构件中，并且可移除的附属物联接到引线框架和模制的壳体构件中的至少一个或两个，引线框架具有至少两个电连接构件可分离的电导体， 在随后的处理步骤中，在电导体的电绝缘之后或之后可移除的附件，由此可移除附件的存在指示电导体不是电隔离的，或者插入模制部件在电气之后未被测试或检查 电导体的隔离，并且由此可移除的附件是配置的 以防止在最终使用组件中使用制造成中等程度的制品。

    Method and apparatus for serializing printed circuit boards and flex circuits
    147.
    发明授权
    Method and apparatus for serializing printed circuit boards and flex circuits 失效
    用于串行化印刷电路板和柔性电路的方法和装置

    公开(公告)号：US4853317A

    公开(公告)日：1989-08-01

    申请号：US177131

    申请日：1988-04-04

    Applicant: Donald J. Hayes

    Inventor： Donald J. Hayes

    IPC: G03F1/00 ,  H05K1/00 ,  H05K1/02 ,  H05K3/00 ,  H05K3/06

    CPC classification number: G03F7/2018 ,  H05K1/0266 ,  H05K3/0082 ,  H05K1/0393 ,  H05K2201/09781 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2203/013 ,  H05K2203/0551 ,  H05K3/064

    Abstract: A method and apparatus for providing serialization of printed circuit boards and flex circuits during the normal process of manufacture of the boards and circuits is disclosed and includes a print module which prints the serializing information on the surface of the photoresist material with a fluid, which blocks the passage of ultraviolet radiation, before the photoresist material is exposed to ultraviolet radiation through the photomask. If a negative-acting photoresist material is used, the serializing information is reverse printed on the surface of the negative-acting photoresist material. If a positive-acting photoresist material is used, the serializing information is printed on the surface of the positive-acting photoresist material.

    Abstract translation: 公开了一种用于在板和电路的正常制造过程中提供印刷电路板和柔性电路串联化的方法和装置，其包括印刷模块，该印刷模块用流体将光致抗蚀剂材料的表面上的串行化信息打印， 在光致抗蚀剂材料通过光掩模暴露于紫外线辐射之前紫外线辐射的通过。 如果使用负性光致抗蚀剂材料，则在负性光致抗蚀剂材料的表面上反向印刷串行化信息。 如果使用正性光致抗蚀剂材料，则将序列化信息印刷在正性光致抗蚀剂材料的表面上。

    Electronic circuit assembly
    148.
    发明授权
    Electronic circuit assembly 失效
    电子电路组件

    公开(公告)号：US4833570A

    公开(公告)日：1989-05-23

    申请号：US116662

    申请日：1987-11-03

    Applicant: Tatsuo Teratani

    Inventor： Tatsuo Teratani

    IPC: H05K3/28 ,  H05K3/30 ,  H05K3/34

    CPC classification number: H05K3/306 ,  H05K3/284 ,  H05K2201/0133 ,  H05K2201/09909 ,  H05K2201/09936 ,  H05K2201/10568 ,  H05K2201/10689 ,  H05K2201/10977 ,  H05K2201/2036 ,  H05K2203/167 ,  H05K3/3447

    Abstract: An electronic circuit assembly includes a printed cirucit base plate, an electronic circuit element, a spacer and a coating resin. The electronic circuit element includes an IC housing and a plurality of lead pins. The plurality of lead pins are electrically connected and secured to the printed circuit base plate such that the IC housing is spaced apart from the printed circuit base plate. The spacer is located between the printed circuit base plate and the IC housing. The coating resin coats the printed circuit base plate, a portion of the spacer and a portion of the lead pins of the electronic circuit element.

    Abstract translation: 电子电路组件包括印刷的cirucit基板，电子电路元件，间隔物和涂层树脂。 电子电路元件包括IC壳体和多个引脚。 多个引脚被电连接并固定到印刷电路基板，使得IC壳体与印刷电路基板间隔开。 间隔件位于印刷电路基板和IC外壳之间。 涂布树脂涂覆印刷电路基板，间隔物的一部分和电子电路元件的引脚的一部分。

    Circuit wiring disposed on solder mask coating
    149.
    发明授权
    Circuit wiring disposed on solder mask coating 失效
    电路布线布置在焊接涂层上

    公开(公告)号：US4706167A

    公开(公告)日：1987-11-10

    申请号：US809767

    申请日：1985-12-17

    Applicant: Donald F. Sullivan

    Inventor： Donald F. Sullivan

    IPC: H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/04 ,  H05K3/10 ,  H05K3/24 ,  H05K3/34 ,  H05K3/46

    CPC classification number: H05K1/0268 ,  H05K1/0266 ,  H05K3/242 ,  H05K3/3452 ,  H05K3/465 ,  H05K1/117 ,  H05K2201/09036 ,  H05K2201/09436 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09927 ,  H05K2201/09936 ,  H05K2201/09981 ,  H05K2203/025 ,  H05K2203/054 ,  H05K2203/056 ,  H05K2203/0571 ,  H05K2203/0577 ,  H05K2203/066 ,  H05K2203/0759 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/108 ,  H05K3/4661 ,  Y10T29/49156

    Abstract: In the manufacturing process for a printed wiring board a photopolymer insulation layer having a flat outer plateau surface is extended from the board substrate surface carrying the wiring pattern and provides access channels to a plurality of wiring pattern conductor pad areas. A patterned conductor layer disposed on the insulation layer surface including the sidewalls of the access channels thus electrically connects to the conductor pad areas. Circuit wiring pattern test current or plating currents are passed through the conductor layer pattern during the manufacturing process, and the conductor layer may thereafter be easily removed from the flat surface by sanding or the like. Permanently retained conductor layer portions, such as feasible by indenting the plateau surface, aid in expanding conductor surface areas at solder joint pads, or in increasing the density of circuit wires feasible in a given substrate board area. The conductor layer may provide indicia marking nomenclature patterns which are in dot matrix format to reduce capacitance coupling between wiring circuits on the board substrate.

    Abstract translation: 在印刷电路板的制造方法中，具有平坦的外平台表面的光聚合物绝缘层从承载布线图案的基板表面延伸，并且提供到多个布线图案导体焊盘区域的访问通道。 设置在包括进入通道的侧壁的绝缘层表面上的图案化导体层因此电连接到导体焊盘区域。 电路布线图案测试电流或电镀电流在制造过程中通过导体层图案，并且导体层此后可以通过砂磨等容易地从平坦表面移除。 永久保持的导体层部分，例如通过压平平台表面可行，有助于扩大焊点处的导体表面积，或者增加在给定的基板区域中可行的电路线的密度。 导体层可以提供点阵格式的标记标记图案，以减小电路板基板上布线电路之间的电容耦合。

Patent Agency Ranking