公开(公告)号：US20070139150A1

公开(公告)日：2007-06-21

申请号：US11300860

申请日：2005-12-15

Applicant: Eugene Chow ,  Christopher Chua ,  Koenraad Van Schuylenbergh

Inventor： Eugene Chow ,  Christopher Chua ,  Koenraad Van Schuylenbergh

IPC: H01F5/00

CPC classification number: H05K3/4092 ,  H01F17/0006 ,  H01F17/0033 ,  H01F17/02 ,  H01F41/041 ,  H01F2027/2814 ,  H05K3/243 ,  H05K2201/0166 ,  H05K2201/0317 ,  H05K2201/0397 ,  H05K2203/0597 ,  H05K2203/0783

Abstract: A method of reflowing a polymer to form a spring or coil structure is described. A polymer is deposited over stress engineered thin film with an internal stress gradient. The polymer serves as a loading prevent release of the internal stress until a solvent vapor softens and reflows the polymer. As the polymer softens, the internal stress within the thin film is gradually released allowing controlled curling of the thin film out of a substrate plane. In one embodiment, the thin film forms the windings of a coil structure.

Abstract translation: 描述了一种回流聚合物以形成弹簧或线圈结构的方法。 聚合物沉积在具有内应力梯度的应力工程薄膜上。 聚合物用作负载，防止释放内部应力，直到溶剂蒸气软化和回流聚合物。 当聚合物软化时，薄膜内的内部应力逐渐释放，从而允许薄膜从基板平面受到控制的卷曲。 在一个实施例中，薄膜形成线圈结构的绕组。

公开(公告)号：US07226806B2

公开(公告)日：2007-06-05

申请号：US10074224

申请日：2002-02-14

Applicant: Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

Inventor： Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

IPC: H01L21/00

CPC classification number: H01L21/31138 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32134 ,  H05K1/0346 ,  H05K1/056 ,  H05K3/002 ,  H05K3/064 ,  H05K2201/0154 ,  H05K2201/0166

Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable by a wet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer—insulating layer—second inorganic material layer or a layer construction of inorganic material layer—insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.

Abstract translation: 本发明涉及一种层叠体中的绝缘体，其可以在使用时抑制除尘，更具体地说，涉及绝缘体的电子电路部件，特别是无线悬架。 绝缘体包括可通过湿法蚀刻的一个或多个绝缘单元层的层压体，该绝缘体在湿蚀刻之后已进行等离子体处理。 绝缘体主要作为具有第一无机材料层 - 绝缘层 - 第二无机材料层的层结构或无机材料层 - 绝缘层的层结构的层叠体的绝缘体存在，并且至少一部分无机材料层 已经被去除以暴露绝缘层。

公开(公告)号：US20070120229A1

公开(公告)日：2007-05-31

申请号：US11657448

申请日：2007-01-25

Applicant: Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

Inventor： Katsuya Sakayori ,  Terutoshi Momose ,  Shigeki Kawano ,  Tomoko Togashi ,  Hiroko Amasaki ,  Nobuhiro Sakihama ,  Tsuyoshi Yamazaki ,  Michiaki Uchiyama ,  Hiroshi Yagi

IPC: H01L23/58

CPC classification number: H01L21/31138 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/32134 ,  H05K1/0346 ,  H05K1/056 ,  H05K3/002 ,  H05K3/064 ,  H05K2201/0154 ,  H05K2201/0166

Abstract: The present invention relates to an insulator as an insulating layer in a laminate which can inhibit dusting at the time of use, more particularly an electronic circuit component to which the insulator has been applied, particularly a wireless suspension. The insulator comprises a laminate of one or more insulation unit layers etchable byawet process, the insulator having been subjected to plasma treatment after wet etching. The insulator exists mainly as an insulating layer in a laminate having a layer construction of first inorganic material layer—insulating layer—second inorganic material layer or a layer construction of inorganic material layer—insulating layer, and at least a part of the inorganic material layer has been removed to expose the insulating layer.

Abstract translation: 本发明涉及一种层叠体中的绝缘体，其可以在使用时抑制除尘，更具体地说，涉及绝缘体的电子电路部件，特别是无线悬架。 绝缘体包括一个或多个绝缘单元层的叠层，其可通过疏水工艺蚀刻，该绝缘体在湿法蚀刻之后已进行等离子体处理。 绝缘体主要作为具有第一无机材料层 - 绝缘层 - 第二无机材料层的层结构或无机材料层 - 绝缘层的层结构的层叠体的绝缘体存在，并且至少一部分无机材料层 已经被去除以暴露绝缘层。

公开(公告)号：US07211735B2

公开(公告)日：2007-05-01

申请号：US10028624

申请日：2001-12-20

Applicant: Yutaka Kaneda

Inventor： Yutaka Kaneda

IPC: H05K1/00

CPC classification number: H05K3/0002 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  H05K2201/0166 ,  H05K2201/0367 ,  H05K2203/056 ,  H05K2203/0733 ,  H05K2203/1545 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A process for manufacturing a multilayer flexible wiring board, which allows individual layers of wiring boards to be precisely positioned and to be readily stacked. A mask for exposure is prepared in which a plurality of pattern holes corresponding to individual layers of wiring boards of a multilayer flexible wiring board are arranged in the direction perpendicular to the transporting direction P of substrate. This mask for exposure is used to form a plurality of wiring patterns corresponding to individual layers of wiring boards of a multilayer flexible wiring board on the same sheet-like substrate.

Abstract translation: 一种制造多层柔性布线板的方法，其允许各层布线板精确定位并容易堆叠。 制备用于曝光的掩模，其中与垂直于基板的传送方向P的方向布置与多层柔性布线板的布线板的各层相对应的多个图案孔。 该曝光用掩模用于形成与同一片状基板上的多层柔性布线基板的各层布线基板对应的多个布线图案。

公开(公告)号：US20050251997A1

公开(公告)日：2005-11-17

申请号：US11127167

申请日：2005-05-12

Applicant: Ching-Fuq Homg ,  Yung-Hui Wang

Inventor： Ching-Fuq Homg ,  Yung-Hui Wang

IPC: H01L21/4763 ,  H05K3/00 ,  H05K3/42 ,  H05K3/46

CPC classification number: H05K3/427 ,  H05K3/4602 ,  H05K2201/0166 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for forming a printed circuit board, and more particularly a method of forming a plated through hole (PTH), a blind via, and a buried via of printed circuit board. The method includes providing a two-layer board having a through hole therein, conformally forming a seed layer on the metal foil and in the through hole, forming a mask on the metal foil, having an opening aligned to the through hole to expose the seed layer on the through hole, forming a conductive layer on the exposed seed layer within the through hole, and removing the mask.

Abstract translation: 一种形成印刷电路板的方法，更具体地说，一种形成印刷电路板的电镀通孔（PTH），盲孔和埋入通孔的方法。 该方法包括提供在其中具有通孔的双层板，在金属箔上和通孔中共形形成种子层，在金属箔上形成掩模，具有与通孔对准的开口以暴露种子 在通孔中的暴露的种子层上形成导电层，并且去除掩模。

公开(公告)号：US20050017369A1

公开(公告)日：2005-01-27

申请号：US10495959

申请日：2002-11-15

Applicant: Gary Clayton ,  Douglas Hastings

Inventor： Gary Clayton ,  Douglas Hastings

IPC: H01L23/498 ,  H01R13/24 ,  H05K3/32 ,  H05K3/40 ,  H01L23/48

CPC classification number: H01R13/2414 ,  H01L23/49827 ,  H01L23/49883 ,  H01L2924/0002 ,  H05K3/325 ,  H05K3/4069 ,  H05K2201/0166 ,  H05K2201/0314 ,  H05K2201/10378 ,  H05K2203/0568 ,  H05K2203/0769 ,  H05K2203/1572 ,  H01L2924/00

Abstract: An improved interposer for use in forming an electrical connection between electrical components. The interposer includes a bi-lobate contact pad made of an elastomeric material embedded with conductive metallic granules.

Abstract translation: 一种用于形成电气部件之间的电连接的改进的插入器。 插入器包括由嵌入有导电金属颗粒的弹性体材料制成的双叶接触垫。

公开(公告)号：US06809046B2

公开(公告)日：2004-10-26

申请号：US09795622

申请日：2001-02-28

Applicant: Vedagiri Velpari ,  Ernest L. Lawton ,  William B. Rice ,  Walter J. Robertson ,  Kami Lammon-Hilinski ,  Bruce E. Novich ,  Xiang Wu

Inventor： Vedagiri Velpari ,  Ernest L. Lawton ,  William B. Rice ,  Walter J. Robertson ,  Kami Lammon-Hilinski ,  Bruce E. Novich ,  Xiang Wu

IPC: D03D1500

CPC classification number: D03D15/00 ,  C03C25/00 ,  C03C25/10 ,  C03C25/47 ,  C03C25/48 ,  C08J5/08 ,  H05K1/0366 ,  H05K2201/0166 ,  H05K2201/0175 ,  H05K2201/0209 ,  H05K2201/0212 ,  H05K2201/0245 ,  H05K2201/029 ,  H05K2203/127 ,  Y10T442/2992 ,  Y10T442/3049 ,  Y10T442/3179 ,  Y10T442/3301 ,  Y10T442/3309 ,  Y10T442/699

Abstract: The present invention provides non-heat cleaned glass fiber fabrics comprising resin compatible coatings that offer higher tensile strengths than corresponding fabrics that have been heat cleaned and silane finished. These fabrics can be used in a wide variety of applications, such as reinforcements for composites such as printed circuit boards. In one nonlimiting embodiment, the invention provides a non-heat cleaned fabric comprising a plurality of fiber strands in a warp direction and a fill direction, each fiber strand comprising a plurality of E-glass fiber, and having a resin compatible coating composition on at least a portion of a surface of at least one fiber strand, wherein the fabric has a tensile strength of at least 267 Newtons when measured in the warp direction or fill direction. Although not required, the fabric also has a tensile strength of at least 1.5 times that of a corresponding fabric that is heat cleaned by heating the corresponding fabric to a temperature of at least 380° C. for at least 60 hours and silane finished when measured in the warp direction or fill direction.

Abstract translation: 本发明提供了包含树脂相容性涂层的非热清洁玻璃纤维织物，其具有比已被热清洁和硅烷完成的相应织物更高的拉伸强度。 这些织物可以用于各种各样的应用中，例如用于诸如印刷电路板的复合材料的增强材料。在一个非限制性实施方案中，本发明提供了一种非经热洗涤的织物，其包括经纱方向上的多条纤维束和填充物 方向，每个纤维束包含多个E玻璃纤维，并且在至少一根纤维股的表面的至少一部分上具有树脂相容的涂料组合物，其中所述织物在测量时具有至少267牛顿的拉伸强度 在经向或填充方向。 虽然不是必需的，但是织物的拉伸强度至少是相应织物的1.5倍，通过将相应的织物加热到至少380℃的温度至少60小时而被热清洗，并且当测量时硅烷完成 在经向或填充方向。

公开(公告)号：US06803528B1

公开(公告)日：2004-10-12

申请号：US10088982

申请日：2002-03-26

Applicant: Tatsunori Koyanagi

Inventor： Tatsunori Koyanagi

IPC: H05K111

CPC classification number: H05K3/421 ,  H05K3/388 ,  H05K3/4076 ,  H05K2201/0166 ,  H05K2201/0394 ,  H05K2201/09827 ,  H05K2203/0361 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: Disclosed herein are multi-layer double-sided wiring boards having an insulating layer with an opening, conductive layers on both surfaces of the insulating layer and on the inside of the opening, and an interface layer between the insulating layer and portions of the conductive layers wherein the conductive layers are in direct contact in the opening. Also disclosed are methods of fabricating such multi-layer double-sided wiring boards.

Abstract translation: 这里公开了具有开口的绝缘层，绝缘层的两个表面上的导电层和开口的内部的多层双面布线板，以及绝缘层与导电层的部分之间的界面层 其中导电层在开口中直接接触。 还公开了制造这种多层双面线路板的方法。

公开(公告)号：US20040000427A1

公开(公告)日：2004-01-01

申请号：US10184387

申请日：2002-06-27

Inventor： Alan E. Wang ,  Kevin C. Olson

IPC: H05K001/03 ,  H05K001/09 ,  B32B003/10 ,  H05K001/11 ,  H01R012/04 ,  B21B001/00 ,  B21C027/00 ,  B21D028/00 ,  G03F007/20 ,  G03F007/30 ,  G03F007/40

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2203/135 ,  Y10T29/49126 ,  Y10T29/49156 ,  Y10T29/49167 ,  Y10T428/12361 ,  Y10T428/24322

Abstract: Provided is a process for creating vias for a circuit assembly including the steps of (a) applying a curable coating composition to a substrate, some or all of which is electrically conductive, to form an uncured coating thereon; (b) applying a resist over the uncured coating; (c) imaging the resist in predetermined locations; (d) developing the resist to expose predetermined areas of the uncured coating; (e) removing the exposed areas of the uncured coating; and (f heating the coated substrate of step (e) to a temperature and for a time sufficient to cure the coating. Also disclosed is a process of fabricating a circuit assembly.

Abstract translation: 提供了一种用于创建电路组件的通孔的方法，包括以下步骤：（a）将可固化涂料组合物施加到基底上，其中一些或全部导电，以在其上形成未固化的涂层; （b）在未固化的涂层上涂覆抗蚀剂; （c）在预定位置对抗蚀剂进行成像; （d）显影抗蚀剂以暴露未固化涂层的预定区域; （e）去除未固化涂层的暴露区域; 和（f）将步骤（e）的涂布基材加热到足以固化涂层的温度和时间。还公开了一种制造电路组件的方法。

公开(公告)号：US06653056B2

公开(公告)日：2003-11-25

申请号：US09901246

申请日：2001-07-09

Applicant: John Haetak Choi

Inventor： John Haetak Choi

IPC: G03F726

CPC classification number: C04B41/009 ,  C04B41/4572 ,  C04B41/81 ,  G03F7/033 ,  G03F7/40 ,  H05K1/0306 ,  H05K3/002 ,  H05K2201/0166 ,  H05K2203/0786 ,  C04B41/4562 ,  C04B41/5031 ,  C04B35/581

Abstract: The invention is directed to a process for patterning ceramic tape wherein a photoresist is applied to a ceramic tape, which enables the photoresist, after being exposed patternwise, and developed, to act as a development mask for the tape. The tape then undergoes a development stage, which ultimately removes undesired sections of tape. The tape contains polymeric binder(s) with acidic or alkaline functional pendant groups but not photosensitive ingredients. Therefore, the tape is aqueous processable but itself cannot be photoimaged. However, when this tape is used with conventional photoresists that have the development chemistry opposite from that of the tape, it allows the photoresist to be used as a development barrier layer for the tape.