公开(公告)号：US20090311128A1

公开(公告)日：2009-12-17

申请号：US12374154

申请日：2007-06-20

Applicant: Yasuhiro Aruga ,  Ryoichi Ozaki ,  Yosuke Miwa

Inventor： Yasuhiro Aruga ,  Ryoichi Ozaki ,  Yosuke Miwa

IPC: C22C9/00 ,  C22C9/04 ,  C22C9/02

CPC classification number: C22C9/00 ,  C22C9/02 ,  C22C9/04 ,  C22F1/00 ,  C22F1/08 ,  H01L2924/0002 ,  H05K1/09 ,  H05K2201/0355 ,  H01L2924/00

Abstract: A shear plane ratio is reduced by a dislocation density in which a value obtained by dividing the half-value width β of the intensity of diffraction of {311} plane in the surface of a Cu—Fe—P alloy sheet, by its peak height H, is 0.015 or more.In addition, a Cu—Fe—P alloy sheet with relatively small Fe content is provided with a texture in which a ratio (I(200)/I(220)) of intensity of diffraction of (I(200)) from the (200) plane in the sheet surface to intensity of diffraction of (I(220)) from the (220) plane, is 0.3 or less.In addition, a Cu—Fe—P alloy sheet with relatively small Fe content is provided with a texture in which the orientation distribution density of Brass orientation measured by the crystal orientation analysis method using an EBSP by an FE-SEM, is 25% or more; and an average grain size in the sheet is 6.0 μm or less.

Abstract translation: 通过将Cu-Fe-P合金板的表面中{311}面的衍射强度的半值宽度β除以其峰值高度而得到的值的位错密度， H为0.015以上。 另外，具有Fe含量较低的Cu-Fe-P合金板具有（I（200））与（I（200））衍射强度的比（I（200）/ I（220） （220））的衍射强度为0.3以下。 此外，具有Fe含量较低的Cu-Fe-P合金板具有通过FE-SEM使用EBSP的结晶取向分析法测定的黄铜取向的取向分布密度为25％的结构， 更多; 平均粒径为6.0μm以下。

公开(公告)号：US07615477B2

公开(公告)日：2009-11-10

申请号：US11566956

申请日：2006-12-05

Applicant: John U. Knickerbocker ,  Voya R. Markovich ,  Thomas R. Miller ,  William J. Rudik

Inventor： John U. Knickerbocker ,  Voya R. Markovich ,  Thomas R. Miller ,  William J. Rudik

IPC: H01L31/058 ,  H01L23/495 ,  H01L23/48 ,  H01L21/44

CPC classification number: H05K1/0271 ,  H01L23/49866 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/384 ,  H05K3/4092 ,  H05K2201/0133 ,  H05K2201/0355 ,  H05K2203/0307 ,  H05K2203/1152 ,  H01L2924/00

Abstract: Ball Grid Array packages having decreased adhesion of the BGA pad to the laminate surface and methods for producing same are provided.

Abstract translation: 提供了具有降低的BGA焊盘与层压体表面的粘附性的球栅阵列封装及其制造方法。

公开(公告)号：US07615277B2

公开(公告)日：2009-11-10

申请号：US10986913

申请日：2004-11-15

Applicant: Kenji Takai ,  Norio Moriike ,  Kenichi Kamiyama ,  Katsuyuki Masuda ,  Kiyoshi Hasegawa

Inventor： Kenji Takai ,  Norio Moriike ,  Kenichi Kamiyama ,  Katsuyuki Masuda ,  Kiyoshi Hasegawa

IPC: B32B3/00

CPC classification number: H05K3/386 ,  C23C18/1608 ,  C23C18/1653 ,  C23C18/2093 ,  C23C18/31 ,  C25D5/022 ,  H05K3/108 ,  H05K3/244 ,  H05K3/427 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0154 ,  H05K2201/0355 ,  H05K2203/072 ,  Y10S428/901 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/12472 ,  Y10T428/12493 ,  Y10T428/12507 ,  Y10T428/12514 ,  Y10T428/12535 ,  Y10T428/24917

Abstract: A printed wiring board having a conductor circuit comprising a copper layer adjacent to an insulating layer and an electroless gold plating, wherein the insulating layer has ten-point mean surface roughness (Rz) of 2.0 μm or less is provided. According to the present invention, there is no such a defect that gold plating is deposited on a resin, and fine wiring formation with accuracy is realized.

Abstract translation: 一种印刷电路板，其具有包括与绝缘层相邻的铜层的导体电路和无电镀金，其中，绝缘层具有2.0μm或更小的十点平均表面粗糙度（Rz）。 根据本发明，没有在树脂上沉积镀金的缺陷，并且实现精确的精细布线形成。

公开(公告)号：US07605048B2

公开(公告)日：2009-10-20

申请号：US11697477

申请日：2007-04-06

Applicant: Gregory J. Dunn ,  Jovica Savic ,  Philip M. Lessner ,  Albert K. Harrington

Inventor： Gregory J. Dunn ,  Jovica Savic ,  Philip M. Lessner ,  Albert K. Harrington

IPC: H01L21/20 ,  H01G4/228

CPC classification number: H05K1/162 ,  H01G4/008 ,  H01G4/33 ,  H05K3/382 ,  H05K3/429 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2203/0315 ,  H05K2203/1536 ,  Y10T29/43

Abstract: High capacitance value capacitors are formed using bimetal foils of an aluminum layer attached to a copper layer. The copper side of a bimetallic copper/aluminum foil or a monometallic aluminum foil is temporarily protected using aluminum or other materials, to form a sandwich. The exposed aluminum is treated to increase the surface area of the aluminum by at least one order of magnitude, while not attacking any portion of the protected metal. When the sandwich is separated, the treated bimetal foil is formed into a capacitor, where the copper layer is one electrode of the capacitor and the treated aluminum layer is in intimate contact with a dielectric layer of the capacitor.

Abstract translation: 使用连接到铜层的铝层的双金属箔形成高电容值电容器。 双金属铜/铝箔或单金属铝箔的铜面用铝或其他材料暂时保护，形成三明治。 处理暴露的铝以将铝的表面积增加至少一个数量级，同时不侵蚀受保护金属的任何部分。 当三明治分离时，处理的双金属箔形成电容器，其中铜层是电容器的一个电极，并且经处理的铝层与电容器的电介质层紧密接触。

公开(公告)号：US07601181B2

公开(公告)日：2009-10-13

申请号：US11923974

申请日：2007-10-25

Applicant: William Borland ,  Ian Burn ,  Jon Fredrick Ihlefeld ,  Jon Paul Maria ,  Seigi Suh

Inventor： William Borland ,  Ian Burn ,  Jon Fredrick Ihlefeld ,  Jon Paul Maria ,  Seigi Suh

IPC: H01L21/8242 ,  H01G9/00

CPC classification number: H01L21/02197 ,  C01G23/006 ,  C01P2004/82 ,  C01P2006/40 ,  H01G4/1227 ,  H01G4/33 ,  H01L21/02337 ,  H01L21/31691 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T29/417 ,  Y10T29/435 ,  Y10T29/4913 ,  Y10T428/31678

Abstract: Described herein are methods for making articles comprising a dielectric layer formed from any solution composition that can form barium titanate during firing and containing manganese in an amount between 0.002 and 0.05 atom percent of the solution composition, wherein the dielectric layer has been formed on metal foil and fired in a reducing atmosphere.

Abstract translation: 本文描述了制备制品的方法，所述方法包括由任意溶液组合物形成的介电层，所述溶液组合物在焙烧期间可以形成钛酸钡并且含有0.002至0.05原子％的溶液组成的量，其中介电层已经形成在金属箔 并在还原气氛中开火。

公开(公告)号：US20090242256A1

公开(公告)日：2009-10-01

申请号：US12410685

申请日：2009-03-25

Applicant: Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

Inventor： Hitoshi Saita ,  Kenji Horino ,  Yasunobu Oikawa ,  Shinichiro Kakei

IPC: H05K1/18

CPC classification number: H05K1/162 ,  H05K2201/0355 ,  H05K2201/09509 ,  H05K2201/09763 ,  H05K2201/098

Abstract: In a dielectric element, the angle θ made by either the top face or the bottom face and the side faces is either 0°

Abstract translation: 在电介质元件中，由顶面或底面和侧面形成的角度θ为0°<89°，或91°<180°，并且为89°以外的角度 <=θ<= 91°。 通过这种方式，介电元件的侧面与玻璃环氧树脂基板和绝缘材料的接触面积增加，与树脂基板的粘附性提高，并且当埋在两个树脂之间时，可以提高强度和可靠性 底物。

公开(公告)号：US07592626B2

公开(公告)日：2009-09-22

申请号：US11635000

申请日：2006-12-07

Applicant: Yumiko Ozaki ,  Osamu Shinoura

Inventor： Yumiko Ozaki ,  Osamu Shinoura

IPC: H01L27/108

CPC classification number: H01G4/206 ,  H01L28/55 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/1105 ,  H05K2203/135

Abstract: A capacitor comprises: a lower electrode formed of a foil made of a polycrystalline metal; an upper conductor layer; and a dielectric layer disposed between the lower electrode and the upper electrode layer. Grain boundaries of the polycrystalline metal appear at the top surface of the lower electrode. The capacitor further comprises an insulator that is disposed between the top surface of the dielectric layer and the bottom surface of the upper electrode layer and that is present only in part of a region in which the top surface of the dielectric layer and the bottom surface of the upper electrode layer face each other. The insulator is disposed to cover at least part of the grain boundaries appearing at the top surface of the lower electrode when seen from above the top surface of the dielectric layer. The insulator is formed by electrophoresis.

Abstract translation: 电容器包括：由多晶金属制成的箔形成的下电极; 上导体层; 以及设置在下电极和上电极层之间的电介质层。 多晶金属的晶界出现在下电极的顶表面。 电容器还包括设置在电介质层的顶表面和上电极层的底表面之间的绝缘体，并且其仅存在于介电层的顶表面和底表面的部分区域中的一部分 上电极层彼此面对。 当从电介质层的顶表面上方观察时，绝缘体设置成覆盖出现在下电极的顶表面处的晶界的至少一部分。 绝缘体通过电泳形成。

公开(公告)号：US20090205852A1

公开(公告)日：2009-08-20

申请号：US12193460

申请日：2008-08-18

Applicant: Chun-Chien Chen ,  Tsung-Yuan Chen

Inventor： Chun-Chien Chen ,  Tsung-Yuan Chen

IPC: H05K1/00 ,  H05K3/02

CPC classification number: H05K3/44 ,  H05K3/20 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/445 ,  H05K2201/0355 ,  H05K2201/0376 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2203/0369 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A manufacturing method of a circuit board is provided. A metal core is provided. A conductive layer is formed on each of some carriers. The carriers and dielectric layers are laminated at both sides of the metal core to form a stacked structure. Each of the dielectric layers is located between the corresponding carrier and the metal core, and a portion of the conductive layer is embedded in the corresponding dielectric layer. Then, the carriers are removed. A blind via and/or a through via are/is formed in the stacked structure to connect the corresponding conductive layer and the metal core and/or connect the conductive layers at both sides of the metal core, wherein the through via penetrates the metal core. The conductive layer on a surface of the dielectric layer is removed.

Abstract translation: 提供电路板的制造方法。 提供金属芯。 在一些载体的每一个上形成导电层。 载体和电介质层被层叠在金属芯的两侧以形成堆叠结构。 每个电介质层位于相应的载体和金属芯之间，并且导电层的一部分嵌入相应的介电层中。 然后，移除载体。 在堆叠结构中形成盲通孔和/或通孔，以将相应的导电层和金属芯连接和/或连接金属芯两侧的导电层，其中通孔穿过金属芯 。 去除介电层表面上的导电层。

公开(公告)号：US20090183909A1

公开(公告)日：2009-07-23

申请号：US12382293

申请日：2009-03-12

Applicant: Soon-Jin CHO

Inventor： Soon-Jin CHO

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L2224/16225 ,  H05K1/0206 ,  H05K3/06 ,  H05K3/4644 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/1536 ,  Y10T29/49124 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: A coreless substrate having a plurality of function pads, etched from a metal sheet and having a protruded shape; an insulating layer, the insulating layer being formed on one side of the function pads, a circuit corresponding to a pattern being formed on the insulating layer, a via hole being formed on the insulating layer to electrically connect the function pads and the circuit; and a solder resist, being formed on the insulating layer to protect the surface of the insulating layer. The coreless substrate has a signal delivery characteristic that is improved by eliminating the inner via hole.

Abstract translation: 一种无芯基板，具有从金属板蚀刻并具有突出形状的多个功能垫; 绝缘层，所述绝缘层形成在所述功能焊盘的一侧上，对应于在所述绝缘层上形成的图案的电路，形成在所述绝缘层上以电连接所述功能焊盘和所述电路的通孔; 和阻焊层，形成在绝缘层上以保护绝缘层的表面。 无芯基板具有通过消除内通孔而改善的信号传递特性。

公开(公告)号：US07561406B2

公开(公告)日：2009-07-14

申请号：US11730154

申请日：2007-03-29

Applicant: Hitoshi Saita ,  Yuko Saya ,  Kiyoshi Uchida ,  Kenji Horino

Inventor： Hitoshi Saita ,  Yuko Saya ,  Kiyoshi Uchida ,  Kenji Horino

IPC: H01G4/008 ,  H01G4/06 ,  H01G7/00

CPC classification number: H01G4/008 ,  H01G4/33 ,  H01L27/016 ,  H01L27/0682 ,  H01L27/0802 ,  H01L27/0811 ,  H01L28/55 ,  H05K1/09 ,  H05K1/162 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0355 ,  Y10T29/417 ,  Y10T29/435

Abstract: A thin film capacitor with high capacity and low leak current is provided. The thin film capacitor includes a nickel substrate with nickel (Ni) purity of 99.99 weight percent or above, and a dielectric layer and an electrode layer disposed in this order on the nickel substrate. The thin film capacitor is typically manufactured as follows. A precursor dielectric layer is formed on a nickel substrate with nickel purity of 99.99 weight percent or above, and is subjected to annealing to form a dielectric layer. The diffusion of impurities from the nickel substrate to the precursor dielectric layer during annealing is suppressed.

Abstract translation: 提供了具有高容量和低漏电流的薄膜电容器。 薄膜电容器包括镍（Ni）纯度为99.99重量％以上的镍基板，以及依次设置在镍基板上的电介质层和电极层。 薄膜电容器通常如下制造。 在镍基底上形成前体电介质层，其镍纯度为99.99重量％以上，并进行退火以形成电介质层。 抑制了退火时的杂质从镍基体向前体电介质层的扩散。