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公开(公告)号：US20170005424A1
公开(公告)日：2017-01-05
申请号：US15150673
申请日：2016-05-10
Applicant: BELLWETHER ELECTRONIC CORP
Inventor： HSING-YU LEE , HAN-MIN LEE
CPC classification number: H01R12/778 , H01R12/775 , H05K1/147 , H05K2201/0397
Abstract: An assembly of cable and connector includes a flat flexible cable, an input-output connector and a paddle card. The flat flexible cable has parallel conductor wires, an insulated layer wrapped around the conductor wires. The conductor wires have at least one first integrated power wire and signal wires. A width of the first integrated power wire is larger than two times the width of one signal wire. The input-output connector has terminals separated into an upper-side terminal and a lower-side terminal. A number of the terminals is larger than a number of the conductor wires. The paddle card has a base board, and transferring circuits distributed on the base board. The transferring circuits has first pads on one side of the base board which are correspondingly connected to the conductor wires, and second pads on the other side of the base board which are correspondingly connected to the terminals.
Abstract translation: 电缆和连接器的组件包括扁平柔性电缆，输入 - 输出连接器和桨形卡。 扁平柔性电缆具有平行的导线，缠绕在导线上的绝缘层。 导线具有至少一个第一集成电力线和信号线。 第一集成电力线的宽度大于一个信号线的宽度的两倍。 输入输出连接器具有分为上侧端子和下侧端子的端子。 多个端子大于多个导线。 桨卡具有基板和分布在基板上的传输电路。 传输电路在基板的一侧上具有相应地连接到导线的第一焊盘，以及对应地连接到端子的基板的另一侧上的第二焊盘。
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152.发明授权公开(公告)号：US09468101B2
公开(公告)日：2016-10-11
申请号：US14659977
申请日：2015-03-17
Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.
Inventor： Kuo-Fu Su , Gwun-Jin Lin
CPC classification number: H05K1/115 , H05K1/0251 , H05K1/092 , H05K3/06 , H05K3/4038 , H05K3/4069 , H05K2201/0397 , H05K2201/09845 , H05K2201/09854
Abstract: Disclosed urea microvia structure of a flexible circuit board and a manufacturing method thereof. A first through hole is formed in a first conductive layer of a flexible circuit board and a first exposed zone is defined. A second conductive layer includes a second through hole formed therein and defines a second exposed zone. A dielectric layer includes a dielectric layer through hole corresponding to the second through hole of the second conductive layer. A conductive paste layer is filled in the second through hole of the second conductive layer, the dielectric layer through hole of the dielectric layer, and the first through hole of the first conductive layer in such a way that the conductive paste layer covers and electrically contacts the first exposed zone of the first conductive layer and the second exposed zone of the second conductive layer.
Abstract translation: 柔性电路板的尿素微孔结构及其制造方法。 在柔性电路板的第一导电层中形成第一通孔，并且限定第一暴露区域。 第二导电层包括形成在其中的第二通孔并且限定第二暴露区域。 电介质层包括与第二导电层的第二通孔对应的电介质层通孔。 导电膏层填充在第二导电层的第二通孔，电介质层的电介质层通孔和第一导电层的第一通孔中，导电膏层覆盖并电接触 第一导电层的第一暴露区域和第二导电层的第二暴露区域。
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153.发明申请公开(公告)号：US20160183371A1
公开(公告)日：2016-06-23
申请号：US14659977
申请日：2015-03-17
Applicant: ADVANCED FLEXIBLE CIRCUITS CO., LTD.
Inventor： KUO-FU SU , GWUN-JIN LIN
CPC classification number: H05K1/115 , H05K1/0251 , H05K1/092 , H05K3/06 , H05K3/4038 , H05K3/4069 , H05K2201/0397 , H05K2201/09845 , H05K2201/09854
Abstract: Disclosed urea microvia structure of a flexible circuit board and a manufacturing method thereof. A first through hole is formed in a first conductive layer of a flexible circuit board and a first exposed zone is defined. A second conductive layer includes a second through hole formed therein and defines a second exposed zone. A dielectric layer includes a dielectric layer through hole corresponding to the second through hole of the second conductive layer. A conductive paste layer is filled in the second through hole of the second conductive layer, the dielectric layer through hole of the dielectric layer, and the first through hole of the first conductive layer in such a way that the conductive paste layer covers and electrically contacts the first exposed zone of the first conductive layer and the second exposed zone of the second conductive layer.
Abstract translation: 柔性电路板的尿素微孔结构及其制造方法。 在柔性电路板的第一导电层中形成第一通孔，并且限定第一暴露区域。 第二导电层包括形成在其中的第二通孔并且限定第二暴露区域。 电介质层包括与第二导电层的第二通孔对应的电介质层通孔。 导电膏层填充在第二导电层的第二通孔，电介质层的电介质层通孔和第一导电层的第一通孔中，导电膏层覆盖并电接触 第一导电层的第一暴露区域和第二导电层的第二暴露区域。
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公开(公告)号：US20160172622A1
公开(公告)日：2016-06-16
申请号：US14904875
申请日：2014-07-24
Applicant: LG CHEM, LTD.
Inventor： Ducksu OH , Minsoo KANG
CPC classification number: H01L51/5246 , H01L27/3276 , H01L51/0097 , H01L51/5203 , H05K1/028 , H05K1/11 , H05K1/118 , H05K1/14 , H05K1/147 , H05K1/189 , H05K3/32 , H05K3/323 , H05K3/361 , H05K3/363 , H05K2201/0397 , H05K2201/058 , H05K2201/09418 , H05K2201/10106 , H05K2201/10128 , H05K2203/049
Abstract: An organic light emitting diode including a structure of a flexible printed circuit board installed on a substrate is provided.
Abstract translation: 提供一种包括安装在基板上的柔性印刷电路板的结构的有机发光二极管。
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155.发明授权High speed circuit assembly with integral terminal and mating bias loading electrical connector assembly 有权具有集成端子和配合偏置负载电连接器组件的高速电路组件公开(公告)号：US09350124B2
公开(公告)日：2016-05-24
申请号：US14408039
申请日：2013-03-13
Applicant: HSIO TECHNOLOGIES, LLC
Inventor： James Rathburn
IPC: H01R12/68 , H01R12/50 , H01R13/24 , H01R12/82 , H05K3/36 , H05K3/40 , H01R12/73 , H01L23/00 , H05K1/09 , H05K1/11 , H05K1/18 , H05K3/00 , H05K3/42 , H05K3/46
CPC classification number: H01R23/6813 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01R12/73 , H01R12/82 , H01R13/2457 , H01R13/2485 , H01R31/06 , H05K1/092 , H05K1/111 , H05K1/141 , H05K1/182 , H05K3/0094 , H05K3/10 , H05K3/1291 , H05K3/326 , H05K3/363 , H05K3/365 , H05K3/4007 , H05K3/4015 , H05K3/4092 , H05K3/425 , H05K3/4694 , H05K7/1076 , H05K2201/0397 , H05K2201/048 , H05K2201/09381 , H05K2201/09545 , H05K2201/09563 , H05K2201/09854 , H05K2201/10378 , H05K2201/10386 , H05K2201/2072 , H05K2201/209 , H05K2203/041 , H05K2203/1476 , Y10T29/49165 , H01L2224/45099 , H01L2924/00
Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。
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Patent Agency Ranking
156.发明申请ARRANGEMENT AND METHOD FOR CONNECTING AN ELECTRICAL COMPONENT TO A LEADFRAME 审中-公开将电气部件连接到引线框架的布置和方法公开(公告)号：US20160103147A1
公开(公告)日：2016-04-14
申请号：US14878644
申请日：2015-10-08
Applicant: Continental Automotive Systems, Inc.
Inventor： Gaetan Vich
CPC classification number: G01P1/026 , G01P3/42 , H01R4/28 , H05K3/28 , H05K3/326 , H05K2201/0397 , H05K2201/10151 , H05K2201/10386 , H05K2201/10446 , H05K2201/10757 , H05K2203/1316 , H05K2203/1327
Abstract: An automotive component assembly comprises an input circuit portion for a sensor and a component portion. The input circuit portion is aligned with the component portion in a desired assembly position. A pocket is at least partially defined by the component portion to receive the input circuit portion and a clamping force retains the input circuit portion between a first layer and a second layer of the component portion forming the pocket. An overmold material is applied to retain the input circuit portion and the component portion to one another.
Abstract translation: 汽车部件组件包括用于传感器的输入电路部分和部件部分。 输入电路部分与组件部分对准在期望的组装位置。 口袋至少部分地由部件限定以接收输入电路部分，并且夹紧力将输入电路部分保持在形成口袋的部件部分的第一层和第二层之间。 施加包覆成型材料以将输入电路部分和部件部分保持彼此。
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公开(公告)号：US09207490B2
公开(公告)日：2015-12-08
申请号：US14012560
申请日：2013-08-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Hoon Choi , Kwang-youn Kim
CPC classification number: G02F1/133603 , G02B6/0083 , G02B6/009 , G09G3/3406 , H05K1/115 , H05K1/181 , H05K2201/0397 , H05K2201/10106 , H05K2201/10189 , Y02P70/611
Abstract: A backlight apparatus includes a substrate which includes a plurality of layers. A plurality of light emitting modules are arranged on a top layer of the plurality of layers closest to a light guide panel, and a plurality of wires penetrates through the plurality of layers to electrically connect the light emitting modules and a plurality of driving units. Accordingly, the width of the substrate of an edge type backlight apparatus which can provide local dimming is reduced. Therefore, the display apparatus using the edge type backlight apparatus can be slim even if it is designed to provide local dimming.
Abstract translation: 背光装置包括具有多层的基板。 多个发光模块布置在最靠近导光板的多个层的顶层上，并且多根导线穿过多层以电连接发光模块和多个驱动单元。 因此，可以提供能够提供局部调光的边缘型背光装置的基板的宽度。 因此，即使设计为提供局部调光，使用边缘型背光装置的显示装置也可以是纤细的。
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158.发明申请METHOD AND APPARATUS FOR MECHANICAL LOAD REDUCTION ON THE ELECTRICAL TERMINALS OF A CAPACITOR 有权机电负载减少对电容器电气终端的方法和装置公开(公告)号：US20150313002A1
公开(公告)日：2015-10-29
申请号：US14263681
申请日：2014-04-28
Applicant: GENERAL ELECTRIC COMPANY
Inventor： ANDREW LOUIS KRIVONAK , PATRICK LEE JANSEN , MARK ALLEN MURPHY , FRANK DOLSKI
CPC classification number: H05K1/028 , H01G2/02 , H01G2/065 , H01G2/106 , H01G4/228 , H05K1/181 , H05K3/30 , H05K5/0026 , H05K7/1432 , H05K2201/0397 , H05K2201/10015 , H05K2201/10272
Abstract: In an embodiment, an apparatus for reducing the mechanical load on the electrical terminals of a capacitor includes a plate having a planar body and one or more deflectable tabs connected to the planar body, one or more capacitors respectively mounted to the plate via the one or more deflectable tabs, and a busbar electrically connected to the one or more capacitors such that the one or more capacitors are arranged intermediate the plate and the busbar. The deflectable tabs are configured to support the capacitors, and to move towards and away from the planar body for accommodating size variances in the capacitors relative to a fixed spacing between the busbar and an enclosure.
Abstract translation: 在一个实施例中，用于减小电容器的电端子上的机械负载的装置包括具有平面主体的板和连接到平面主体的一个或多个可偏转突片，一个或多个电容器分别经由一个或多个 更可偏转的接片和与该一个或多个电容器电连接的母线，使得一个或多个电容器布置在板和母线之间。 可偏转突片被构造成支撑电容器，并且朝向和远离平面主体移动，以相对于母线和外壳之间的固定间隔来容纳电容器中的尺寸变化。
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公开(公告)号：US09054669B2
公开(公告)日：2015-06-09
申请号：US14256148
申请日：2014-04-18
Applicant: MediaTek Inc.
Inventor： Hsiao-Ting Huang , Cheng-Hao Kuo
CPC classification number: H03H7/0138 , H01P1/203 , H05K1/0218 , H05K2201/0397
Abstract: In an embodiment of the disclosure, an electronic device arranged for eliminating wireless noise interference is provided. The electronic device includes a circuit board and two first metal components. The metal components are arranged on different sides of the circuit board. Each of the first metal components comprises a first terminal and a second terminal opposite to the first terminal. The first terminal is coupled to the circuit board and the second terminal is open loop. The length of the first metal component is about one-fourth wavelength of a pre-determined frequency.
Abstract translation: 在本公开的实施例中，提供了一种用于消除无线噪声干扰的电子设备。 电子设备包括电路板和两个第一金属部件。 金属部件布置在电路板的不同侧。 每个第一金属部件包括与第一端子相对的第一端子和第二端子。 第一端子耦合到电路板，第二端子是开环的。 第一金属部件的长度约为预定频率的四分之一波长。
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160.发明申请HIGH SPEED CIRCUIT ASSEMBLY WITH INTEGRAL TERMINAL AND MATING BIAS LOADING ELECTRICAL CONNECTOR ASSEMBLY 有权具有整体端子和负极偏置电气连接器总成的高速电路组件公开(公告)号：US20150136467A1
公开(公告)日：2015-05-21
申请号：US14408039
申请日：2013-03-13
Applicant: HSIO TECHNOLOGIES, LLC
Inventor： James Rathburn
CPC classification number: H01R23/6813 , H01L24/16 , H01L24/48 , H01L2224/16225 , H01L2224/45144 , H01L2224/48091 , H01L2924/00014 , H01L2924/12042 , H01L2924/15311 , H01R12/73 , H01R12/82 , H01R13/2457 , H01R13/2485 , H01R31/06 , H05K1/092 , H05K1/111 , H05K1/141 , H05K1/182 , H05K3/0094 , H05K3/10 , H05K3/1291 , H05K3/326 , H05K3/363 , H05K3/365 , H05K3/4007 , H05K3/4015 , H05K3/4092 , H05K3/425 , H05K3/4694 , H05K7/1076 , H05K2201/0397 , H05K2201/048 , H05K2201/09381 , H05K2201/09545 , H05K2201/09563 , H05K2201/09854 , H05K2201/10378 , H05K2201/10386 , H05K2201/2072 , H05K2201/209 , H05K2203/041 , H05K2203/1476 , Y10T29/49165 , H01L2224/45099 , H01L2924/00
Abstract: A method of making an array of integral terminals on a circuit assembly. The method includes the steps of depositing at least a first liquid dielectric layer on the first surface of a first circuit member, imaged to include a plurality of first recesses corresponding to the array of integral terminals. The selected surfaces of the first recesses are processed to accept electro-less conductive plating deposition. Electro-lessly plating is applied to the selected surfaces of the first recesses to create a plurality of first conductive structures electrically coupled to, and extending generally perpendicular to, the first circuitry layer. Electro-plating is applied to the electro-less plating to substantially first recesses with a conductive material. The steps of depositing, processing, electro-less plating, and electro-plating are repeated to form the integral terminals of a desired shape. The dielectric layers are removed to expose the terminals.
Abstract translation: 一种在电路组件上制成集成端子阵列的方法。 该方法包括以下步骤：在第一电路构件的第一表面上沉积至少第一液体电介质层，成像为包括与集成端子阵列相对应的多个第一凹部。 处理第一凹槽的选定表面以接受无电导电电镀沉积。 对所述第一凹槽的所选择的表面施加无电镀以产生电耦合到所述第一电路层并且大致垂直于所述第一电路层延伸的多个第一导电结构。 使用导电材料将电镀施加到基本上第一凹部的无电镀。 重复沉积，加工，无电镀和电镀的步骤以形成所需形状的整体端子。 去除电介质层以露出端子。
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