公开(公告)号：US20050164531A1

公开(公告)日：2005-07-28

申请号：US10764898

申请日：2004-01-26

Applicant: Henry Wong

Inventor： Henry Wong

IPC: H01R12/00 ,  H01R12/71 ,  H05K1/14 ,  H05K3/30

CPC classification number: H05K3/308 ,  H01R12/724 ,  H05K1/141 ,  H05K2201/09409 ,  H05K2201/10189 ,  H05K2201/10446 ,  H05K2201/10515

Abstract: A board module (401) can include a board module surface (420) and a connector (403) coupled to the board module surface, wherein the connector is coupled to provide at least one signal (112, 114) to the board module. The connector can include a connector lead surface (419) substantially perpendicular to the board module surface (420); a first row of leads (430) substantially parallel to and a first distance (451) from the board module surface extending substantially perpendicular from the connector lead surface (419) and shaped to connect substantially perpendicular to the board module surface at a second distance (452) from the connector lead surface; and a second row of leads (440) substantially parallel to and a third distance (453) from the board module surface extending substantially perpendicular from the connector lead surface (419) and shaped to connect substantially perpendicular to the board module surface (420) at a fourth distance (454) from the connector lead surface. The first distance is greater than the third distance, the second distance is less than the fourth distance, and each of the second row leads are offset from each of the first row of leads.

Abstract translation: 板模块（401）可以包括耦合到板模块表面的板模块表面（420）和连接器（403），其中连接器被耦合以向板模块提供至少一个信号（112,114）。 连接器可以包括基本上垂直于板模块表面（420）的连接器引线表面（419）。 基本上平行于第一排引线（430）并且离开板模块表面的第一距离（451），该第一距离基本上垂直于连接器引线表面（419）延伸并成形为在第二距离（基本上垂直于基板垂直于板模块表面） 452）从连接器引线表面; 以及基本上平行于所述板模块表面延伸的第二排引线（440）和从所述连接器引线表面（419）基本上垂直延伸的第三距离（453），并且被成形为基本垂直于所述板模块表面（420）连接 与连接器引线表面的第四距离（454）。 所述第一距离大于所述第三距离，所述第二距离小于所述第四距离，并且所述第二行引线中的每一个从所述第一排引线偏移。

公开(公告)号：US20050007806A1

公开(公告)日：2005-01-13

申请号：US10910979

申请日：2004-08-03

Applicant: Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

Inventor： Chris Martin ,  Brent Keeth ,  Brian Johnson ,  Walter Moden

IPC: G11C5/00 ,  H05K1/18 ,  G11C7/00

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

Abstract translation: 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US06835896B2

公开(公告)日：2004-12-28

申请号：US10103804

申请日：2002-03-25

Applicant: Kwang-Jo Hwang ,  Woo-Hyun Kim

Inventor： Kwang-Jo Hwang ,  Woo-Hyun Kim

IPC: H05K103

CPC classification number: G02F1/13452 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/117 ,  H05K1/118 ,  H05K3/361 ,  H05K3/4644 ,  H05K2201/0919 ,  H05K2201/09409 ,  H05K2201/09727 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A packaging structure of a driving circuit for a liquid crystal display device includes a base film, a plurality of first metal lines formed on the base film and arranged to have a certain distance between neighboring first metal lines, an insulating film on the first metal lines, wherein the insulating film exposes both ends of the first metal lines, a plurality of second metal lines on the insulating film, wherein the second metal lines are formed parallel to the first metal lines and an overcoat layer on the second metal lines and exposing ends of the first and second metal lines.

Abstract translation: 一种用于液晶显示装置的驱动电路的封装结构，包括基膜，形成在基膜上的多个第一金属线，并且被布置成在相邻的第一金属线之间具有一定距离，在第一金属线上具有绝缘膜 其中，所述绝缘膜暴露所述第一金属线的两端，在所述绝缘膜上暴露多个第二金属线，其中所述第二金属线形成为平行于所述第一金属线，并且所述第二金属线上的外涂层和所述第二金属线的暴露端 的第一和第二金属线。

公开(公告)号：US20040242027A1

公开(公告)日：2004-12-02

申请号：US10853493

申请日：2004-05-26

Applicant: NEC Electronics Corporation

Inventor： Masaru Tanokura ,  Yukio Yanagita

IPC: H01R012/00

CPC classification number: H01L24/06 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/06153 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01R4/027 ,  H01R43/0249 ,  H05K1/0268 ,  H05K1/0393 ,  H05K2201/09381 ,  H05K2201/09409 ,  H05K2201/10681 ,  H05K2203/1545 ,  H01L2224/45099 ,  H01L2924/00012

Abstract: A semiconductor device has a plurality of first pads to a plurality of fourth pads laid out in a first direction, thereby forming first to fourth pad rows. The first to fourth pad rows are laid out in the named order in a second direction orthogonal to the first direction. First to fourth leads are respectively connected between the first to fourth pad rows and a semiconductor chip. A first slanted side inclined to the first direction is formed at each second pad at that corner which lies on that side of the third pad row. A second slanted side inclined to the second direction in such a way as to face the first slanted side is formed at each third pad. Each first lead has a first slanted portion provided between the first slanted side and the second slanted side and extending in a direction oblique to the first direction.

Abstract translation: 半导体器件具有多个第一焊盘，至多布置在第一方向上的第四焊盘，从而形成第一至第四焊盘行。 在与第一方向正交的第二方向上，以所述顺序布置第一至第四焊盘行。 第一至第四引线分别连接在第一至第四焊盘行和半导体芯片之间。 在位于第三垫排的该侧的拐角处的每个第二垫处形成有朝向第一方向倾斜的第一倾斜面。 在每个第三垫处形成有朝向第一倾斜侧的方式倾斜到第二方向的第二倾斜面。 每个第一引线具有设置在第一倾斜侧和第二倾斜侧之间并沿与第一方向倾斜的方向延伸的第一倾斜部。

公开(公告)号：US20040136229A1

公开(公告)日：2004-07-15

申请号：US10674082

申请日：2003-09-26

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley JR.

IPC: G11C011/00

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

公开(公告)号：US20040076030A1

公开(公告)日：2004-04-22

申请号：US10273869

申请日：2002-10-17

Inventor： Chris G. Martin ,  Brent Keeth ,  Brian Johnson ,  Walter L. Moden

IPC: G11C005/06

CPC classification number: H05K1/181 ,  G11C5/04 ,  G11C5/06 ,  H05K1/112 ,  H05K2201/09409 ,  H05K2201/10159 ,  H05K2201/10545 ,  H05K2201/10689 ,  Y02P70/611

Abstract: The present invention is directed to a system, a module, and an apparatus and method for forming a microelectronic memory device. In one embodiment, a system includes a processor and a controller coupled to the processor with at least one memory module coupled to the controller, the module including a pair of memory devices oppositely positioned on respective surfaces of a substrate and interconnected by members extending through the substrate that couple terminals of the devices, the terminals being selected to include a group of terminals that are configured to communicate functionally compatible signals.

Abstract translation: 本发明涉及一种用于形成微电子存储器件的系统，模块以及装置和方法。 在一个实施例中，系统包括处理器和耦合到处理器的控制器，其中至少一个存储器模块耦合到控制器，该模块包括一对存储器件，其相对地定位在衬底的相应表面上并且通过延伸穿过 耦合器件的端子的基板，所述端子被选择为包括被配置为传送功能兼容的信号的一组端子。

公开(公告)号：US20040057269A1

公开(公告)日：2004-03-25

申请号：US10674240

申请日：2003-09-29

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley JR.

IPC: G11C027/00

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

公开(公告)号：US20030171015A1

公开(公告)日：2003-09-11

申请号：US10213771

申请日：2002-08-06

Inventor： Iosif R. Korsunsky ,  Kevin E. Walker ,  Joanne E. Shipe ,  Wei-Chen Lee ,  Tod M. Harlan ,  Robert W. Brown

IPC: H01R004/66

CPC classification number: H01R12/721 ,  H05K1/117 ,  H05K3/3405 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2203/0545

Abstract: An electrical connector (1) straddle-mounted on an edge (20) of a printed circuit board (2) includes an insulative housing (10) having an elongated groove (11) for mating. A support subassembly (3) is inserted from the opposing side of the housing (10) to expose its portions in the groove (11). The support subassembly (3) includes two bases (30) with attached signal conductors (5) and a U-shaped ground member (4). Two parallel-arranged side portions (40) of the U-shaped ground member (4) are integrally connected via its central portion and each of them is located parallel to a row of signal conductors (5) as their ground reference. The united ground member (4) can be used to establish ground path to the printed circuit board (2) by fewer contacting legs (42) sheared therefrom and help all parts of the support subassembly (3) to be installed in the connector housing (10) at one time.

Abstract translation: 跨接在印刷电路板（2）的边缘（20）上的电连接器（1）包括具有用于配合的细长槽（11）的绝缘壳体（10）。 支撑子组件（3）从壳体（10）的相对侧插入以暴露其凹槽（11）中的部分。 支撑子组件（3）包括具有附接信号导体（5）和U形接地构件（4）的两个基座（30）。 U形接地构件（4）的两个平行布置的侧部（40）经由其中心部分一体地连接，并且它们中的每一个平行于作为其接地基准的一行信号导体（5）。 联合接地构件（4）可用于通过较少的从其剪切的接触腿（42）来建立到印刷电路板（2）的接地路径，并且帮助支撑子组件（3）的所有部分安装在连接器壳体 10）一次。

公开(公告)号：US20030171012A1

公开(公告)日：2003-09-11

申请号：US10214014

申请日：2002-08-06

Inventor： Iosif R. Korsunsky ,  Kevin E. Walker ,  Joanne E. Shipe ,  Wei-Chen Lee ,  Tod M. Harlan ,  Robert W. Brown

IPC: H01R012/00

CPC classification number: H01R12/721 ,  H05K1/117 ,  H05K3/3405 ,  H05K3/3484 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2203/0545

Abstract: An electrical connector (1) straddle-mounted on an edge (20) of a printed circuit board (2) includes an insulative housing (10) having an elongated groove (11) for mating. A plurality of receiving channels (13) each used to receive a support subassembly (3) is formed adjacently to and communicated with the mating groove (11). The support subassembly (3) includes a base (30) with signal contacts (5) and a ground member (4) attached thereon. Every contact (5) includes an engaging end (51) exposed to the mating groove (11) and a tail end (52) extending out of the receiving channel (13) in a suspended status. And the ground member (4) includes a plurality of contacting legs (42) extending from the ground member (4) and being arranged to stagger with the tail end (52) of every contact (5) along the lengthwise of the connector (1). Several holding elements (43) are formed in a hook shape on one edge side of the ground member (4) to hook and be partially inserted into the apertures (22) formed on the housing (10) to stop further insertion of the support subassembly (3), and the holding elements (43) of the neighboring ground member (4) are inserted in the same apertures (22) so that they can establish a common ground path to reduce their needed contacting legs (42) to the printed circuit board (2).

Abstract translation: 跨接在印刷电路板（2）的边缘（20）上的电连接器（1）包括具有用于配合的细长槽（11）的绝缘壳体（10）。 每个用于接收支撑子组件（3）的多个接收通道（13）形成为与配合凹槽（11）相邻并与其相连通。 支撑子组件（3）包括具有信号触头（5）的基座（30）和附接在其上的接地构件（4）。 每个触点（5）包括暴露于配合凹槽（11）的接合端（51）和悬挂状态下从接收通道（13）延伸的尾端（52）。 并且所述接地构件（4）包括从所述接地构件（4）延伸的多个接触腿（42），并且布置成沿着连接器（1）的纵向与每个接触件（5）的尾端（52）交错 ）。 几个保持元件（43）在接地构件（4）的一个边缘侧上形成为钩状，以钩挂并部分地插入形成在壳体（10）上的孔（22）中，以阻止支撑子组件的进一步插入 （3），并且相邻接地构件（4）的保持元件（43）插入相同的孔（22）中，使得它们可以建立公共接地路径，以将它们所需的接触腿（42）减小到印刷电路 板（2）。

公开(公告)号：US20030169614A1

公开(公告)日：2003-09-11

申请号：US10094512

申请日：2002-03-07

Inventor： Jayesh R. Bhakta ,  Robert S. Pauley JR.

IPC: G11C005/02

CPC classification number: H05K1/181 ,  H05K1/0266 ,  H05K2201/09409 ,  H05K2201/09709 ,  H05K2201/10689 ,  Y02P70/611

Abstract: Integrated circuits utilizing standard commercial packaging are arranged on a printed circuit board to allow the production of 1-Gigabyte and 2-Gigabyte capacity memory modules. A first row of integrated circuits is oriented in an opposite orientation to a second row of integrated circuits. The integrated circuits in a first half of the first row and in the corresponding half of the second row are connected via a signal trace to a first register. The integrated circuits in a second half of the first row and in the corresponding half of the second row are connected to a second register. Each register processes a non-contiguous subset of the bits in each data word.

Abstract translation: 使用标准商业包装的集成电路布置在印刷电路板上，以允许生产1千兆字节和2千兆字节容量的存储器模块。 第一排集成电路定向成与第二排集成电路相反的方向。 第一行的前半部分和第二行的相应一半中的集成电路经由信号迹线连接到第一寄存器。 第一行的后半部分和第二行的相应一半中的集成电路连接到第二寄存器。 每个寄存器处理每个数据字中位的不连续子集。