公开(公告)号：US20020014346A1

公开(公告)日：2002-02-07

申请号：US09872256

申请日：2001-06-01

Applicant: NEC Corporation

Inventor： Kimio Tsunemasu ,  Yasunori Tanaka

IPC: H02G003/08

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L2224/13 ,  H01L2924/00014 ,  H05K1/112 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09572 ,  Y02P70/613 ,  H01L2224/0401

Abstract: A mounting structure of a semiconductor package can improve resistance against thermal and mechanical external force. The mounting structure of a semiconductor package establishes electrical connection of a pad on a printing circuit board to a connection wiring by soldering the semiconductor package. The pad may be integrally formed with a via. The soldering may be performed by penetrating a part of solder within the via so that the connection wiring is connected to the pad through the via at a layer different from a layer of the pad.

Abstract translation: 半导体封装的安装结构可以提高对热和机械外力的抵抗力。 半导体封装的安装结构通过焊接半导体封装而将印刷电路板上的焊盘电连接到连接布线。 垫可以与通孔一体地形成。 可以通过穿过通孔内的焊料的一部分来进行焊接，使得连接布线通过​​通孔在不同于焊盘层的层处连接到焊盘。

公开(公告)号：US06344695B1

公开(公告)日：2002-02-05

申请号：US09414503

申请日：1999-10-08

Applicant: Kei Murayama

Inventor： Kei Murayama

IPC: H01L2348

CPC classification number: H05K3/3436 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/07802 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/10992 ,  H05K2203/043 ,  Y02P70/613 ,  H01L2924/0105 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A semiconductor chip has an active surface with electrodes thereon and an insulating layer covering the active surface and having through holes therein through which corresponding electrodes are exposed. Rewiring circuits are formed on the insulating layer, each having a first terminal end extending through a corresponding through hole and electrically connected to a respective electrode and a second terminal end comprising a conductive pad. Respective inner bumps are formed on the second terminal ends of the rewiring circuits. An insulating film is formed on the rewiring circuits and exposed surfaces of the insulating layer and through holes are formed therein corresponding to the conductive pads and into which respective inner bumps are inserted. A respective outer bump is superimposed on each inner bump in the insulating film and projects beyond an exposed surface of the insulating film remote from the semiconductor chip. In an alternative, inner bumps are omitted and the outer bumps are directly superimposed on the conductive pads in the corresponding through holes. A method of making the semiconductor device provides for superimposing outer bumps either directly on the respective conductive pads in the corresponding through holes, where inner bumps are not employed, or superimposing same on the respective inner bumps after superimposing the inner bumps on the respective conductive pads.

Abstract translation: 半导体芯片具有其上具有电极的活性表面和覆盖有源表面的绝缘层，并且在其中具有通孔，相应的电极通过该孔暴露。 重叠电路形成在绝缘层上，每个具有延伸穿过相应通孔并且电连接到相应电极的第一端部和包括导电焊盘的第二端子。 在再布线电路的第二端部形成有各自的内部凸点。 在再布线电路上形成绝缘膜，绝缘层的露出表面形成有与导电焊盘相对应的通孔，并且插入有各自的内凸块。 相应的外部凸起叠加在绝缘膜的每个内部凸起上，并突出超过远离半导体芯片的绝缘膜的暴露表面。 另一方面，省略了内部凸块，并且外部凸块直接叠加在相应通孔中的导电焊盘上。 制造半导体器件的方法提供了将外部凸块直接叠加在不使用内部凸起的相应通孔中的相应导电焊盘上，或者将内部凸块叠加在各个导电焊盘上之后将其叠加在相应的内部凸起上 。

公开(公告)号：US20020004320A1

公开(公告)日：2002-01-10

申请号：US09205502

申请日：1998-12-04

Inventor： DAVID V. PEDERSEN ,  BENJAMIN N. ELDRIDGE ,  IGOR Y. KHANDROS

IPC: H05K001/00

CPC classification number: H01L25/16 ,  B23K1/0016 ,  B23K20/004 ,  B23K2101/40 ,  C25D5/08 ,  C25D5/22 ,  C25D21/02 ,  G01R1/0408 ,  G01R1/0433 ,  G01R1/06711 ,  G01R1/07342 ,  G01R1/07378 ,  G01R31/01 ,  G01R31/2863 ,  G01R31/2886 ,  G01R31/2889 ,  H01L21/4853 ,  H01L21/4889 ,  H01L21/563 ,  H01L22/20 ,  H01L23/04 ,  H01L23/13 ,  H01L23/32 ,  H01L23/49811 ,  H01L23/5385 ,  H01L24/06 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/45 ,  H01L24/49 ,  H01L24/72 ,  H01L24/81 ,  H01L25/0652 ,  H01L2223/54473 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2224/45144 ,  H01L2224/49109 ,  H01L2224/73203 ,  H01L2224/81136 ,  H01L2224/81801 ,  H01L2224/85201 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06527 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01033 ,  H01L2924/01051 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/19043 ,  H05K1/141 ,  H05K3/20 ,  H05K3/325 ,  H05K3/326 ,  H05K3/3421 ,  H05K3/368 ,  H05K3/4015 ,  H05K2201/09472 ,  H05K2201/1031 ,  H05K2201/10318 ,  H05K2201/10757 ,  H05K2201/10878 ,  H05K2201/10909 ,  H05K2201/10946 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/48

Abstract: Products and assemblies are provided for socketably receiving elongate interconnection elements, such as spring contact elements, extending from electronic components, such as semiconductor devices. Socket substrates are provided with capture pads for receiving ends of elongate interconnection elements extending from electronic components. Various capture pad configurations are disclosed. Connections to external devices are provided via conductive traces adjacent the surface of the socket substrate. The socket substrate may be supported by a support substrate. In a particularly preferred embodiment the capture pads are formed directly on a primary substrate such as a printed circuit board.

Abstract translation: 提供产品和组件用于可插拔地接收从电子部件（例如半导体器件）延伸的细长互连元件，例如弹簧接触元件。 插座基板设置有用于接收从电子部件延伸的细长互连元件的端部的捕获垫。 公开了各种捕获垫结构。 通过邻近插座基板表面的导电迹线提供与外部设备的连接。 插座基板可以由支撑基板支撑。 在特别优选的实施例中，捕获垫直接形成在诸如印刷电路板的主要基底上。

公开(公告)号：US20010050566A1

公开(公告)日：2001-12-13

申请号：US09789972

申请日：2001-02-20

Inventor： Hans-Jurgen Hacke

IPC: G01R031/02

CPC classification number: G01R1/0735 ,  G01R31/2886 ,  H05K1/0393 ,  H05K1/112 ,  H05K3/326 ,  H05K2201/0394 ,  H05K2201/09472

Abstract: A printed circuit board for use in testing electrical components having distributed two-dimensional connection contacts. The printed circuit board has an electrically insulating insulation layer provided with through-holes. In the region of a respective through-hole, an electrically conductive contact pad is provided on a side surface of the insulation layer. Proceeding from a respective contact pad, a respective conductor track extends to an edge region of the insulation layer.

Abstract translation: 一种用于测试具有分布式二维连接触点的电气部件的印刷电路板。 印刷电路板具有设置有通孔的电绝缘绝缘层。 在相应通孔的区域中，导电接触垫设置在绝缘层的侧表面上。 从相应的接触垫开始，相应的导体轨道延伸到绝缘层的边缘区域。

公开(公告)号：US06330166B1

公开(公告)日：2001-12-11

申请号：US09399166

申请日：1999-09-20

Applicant: Masayuki Aoyama ,  Yasuaki Matsunaga ,  Tomoyuki Hiramatsu ,  Naoyuki Akita ,  Koji Kondo

Inventor： Masayuki Aoyama ,  Yasuaki Matsunaga ,  Tomoyuki Hiramatsu ,  Naoyuki Akita ,  Koji Kondo

IPC: H05K702

CPC classification number: H05K3/3436 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/3452 ,  H05K2201/0394 ,  H05K2201/09427 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In an electronic-component mounting structure, an electronic component (2) has a surface. First electrodes (1) provided on the surface of the electronic component (2) are arranged in a first array. Second electrodes (3) provided on a base board (4) are arranged in a second array corresponding to the first array. The second electrodes (3) correspond to the first electrodes (1) respectively. Solder bumps (9) connect the first electrodes (1) and the second electrodes (3) respectively. The first electrodes (1) include first outermost electrodes (1b) located in an outer area of the first array. The second electrodes (3) include second outermost electrodes (3b, 3c) located in an outer area of the second array. The second outermost electrodes (3b, 3c) correspond to the first outermost electrodes (1b) respectively. An outer edge (X1, Z1) of each of the second outermost electrodes (3b, 3c) extends outward of an outer edge (Y1) of a corresponding first outermost electrode (1b) with respect to the first and second arrays. A distance between an outer edge (X1, Z1) of each of the second outermost electrodes (3b, 3c) and an outer edge (Y1) of a corresponding first outermost electrode (1b) is greater than a distance between an inner edge (X2, Z2) of the second outermost electrode (3b, 3c) and an inner edge (Y2) of the corresponding first outermost electrode (1b) with respect to the first and second arrays.

Abstract translation: 在电子部件安装结构中，电子部件（2）具有表面。 设置在电子部件（2）的表面上的第一电极（1）以第一阵列布置。 设置在基板（4）上的第二电极（3）以对应于第一阵列的第二阵列布置。 第二电极（3）分别对应于第一电极（1）。 焊接凸块（9）分别连接第一电极（1）和第二电极（3）。 第一电极（1）包括位于第一阵列的外部区域中的第一最外电极（1b）。 第二电极（3）包括位于第二阵列的外部区域中的第二最外电极（3b，3c）。 第二最外电极（3b，3c）分别对应于第一最外电极（1b）。 每个第二最外电极（3b，3c）的外边缘（X1，Z1）相对于第一和第二阵列延伸到对应的第一最外电极（1b）的外边缘（Y1）的外侧。 每个第二最外电极（3b，3c）的外边缘（X1，Z1）与对应的第一最外电极（1b）的外边缘（Y1）之间的距离大于内边缘（X2 ，Z2）和相应的第一最外电极（1b）的内边缘（Y2）相对于第一和第二阵列。

公开(公告)号：US20010030185A1

公开(公告)日：2001-10-18

申请号：US09826514

申请日：2001-04-04

Inventor： Roland Schnabel ,  Kurt Schaupert ,  Harry Engelmann

IPC: H05B003/68 ,  H05B003/08

CPC classification number: H01L24/85 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49866 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/48699 ,  H01L2224/73265 ,  H01L2224/8314 ,  H01L2224/83385 ,  H01L2224/85205 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/19043 ,  H01L2924/2076 ,  H01L2924/3025 ,  H01R4/023 ,  H01R43/0207 ,  H05K1/0284 ,  H05K1/0306 ,  H05K3/328 ,  H05K2201/09472 ,  H05K2203/049 ,  H01L2924/01014 ,  H01L2224/78 ,  H01L2924/01013 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/85399 ,  H01L2224/05599

Abstract: A connection of an electrical terminal 13 to a conductor track 5 applied to a glass or glass ceramic plate 1 is to be resistant to temperature change and traction and conductive. For this purpose an electrically conductive connecting element 11 is ultrasonically welded to the composite consisting of the conductor track 5 and plate 1. The connecting element 11 extends to the terminal 13 which is fastened to the plate 1.

Abstract translation: 电气端子13与施加到玻璃或玻璃陶瓷板1的导体轨道5的连接是耐温度变化和牵引力和导电性的。 为此，将导电连接元件11超声波焊接到由导体轨道5和板1组成的复合体上。连接元件11延伸到紧固到板1的端子13上。

公开(公告)号：US06299456B1

公开(公告)日：2001-10-09

申请号：US09058586

申请日：1998-04-10

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: H01R1200

CPC classification number: H01R12/57 ,  G01R1/0408 ,  G01R1/0466 ,  H01L2924/0002 ,  H01R43/205 ,  H05K1/119 ,  H05K3/325 ,  H05K3/326 ,  H05K3/4007 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/09045 ,  H05K2201/09472 ,  H05K2201/10689 ,  Y10T29/49117 ,  Y10T29/49123 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49174 ,  Y10T29/49179 ,  Y10T29/49222 ,  Y10T29/49453 ,  H01L2924/00

Abstract: An interposer having an array of contact structures for making temporary electrical contact with the leads of a chip package. The contact structures may make contact with the leads substantially as close as desired to the body of the chip package. Moreover, the contact structures can be adapted for making contact with leads having a very fine pitch. In a first embodiment, the contact structures include raised members formed over a body of the interposer. A conductive layer is formed over each of the raised members to provide a contact surface for engaging the leads of the chip package. In another embodiment, the raised members are replaced with depressions formed into the interposer. A conductive layer is formed on an inside surface of each depression to provide a contact surface for engaging the leads of the chip package. Moreover, any combination of raised members and depressions may be used.

Abstract translation: 具有用于与芯片封装的引线暂时电接触的接触结构阵列的插入器。 接触结构可以与引线基本上接近于芯片封装体的所需位置。 此外，接触结构可以适于与具有非常细的间距的引线接触。 在第一实施例中，接触结构包括形成在插入件的主体上的凸起部件。 在每个凸起构件上形成导电层，以提供用于接合芯片封装引线的接触表面。 在另一个实施例中，凸起构件被形成在插入件中的凹陷所代替。 在每个凹陷的内表面上形成导电层，以提供用于接合芯片封装的引线的接触表面。 此外，可以使用凸起构件和凹陷的任何组合。

公开(公告)号：US06291778B1

公开(公告)日：2001-09-18

申请号：US08765451

申请日：1997-01-22

Applicant: Motoo Asai ,  Masato Kawade ,  Shinji Hiratuka

Inventor： Motoo Asai ,  Masato Kawade ,  Shinji Hiratuka

IPC: H01R909

CPC classification number: H05K3/3457 ,  H05K1/112 ,  H05K3/184 ,  H05K3/3452 ,  H05K3/4644 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/0989 ,  H05K2201/10734 ,  H05K2203/0588

Abstract: This invention is to provide a printed circuit board suitable for the high densification of mounting parts using a solder bump and for the improvements of connection reliability and mounting reliability, and proposes a printed circuit board comprising a mounting pad provided with a solder bump by covering a mounting surface with a solder resist, characterized in that a position of forming the solder bump is arranged so as to match with a position of a viahole, or a size of opening portion formed in the solder resist is made larger than a size of a land of the viahole so as not to overlap the solder resist with the viahole.

Abstract translation: 本发明是提供一种印刷电路板，其适用于使用焊料凸块的安装部件的高致密度，并且用于提高连接可靠性和安装可靠性，并且提出了一种印刷电路板，其包括通过覆盖 安装表面具有阻焊剂，其特征在于，形成焊料凸点的位置被布置成与通孔的位置匹配，或者形成在阻焊层中的开口部分的尺寸大于焊盘的尺寸 以防止阻焊剂与通孔重叠。

公开(公告)号：US20010004942A1

公开(公告)日：2001-06-28

申请号：US09741455

申请日：2000-12-19

Inventor： Simone Rehm ,  Roland Frech ,  Erich Klink ,  Helmut Virag ,  Thomas-Michael Winkel ,  Wiren Becker ,  Bruce Chamberlin ,  Wai Ma

IPC: H05K001/11

CPC classification number: H05K1/113 ,  H05K1/0231 ,  H05K1/115 ,  H05K3/429 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10522 ,  H05K2201/10636 ,  Y02P70/611 ,  Y10T29/4913

Abstract: Described is a method for minimizing switching noise in the high- and mid-frequency range on printed circuit cards or boards by means of a plurality of surface mounted decoupling capacitors. A novel configuration and implementation of capacitor pads including the connecting vias is also presented. As a result the parasitic inductance of the pads and vias can be significantly reduced. Thus the effectiveness of the decoupling capacitors in the mid and high frequency range can be increased, the voltage drop can be reduced and the system performance can be increased. Several design rules for the new pad via configuration lead to the significant reduction of the parasitic inductance. The proposal is especially important for high integrated system designs on boards and cards combined with increased cycle times.

Abstract translation: 描述了一种通过多个表面安装的去耦电容器来最小化印刷电路板或板上的高频和中频范围内的开关噪声的方法。 还介绍了包括连接通孔的电容器焊盘的新颖配置和实现。 结果，焊盘和通孔的寄生电感可以显着降低。 因此，可以提高中高频区域中的去耦电容器的有效性，可以降低电压降并且可以提高系统性能。 新焊盘通过配置的几个设计规则导致寄生电感的显着减少。 该建议对于板卡和卡上的高集成系统设计以及增加的周期时间尤其重要。

公开(公告)号：US06251766B1

公开(公告)日：2001-06-26

申请号：US09388755

申请日：1999-09-02

Applicant: Kishor V. Desai ,  Amit K. Sarkhel

Inventor： Kishor V. Desai ,  Amit K. Sarkhel

IPC: H01L2144

CPC classification number: H01L24/10 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/05655 ,  H01L2224/13 ,  H01L2224/13006 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/10734 ,  H05K2201/10992 ,  H05K2203/041 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An adhesion pad for adhering a semiconductor chip or a ball grid array module to a supporting substrate includes a stepped or tapered structure. The structure is composed of at least one solder wettable metal or alloy layer having solder deposited thereon. The stepped or tapered structure prevents a fatigue crack from propagating in the X-Y plane above the adhesion pad.

Abstract translation: 用于将半导体芯片或球栅阵列模块粘附到支撑基板上的粘合垫包括阶梯形或锥形结构。 该结构由至少一个焊料可湿性金属或其上沉积有焊料的合金层组成。 台阶或锥形结构防止疲劳裂纹在粘合垫上方的X-Y平面中传播。