公开(公告)号：US06282782B1

公开(公告)日：2001-09-04

申请号：US09389308

申请日：1999-09-02

Applicant: Nicholas Biunno ,  Scott Bryan ,  Mason Hu

Inventor： Nicholas Biunno ,  Scott Bryan ,  Mason Hu

IPC: H01K310

CPC classification number: H05K3/0094 ,  H05K1/0206 ,  H05K3/1216 ,  H05K3/3452 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/083 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49222

Abstract: A method of forming a subassembly for use in a printed circuit board is described. This method includes providing a subassembly including a circuit board layer laminated to two sheets of conductive material with two intermediate sheets of prepreg material, forming a via in the assembly, plating the via, filling the via with a plug material in a volatile solvent, evaporating the volatile solvent, and curing the plug material. Also described is a method of forming a partially filled via in a circuit board layer and a method of forming a thermally conductive plug in a circuit board layer for the transfer of thermal energy from one surface of the circuit board to the other.

Abstract translation: 描述了形成用于印刷电路板的子组件的方法。 该方法包括提供一个子组件，该组件包括层压到两片导电材料的电路板层，该片材具有两片中间片预浸料材料，在组件中形成通孔，电镀通孔，用挥发性溶剂中的塞子材料填充通孔，蒸发 挥发性溶剂，并固化塞子材料。 还描述了在电路板层中形成部分填充的通孔的方法以及在电路板层中形成用于将热能从电路板的一个表面传递到另一个的导热塞的方法。

公开(公告)号：US06264862B1

公开(公告)日：2001-07-24

申请号：US09246220

申请日：1999-02-08

Applicant: Been-Yu Liaw

Inventor： Been-Yu Liaw

IPC: B29C3910

CPC classification number: B29C39/10 ,  B29C67/08 ,  B29C2791/005 ,  H01L21/486 ,  H05K3/0094 ,  H05K3/1233 ,  H05K3/4053 ,  H05K2201/0959 ,  H05K2203/0126 ,  H05K2203/082 ,  H05K2203/1105 ,  Y10T29/49124

Abstract: An apparatus for manufacturing a plug and the manufacturing method. The method includes the following steps. A baseplate located in the bottom of a closed printing chamber is provided. A printed circuit board and a stencil are mounted on the baseplate in sequence. The stencil is aligned to the printed circuit board. An amount of preheated paste is placed on the stencil. A pressure of the closed printing chamber is adjusted to a first pressure. A printing step is performed to form plugs in the printed circuit board. The pressure of the closed printing chamber is adjusted to a second pressure to remove voids trapped in the plugs. The pressure of the closed printing chamber is adjusted to a third pressure. A scraping step is performed to remove the redundant paste.

Abstract translation: 一种用于制造插头的装置及其制造方法。 该方法包括以下步骤。 提供位于封闭印刷室底部的底板。 依次将印刷电路板和模板安装在底板上。 模板与印刷电路板对齐。 将一定量的预热膏放在模板上。 将封闭的印刷室的压力调节至第一压力。 执行打印步骤以在印刷电路板中形成插头。 将封闭的印刷室的压力调节至第二压力以除去捕获在插塞中的空隙。 将封闭的印刷室的压力调整到第三压力。 执行刮擦步骤以去除冗余浆料。

公开(公告)号：US20010007289A1

公开(公告)日：2001-07-12

申请号：US09778702

申请日：2001-02-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Anilkumar C. Bhatt ,  Voya R. Markovich ,  Irving Memis ,  William E. Wilson

IPC: H01R012/04 ,  H05K001/00

CPC classification number: H05K3/0094 ,  B32B7/04 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/0023 ,  H05K3/045 ,  H05K3/184 ,  H05K3/4053 ,  H05K3/4069 ,  H05K3/426 ,  H05K3/427 ,  H05K3/4605 ,  H05K2201/0154 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/10734 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0353 ,  H05K2203/1152 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A method provides for additive plating on a subcomposite having filled plated through holes. Fine-line circuitry is achieved via electroless deposition onto a dielectric substrate after the through hole is plated and filled. Fine-line circuitry may be routed over landless, plated through holes thereby increasing the aspect ratio and the available surface area for additional components and wiring.

公开(公告)号：US20010002162A1

公开(公告)日：2001-05-31

申请号：US09769243

申请日：2001-01-26

Applicant: Hitachi, Ltd.

Inventor： Satoshi Imasu ,  Ikuo Yoshida ,  Tetsuya Hayashida ,  Akira Yamagiwa ,  Shinobu Takeura

IPC: H05K007/06

CPC classification number: H05K1/111 ,  H01L21/563 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49811 ,  H01L23/5383 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/105 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49109 ,  H01L2224/73103 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81191 ,  H01L2224/83101 ,  H01L2224/83191 ,  H01L2224/83192 ,  H01L2225/1023 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01079 ,  H01L2924/0132 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/1579 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/351 ,  H05K1/0271 ,  H05K1/114 ,  H05K3/3436 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/091 ,  H05K2201/09472 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/10674 ,  H05K2203/1581 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/00012 ,  H01L2924/01082 ,  H01L2924/00

Abstract: An electronic device comprising a semiconductor chip which is fixed to the mounting face of a wiring board through an adhesive and in which external terminals are electrically connected with electrode pads of the wiring board through bump electrodes. Recesses are formed in the electrode pads, and in the recesses the electrode pads and the bump electrodes are connected. The electrode pads are formed over the surface of a soft layer, and the recesses are formed by elastic deformation of the electrode pads and the soft layer.

Abstract translation: 一种电子设备，包括通过粘合剂固定到布线板的安装面的半导体芯片，其中外部端子通过凸块电极与布线板的电极焊盘电连接。 在电极焊盘上形成凹部，在凹部中连接有电极焊盘和凸块电极。 电极焊盘形成在软层的表面上，并且通过电极焊盘和软层的弹性变形形成凹部。

公开(公告)号：US06199273B1

公开(公告)日：2001-03-13

申请号：US08769449

申请日：1996-12-19

Applicant: Toshihiko Kubo ,  Takuji Ito ,  Hiroshi Takamichi ,  Akihiro Hidaka

Inventor： Toshihiko Kubo ,  Takuji Ito ,  Hiroshi Takamichi ,  Akihiro Hidaka

IPC: H01R900

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L2224/11334 ,  H01L2924/15173 ,  H05K1/113 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3452 ,  H05K3/3478 ,  H05K2201/0379 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/10666 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/043 ,  H05K2203/074 ,  H05K2203/1394 ,  Y02P70/613 ,  Y10T29/49147 ,  Y10T29/49149

Abstract: A ball-grid array connector structure for an electronic package in which the ball pitch can be reduced to increase the packaging density has a plastic substrate having at least one hollow through-hole and an electrode covering the wall of the through-hole and forming an electrode pad surrounding the through-hole on each surface of the substrate. A metallic ball is joined, either directly or through a solder or a combination of a metallic bump and a solder, to the electrode pad on at least one surface of the substrate at the position of the through-hole. The connector structure can be formed either by sealing an open end of the through-hole on the side to which the ball is not joined, or increasing the pressure within the through-hole by a pressure-control mechanism, before the through-hole is blocked by reflowing the ball itself or the metallic bump or solder used to connect the ball.

Abstract translation: 用于电子封装的球栅阵列连接器结构，其中球节距可以减小以增加封装密度，具有具有至少一个中空通孔的塑料基板和覆盖通孔壁的电极，并形成 围绕基板每个表面上的通孔的电极焊盘。 金属球直接或通过焊料或金属凸块和焊料的组合连接到通孔位置处的基板的至少一个表面上的电极焊盘。 连接器结构可以通过在通孔之前通过密封球体未接合的一侧上的通孔的开口端或通过压力控制机构来增加通孔内的压力来形成 通过回流球本身或用于连接球的金属凸块或焊料来阻止。

公开(公告)号：US06190941B1

公开(公告)日：2001-02-20

申请号：US09396661

申请日：1999-09-15

Applicant: Helmut Heinz ,  Bernhard Schuch

Inventor： Helmut Heinz ,  Bernhard Schuch

IPC: H01L2144

CPC classification number: H05K7/205 ,  H01L23/3677 ,  H01L2924/0002 ,  H05K1/0206 ,  H05K1/113 ,  H05K3/0058 ,  H05K3/0094 ,  H05K3/1216 ,  H05K3/341 ,  H05K3/3452 ,  H05K7/20854 ,  H05K2201/066 ,  H05K2201/09572 ,  H05K2201/0959 ,  H05K2201/10166 ,  H05K2201/10969 ,  H05K2203/1476 ,  Y02P70/613 ,  H01L2924/00

Abstract: An electronic component is mounted on a substrate such as a circuit board by means of a soldering process such as reflow soldering. The circuit board has a thermal via hole therethrough to provide a heat dissipation path from the top surface to the bottom surface of the circuit board, for dissipating heat from the electronic component. To prevent molten solder from penetrating through the via hole during the soldering process, the via hole is sealed prior to the soldering process. The via hole is sealed from the bottom surface of the substrate by carrying out a screen printing process including at least two printing passes to print a sealing material into the open hole of the thermal via.

Abstract translation: 电子部件通过诸如回流焊接的焊接工艺安装在诸如电路板的基板上。 电路板具有穿过其中的热通孔以提供从电路板的顶表面到底表面的散热路径，用于从电子部件散热。 为了防止熔融焊料在焊接过程中穿透通孔，通孔在焊接过程之前被密封。 通过进行包括至少两个印刷通道的丝网印刷工艺将通孔从基材的底表面密封，以将密封材料印刷到热通孔的开孔中。

公开(公告)号：US06177490B1

公开(公告)日：2001-01-23

申请号：US09222347

申请日：1998-12-29

Applicant: Kyoichi Yoda ,  Akio Sekimoto ,  Norio Kimura ,  Masashi Sugita ,  Masao Arima

Inventor： Kyoichi Yoda ,  Akio Sekimoto ,  Norio Kimura ,  Masashi Sugita ,  Masao Arima

IPC: C08K500

CPC classification number: H05K3/0094 ,  C08L63/00 ,  H05K2201/0209 ,  H05K2201/0959 ,  C08L61/04

Abstract: A liquid thermosetting filling composition comprising (A) an epoxy resin assuming a liquid state at room temperature, (B) a phenolic resin assuming a liquid state at room temperature, (C) a curing catalyst, and (D) an inorganic filler is useful as an ink for permanently filling such holes as via holes and through holes in printed circuit boards of a multilayer board or a double-sided board, a sealing compound for IC packages, and the like. This composition is a two-stage thermally curing type. In a method for permanently filling holes in a printed circuit board, the composition is applied to the board so as to fill the holes in the printed circuit board and precured by application of heat. The parts of the precured composition protruding from a surface defining the holes is removed by polishing and then the precured composition is further heated to cause final curing thereof.

Abstract translation: 一种液体热固性填充组合物，其包含（A）在室温下呈液态的环氧树脂，（B）在室温下呈液态的酚醛树脂，（C）固化催化剂和（D）无机填料是有用的 作为用于永久地填充多层板或双面板的印刷电路板中的通孔和通孔的孔，用于IC封装的密封化合物等。 该组合物是两阶段热固化型。 在用于永久地填充印刷电路板中的孔的方法中，将组合物施加到板上，以便填充印刷电路板中的孔并通过施加热来预固化。 从形成孔的表面突出的预固化组合物的部分通过抛光除去，然后将预固化组合物进一步加热以使其最终固化。

公开(公告)号：US6165892A

公开(公告)日：2000-12-26

申请号：US127580

申请日：1998-07-31

Applicant: David J. Chazan ,  Ted T. Chen ,  Todd S. Kaplan ,  James L. Lykins ,  Michael P. Skinner ,  Jan I. Strandberg

Inventor： David J. Chazan ,  Ted T. Chen ,  Todd S. Kaplan ,  James L. Lykins ,  Michael P. Skinner ,  Jan I. Strandberg

IPC: H01L21/48 ,  H01L23/538 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H01L21/4763

CPC classification number: H05K3/4673 ,  H01L21/481 ,  H01L21/4857 ,  H01L23/5383 ,  H01L23/5385 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K1/0271 ,  H05K3/0023 ,  H05K3/0032 ,  H05K3/4602 ,  H05K3/4644 ,  H05K2201/0195 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09881 ,  H05K2203/0585 ,  H05K2203/0759 ,  H05K2203/1476 ,  H01L2924/00

Abstract: A method for forming a planarized thin film dielectric film on a surface of a common circuit base upon which one or more integrated circuits are to be attached. The common circuit base includes raised features formed over its surface such that the raised features define a trench area between them. The method includes the steps of forming a first layer of the dielectric film over the common circuit base and over the raised features and the trench, then patterning the newly formed layer to remove portions of the layer formed over the raised features and expose the raised features. After the layer is patterned, formation of the dielectric film is completed by forming a second layer of the dielectric film over the patterned first layer. Additional film deposition and film patterning steps are performed to complete the layout of a thin film interconnect structure over said common circuit base, and an integrated circuit die is attached to the common circuit base and electrically connecting to the thin film interconnect structure. In a preferred embodiment, the first and second layers of the dielectric film are both formed from a photo-definable material and the patterning step includes exposing the first layer to light through a patterned mask corresponding to the raised features and developing the exposed layer with a developing solution to etch away portions of the first layer formed over the raised features.

Abstract translation: 一种用于在公共电路基底的表面上形成平坦化的薄膜电介质膜的方法，一个或多个集成电路将安装在该公共电路基底上。 公共电路基座包括在其表面上形成的凸起特征，使得凸起特征在它们之间限定沟槽区域。 该方法包括以下步骤：在公共电路基底上方和凸起的特征​​和沟槽上形成电介质膜的第一层，然后对新形成的层进行图案化以去除在凸起特征上形成的层的部分，并暴露凸起特征 。 在层被图案化之后，通过在图案化的第一层上形成电介质膜的第二层来完成电介质膜的形成。 执行附加的膜沉积和膜图案化步骤以在所述公共电路基底上完成薄膜互连结构的布局，并且集成电路管芯附接到公共电路基座并电连接到薄膜互连结构。 在优选实施例中，电介质膜的第一和第二层都由光可定义材料形成，并且图案化步骤包括通过对应于凸起特征的图案化掩模将第一层暴露于光，并将曝光层用 显影溶液以蚀刻形成在凸起特征上的第一层的部分。

公开(公告)号：US6138350A

公开(公告)日：2000-10-31

申请号：US30587

申请日：1998-02-25

Applicant: Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

Inventor： Anilkumar Chinuprasad Bhatt ,  Donald Herman Glatzel ,  Allen F. Moring ,  Voya Rista Markovich ,  Kostas Papathomas ,  David John Russell

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/02 ,  H05K3/24 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  H01K3/10

CPC classification number: H05K3/4652 ,  H05K1/113 ,  H05K3/4069 ,  H05K3/4602 ,  H01L2224/48091 ,  H01L2224/73204 ,  H01L2924/12044 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/092 ,  H05K2201/0959 ,  H05K2203/0191 ,  H05K2203/025 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/0554 ,  H05K3/0023 ,  H05K3/0094 ,  H05K3/025 ,  H05K3/246 ,  H05K3/429 ,  Y10S428/901 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49139 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917 ,  Y10T428/24926 ,  Y10T428/24942 ,  Y10T428/249996

Abstract: A process for manufacturing circuit boards comprising providing a circuitized substrate having a dielectric surface, providing a peel apart structure including a metal layer and a peelable film, laminating the peel apart structure to the circuitized substrate with the metal layer positioned adjacent said dielectric surface, forming holes in the circuitized substrate through the peel apart structure, applying a filler material including an organic base to the peel apart structure, applying a sacrificial film onto the filler material, and applying sufficient heat and pressure to the sacrificial film to force the filler material into the holes to substantially fill the holes is provided.

Abstract translation: 一种用于制造电路板的方法，包括提供具有电介质表面的电路化基板，提供包括金属层和可剥离膜的剥离结构，将剥离结构层压到电路化基板上，金属层位于邻近所述电介质表面，形成 通过剥离结构在电路化基板中的孔，将包含有机基底的填充材料施加到剥离结构上，将牺牲膜施加到填充材料上，以及向牺牲膜施加足够的热和压力以迫使填充材料进入 提供基本上填充孔的孔。

公开(公告)号：US6125531A

公开(公告)日：2000-10-03

申请号：US259977

申请日：1999-03-01

Applicant: Donald S. Farquhar ,  Voya R. Markovich ,  Kostas I. Papathomas ,  Leonard L. Schmidt

Inventor： Donald S. Farquhar ,  Voya R. Markovich ,  Kostas I. Papathomas ,  Leonard L. Schmidt

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/24 ,  H05K3/40 ,  H01K3/10

CPC classification number: H05K3/0094 ,  H05K3/4069 ,  H05K1/0366 ,  H05K1/113 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2203/0278 ,  H05K2203/0338 ,  H05K2203/1453 ,  H05K3/246 ,  Y10T29/49144 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of making a circuitized substrate such as a printed circuit board having at least one hole therein which comprises the steps of providing a layer of dielectric, forming at least one (and preferably several) holes therein, providing a fill member including a quantity of fill material and reinforcement means located within the fill material, positioning the fill member on the dielectric over the holes and thereafter applying a predetermined force sufficient to cause only the fill material to be forcibly driven into the accommodating hole(s), not the reinforcement means. Subsequent steps can include forming a layer of circuitry on the substrate's external surface and over the filled holes such that an electrical component such as a ball grid array (BGA), semiconductor chip, etc. may be directly positioned on and/or over the hole(s). A fill member usable with the method is also provided.