公开(公告)号：US09450279B2

公开(公告)日：2016-09-20

申请号：US14473102

申请日：2014-08-29

Applicant: SOCIONEXT INC.

Inventor： Ian Juso Dedic

IPC: H01P1/26 ,  H03H7/38 ,  H01L23/64 ,  H01P11/00 ,  H05K1/02 ,  H01P1/22

CPC classification number: H01P1/268 ,  H01L23/64 ,  H01L2924/0002 ,  H01P1/22 ,  H01P1/227 ,  H01P11/003 ,  H03H7/383 ,  H05K1/0219 ,  H05K1/0246 ,  H05K1/025 ,  H05K2201/09727 ,  H05K2201/09736 ,  H01L2924/00

Abstract: A lossy electrical-signal transmission line having first and second ends, the transmission line being configured such that: its characteristic impedance at the first end has a first value; its characteristic impedance at the second end has a second value, lower than the first value; and its series resistance measured from its first end to its second end is within a given range of the difference between said first and second values.

Abstract translation: 一种具有第一和第二端的有损耗的电信号传输线，所述传输线被配置为：其第一端的特征阻抗具有第一值; 其第二端的特征阻抗具有低于第一值的第二值; 并且其从其第一端到其第二端测量的串联电阻在所述第一和第二值之间的差的给定范围内。

公开(公告)号：US20160219690A1

公开(公告)日：2016-07-28

申请号：US15001383

申请日：2016-01-20

Applicant: KYOCERA Circuit Solutions, Inc.

Inventor： Yasuki ITOH

IPC: H05K1/02

CPC classification number: H05K3/4644 ,  H01L2224/16225 ,  H01L2924/15174 ,  H05K1/0271 ,  H05K3/3436 ,  H05K2201/09736

Abstract: A wiring board of the present invention includes a core substrate, insulating layers laminated on upper and lower surfaces of the core substrate, and a conductor layer deposited on the upper and lower surfaces of the core substrate and a surface of each of the insulating layers, in such a manner as to make a difference in area occupation ratio between the upper and lower surfaces of the core substrate. A thickness of a conductor that has a large area occupation ratio is smaller than a thickness of a conductor that has a small area occupation ratio between the conductor layers deposited on the upper and lower surfaces of the core substrate, and between the conductor layers deposited on the surface of each of the insulating layers laminated at an identical level on upper and lower surface sides with the core substrate as a center.

Abstract translation: 本发明的布线基板包括芯基板，层叠在芯基板的上表面和下表面上的绝缘层，以及沉积在芯基板的上表面和下表面上的导体层和每个绝缘层的表面， 以使得芯基板的上表面和下表面之间的面积占有率不同。 具有大面积占有率的导体的厚度小于在芯基板的上表面和下表面之间以及沉积在芯基板上的导体层之间的导体层之间具有小面积占有率的导体的厚度 每个绝缘层的表面以芯基板为中心在上表面和下表面侧以相同的水平层压。

公开(公告)号：US20160152020A1

公开(公告)日：2016-06-02

申请号：US14867079

申请日：2015-09-28

Applicant: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.

Inventor： Masayuki MANTANI

IPC: B41F15/08

CPC classification number: B41F15/44 ,  B41F15/0881 ,  B41F15/18 ,  B41F15/36 ,  B41F15/46 ,  B41P2215/114 ,  H05K3/1225 ,  H05K3/3484 ,  H05K2201/094 ,  H05K2201/09736

Abstract: A screen printing apparatus includes a mask and a printing head. The mask has a first opening provided in a first region, and a second opening provided in a second region which is thicker than the first region. The printing head fills the first opening with a paste in a state where a substrate is in contact with the first region, and fills the second opening with the paste in a state where the substrate is in contact with the second region.

Abstract translation: 丝网印刷装置包括掩模和打印头。 掩模具有设置在第一区域中的第一开口和设置在比第一区域更厚的第二区域中的第二开口。 打印头在基板与第一区域接触的状态下用糊状物填充第一开口，并且在基板与第二区域接触的状态下用糊状物填充第二开口。

公开(公告)号：US09332650B2

公开(公告)日：2016-05-03

申请号：US13494417

申请日：2012-06-12

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: H05K3/02 ,  H05K3/18 ,  H05K1/16 ,  H05K3/10 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/46

CPC classification number: H05K3/184 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/15173 ,  H01L2924/15311 ,  H05K1/0206 ,  H05K1/023 ,  H05K1/0284 ,  H05K1/11 ,  H05K1/162 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/107 ,  H05K3/381 ,  H05K3/4069 ,  H05K3/4647 ,  H05K3/4661 ,  H05K2201/09381 ,  H05K2201/096 ,  H05K2201/09736 ,  H05K2203/0108 ,  H05K2203/0565 ,  Y10T29/49114 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: The present invention relates to a method of producing a multilayer circuit board including: a film-forming step of forming a swellable resin film on the surface of an insulative substrate, a circuit groove-forming step of forming circuit grooves having a depth equal to or greater than the thickness of the swellable resin film on the external surface of the film, a catalyst-depositing step of depositing a plating catalyst or the precursor thereof on the surface of the circuit grooves and the surface of the swellable resin film, a film-separating step of swelling the swellable resin film with a particular liquid and then separating the swollen resin film from the insulative substrate surface, and a plating processing step of forming an electrolessly plated film only in the region where the plating catalyst or the plating catalyst formed from the plating catalyst precursor remains unseparated after separation of the film.

Abstract translation: 本发明涉及一种制造多层电路板的方法，包括：在绝缘基板的表面上形成可溶胀树脂膜的成膜步骤，形成电路槽的电路槽形成步骤，该电路槽的深度等于或等于 大于膜的外表面上的可溶胀树脂膜的厚度，在电路槽的表面和可溶胀树脂膜的表面上沉积电镀催化剂或其前体的催化剂沉积步骤， 分离步骤，用特定的液体使溶胀性树脂膜溶胀，然后从膨胀的基材表面分离溶胀的树脂膜;以及电镀处理步骤，仅在由镀催化剂或电镀催化剂形成的镀层催化剂的区域形成无电镀膜 电镀催化剂前体在分离膜后保持未分离。

公开(公告)号：US09332642B2

公开(公告)日：2016-05-03

申请号：US14481188

申请日：2014-09-09

Applicant: Panasonic Corporation

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara ,  Hiromitsu Takashita ,  Tsuyoshi Takeda

IPC: H05K1/09 ,  H05K1/11 ,  H05K3/10 ,  H05K3/18 ,  H05K3/40 ,  H05K1/02 ,  H05K1/03 ,  H05K3/00

CPC classification number: H05K1/119 ,  H01L2224/81385 ,  H05K1/0284 ,  H05K1/0373 ,  H05K1/111 ,  H05K3/0014 ,  H05K3/0032 ,  H05K3/0044 ,  H05K3/0076 ,  H05K3/0079 ,  H05K3/0085 ,  H05K3/107 ,  H05K3/185 ,  H05K3/4007 ,  H05K2201/0209 ,  H05K2201/0224 ,  H05K2201/0233 ,  H05K2201/0239 ,  H05K2201/0376 ,  H05K2201/0769 ,  H05K2201/09227 ,  H05K2201/09472 ,  H05K2201/09736 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09972 ,  H05K2203/0108 ,  H05K2203/013 ,  H05K2203/0143 ,  H05K2203/0228 ,  H05K2203/0264 ,  H05K2203/0285 ,  H05K2203/0565 ,  H05K2203/0706 ,  H05K2203/0776 ,  H05K2203/1163 ,  Y02P70/611

Abstract: One aspect of the present invention relates to a circuit board including an insulating base substrate; and a circuit layer that is formed of a conductor and that is provided on the surface of the insulating base substrate, wherein the insulating base substrate has a smooth surface having a surface roughness Ra of 0.5 μm or less, and the conductor is at least partially embedded in a wiring groove formed in the surface of the insulating base substrate.

Abstract translation: 本发明的一个方面涉及一种包括绝缘基底的电路板; 以及电路层，其由导体形成，并且设置在所述绝缘基底基板的表面上，其中所述绝缘基底具有表面粗糙度Ra为0.5μm以下的平滑表面，并且所述导体至少部分地 嵌入形成在绝缘性基板的表面的布线槽。

公开(公告)号：US20150340149A1

公开(公告)日：2015-11-26

申请号：US14541552

申请日：2014-11-14

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Dong Hwan LEE ,  Chan YOON ,  Hye Yeon CHA ,  Jin Woo HAN

IPC: H01F27/28 ,  H05K1/11 ,  H01F27/29 ,  H05K1/18 ,  H01F27/24

CPC classification number: H01F27/2804 ,  H01F17/0013 ,  H01F27/24 ,  H01F27/292 ,  H01F2017/0066 ,  H01F2017/0073 ,  H01F2027/2809 ,  H05K1/111 ,  H05K1/165 ,  H05K1/181 ,  H05K3/241 ,  H05K2201/0347 ,  H05K2201/086 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/098 ,  H05K2201/1003 ,  H05K2201/10636 ,  H05K2203/1476 ,  Y02P70/611

Abstract: A chip electronic component may include a magnetic material body including an insulating substrate and coil conductor patterns formed on at least one surface of the insulating substrate, and external electrodes disposed on both end portions of the magnetic material body so as to be connected to end portions of the coil conductor patterns, respectively. In a cross section of the magnetic material body in a length direction, a thickness of an innermost loop/section of the coil conductor patterns may be smaller than a thickness of the remaining loops/sections of the coil conductor pattern.

Abstract translation: 芯片电子部件可以包括：磁性材料体，包括绝缘基板和形成在绝缘基板的至少一个表面上的线圈导体图案;以及外部电极，设置在磁性材料体的两端部，以便连接到端部 的线圈导体图案。 在磁性材料体的长度方向的截面中，线圈导体图案的最内圈/截面的厚度可以小于线圈导体图案的剩余环/厚度。

公开(公告)号：US09136702B2

公开(公告)日：2015-09-15

申请号：US13843860

申请日：2013-03-15

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang Moon Lee ,  Sung Kwon Wi ,  Ju Hwan Yang ,  Won Chul Sim ,  Young Do Kweon

IPC: H02H7/24 ,  H02H9/04 ,  H01T4/08 ,  H01T4/10 ,  H01C1/14 ,  H05K1/02 ,  H01C7/12

CPC classification number: H02H9/044 ,  H01C1/14 ,  H01C7/12 ,  H01T4/08 ,  H01T4/10 ,  H05K1/026 ,  H05K2201/09736 ,  H05K2201/09827

Abstract: Disclosed herein are an electrostatic discharge protection device including: a substrate; a pair of electrodes formed on the substrate so as to be spaced apart from each other; and an insulating layer formed on the electrodes, wherein each of the electrodes has a shape in which it protrudes from a cross section thereof toward a surface thereof, and a manufacturing method thereof, and a composite electronic component including the same.

Abstract translation: 这里公开了一种静电放电保护装置，包括：基板; 一对电极，形成在所述基板上以彼此间隔开; 以及形成在电极上的绝缘层，其中每个电极具有从其横截面向其表面突出的形状及其制造方法，以及包括该绝缘层的复合电子部件。

公开(公告)号：US20150156873A1

公开(公告)日：2015-06-04

申请号：US14554334

申请日：2014-11-26

Applicant: Panasonic Corporation

Inventor： Shingo YOSHIOKA ,  Hiroaki FUJIWARA ,  Hiromitsu TAKASHITA ,  Tsuyoshi TAKEDA

IPC: H05K1/11

CPC classification number: H05K1/111 ,  H01L21/4846 ,  H01L23/49811 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/16237 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/82385 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K3/107 ,  H05K3/184 ,  H05K3/38 ,  H05K2201/0373 ,  H05K2201/0391 ,  H05K2201/09736 ,  H05K2201/2072 ,  H05K2203/0307 ,  H05K2203/0565 ,  Y02P70/611 ,  Y10T29/49155 ,  H01L2924/00

Abstract: A circuit board includes an electric circuit having a wiring section and a pad section in the surface of an insulating base substrate. The electric circuit is configured such that a conductor is embedded in a circuit recess formed in the surface of the insulating base substrate, and the surface roughness of the conductor is different in the wiring section and the pad section of the electric circuit. In this case, it is preferable that the surface roughness of the conductor in the pad section is greater than the surface roughness of the conductor in the wiring section.

Abstract translation: 电路板包括在绝缘基底的表面上具有布线部分和焊盘部分的电路。 电路被配置为使得导体嵌入形成在基底绝缘体的表面中的电路凹槽中，并且导体的表面粗糙度在电路的布线部分和焊盘部分中是不同的。 在这种情况下，优选的是，焊盘部中的导体的表面粗糙度大于布线部中的导体的表面粗糙度。

公开(公告)号：US09021690B2

公开(公告)日：2015-05-05

申请号：US13137756

申请日：2011-09-09

Applicant: Myung Sam Kang

Inventor： Myung Sam Kang

IPC: H01R9/00 ,  H05K1/11 ,  H05K3/20 ,  H05K3/34 ,  H05K3/28

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/09736 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00

Abstract: A method of manufacturing a printed circuit board having a buried solder bump, including: preparing a carrier on which a circuit layer, a solder bump, and a circuit pattern formed on the solder bump are formed; pressing the carrier into an insulating layer so that the circuit layer, the solder bump and the circuit pattern are buried in the insulating layer; and removing the carrier.

Abstract translation: 一种制造具有埋置焊料凸块的印刷电路板的方法，包括：制备其上形成有电路层，焊料凸块和形成在焊料凸块上的电路图案的载体; 将载体压入绝缘层，使得电路层，焊料凸块和电路图案埋在绝缘层中; 并移除载体。

公开(公告)号：US08971006B2

公开(公告)日：2015-03-03

申请号：US13362562

申请日：2012-01-31

Applicant: Yuuki Mikami ,  Toru Itabashi ,  Takahiko Furuta ,  Ryoichi Shiraishi ,  Yusuke Takahashi ,  Hiroaki Nakamura ,  Shigeki Nishiyama

Inventor： Yuuki Mikami ,  Toru Itabashi ,  Takahiko Furuta ,  Ryoichi Shiraishi ,  Yusuke Takahashi ,  Hiroaki Nakamura ,  Shigeki Nishiyama

IPC: H01H85/08 ,  H01H85/10 ,  H02H5/04 ,  H05K1/02 ,  H01H85/046

CPC classification number: H02H5/047 ,  H01H85/046 ,  H01H85/08 ,  H01H85/10 ,  H05K1/0265 ,  H05K1/0293 ,  H05K2201/09263 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09909 ,  H05K2201/10181

Abstract: An electronic control device includes a substrate, a plurality of component-mounted wires, a plurality of electronic components, a common wire, an interrupt wire and a protective layer. The component-mounted wires and the common wire are disposed on the substrate. The electronic components are mounted on the respective component-mounted wires and are coupled with the common wire. The interrupt wire is coupled between one component-mounted wire and the common wire, and is configured to melt in accordance with heat generated by an overcurrent to interrupt a coupling between the component-mounted wire and the common wire. The protective layer covers a surface of the substrate including the interrupt wire and defines an opening portion so that at least a portion of the interrupt wire is exposed.