公开(公告)号：US06651315B1

公开(公告)日：2003-11-25

申请号：US09181028

申请日：1998-10-27

Applicant: Gregory A. Graves ,  Michael Mengruo Zhang ,  Daniel Chandler ,  Chi-Ming Chan ,  Shou-Mean Fang ,  Dennis Siden ,  Mark Thompson

Inventor： Gregory A. Graves ,  Michael Mengruo Zhang ,  Daniel Chandler ,  Chi-Ming Chan ,  Shou-Mean Fang ,  Dennis Siden ,  Mark Thompson

IPC: H01C1728

CPC classification number: H05K1/184 ,  H01C1/14 ,  H01C1/1406 ,  H01C7/027 ,  H01C17/06586 ,  H05K1/182 ,  H05K3/0097 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/09181 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10469 ,  H05K2201/10643 ,  H05K2201/10666 ,  Y02P70/613 ,  Y10T29/49085 ,  Y10T29/49101 ,  Y10T29/49103

Abstract: An electrical device which comprises first and second laminar electrodes and a laminar PTC resistive element sandwiched between them, the device comprising: (a) a main portion which comprises a main part of the first electrode, a main part of the second electrode, and a main part of the resistive element; and (b) a first connection leg which extends away from the main portion and which comprises a first leg part of the first electrode which is integral with the main part of the first electrode, and a first leg part of the resistive element which is integral with the main part of the resistive element. Such devices can be secured to circuit boards in a variety of ways, and to elastically deformed terminals. Preferably preferred devices contain two laminar electrodes, with a PTC element between them, and a cross-conductor which passes through the thickness of the device and contacts one only of the two electrodes. The cross-conductor permits connection to both electrodes from the same side of the device, and also makes it possible to carry out the steps for preparing such devices on an assembly which corresponds to a number of individual devices, with division of the assembly as the final step.

Abstract translation: 一种电气装置，包括第一和第二层状电极和夹在它们之间的层状PTC电阻元件，该装置包括：（a）主要部分，其包括第一电极的主要部分，第二电极的主要部分，以及 电阻元件的主要部分; 和（b）第一连接腿，其远离主要部分延伸并且包括与第一电极的主要部分成一体的第一电极的第一腿部和电阻元件的第一腿部， 电阻元件的主要部分。这些装置可以以各种方式固定到电路板，并且可弹性变形的端子。 优选地，优选的装置包含两个层状电极，其间具有PTC元件，并且穿过该器件的厚度并且仅与两个电极中的一个接触的交叉导体。 交叉导体允许从设备的同一侧连接到两个电极，并且还使得可以在对应于多个单独设备的组件上执行用于准备这样的设备的步骤，将组件划分为 最后一步。

公开(公告)号：US20030165051A1

公开(公告)日：2003-09-04

申请号：US10371061

申请日：2003-02-21

Inventor： Kenneth J. Kledzik ,  Jason C. Engle

IPC: H05K007/02 ,  H05K007/06 ,  H05K007/08 ,  H05K007/10

CPC classification number: H05K1/14 ,  H01L25/0652 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2924/01078 ,  H01L2924/15331 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/141 ,  H05K1/144 ,  H05K1/183 ,  H05K3/3436 ,  H05K7/12 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09954 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/1572

Abstract: An apparatus and method is disclosed that allows for the arranging in a three dimensional array semiconductor chips on a circuit board. A unique chip carrier is disclosed on which any IC chip can be positioned on above the other on a circuit board. Additionally, the carrier allows for the testing of IC chips on the carrier and underneath it without having to remove the carrier and chips from the system even if they are of the BGA or CSP type. The carrier includes exposed test points to allow an on site test.

Abstract translation: 公开了允许在电路板上布置三维阵列半导体芯片的装置和方法。 公开了一种独特的芯片载体，其中任何IC芯片可以在电路板上定位在另一个上。 此外，载体允许在载体上并在其下测试IC芯片，而不必从系统中移除载体和芯片，即使它们是BGA或CSP型。 运营商包括暴露的测试点，以便现场测试。

公开(公告)号：US20030157816A1

公开(公告)日：2003-08-21

申请号：US10345057

申请日：2003-01-15

Inventor： Oliver Kiehl ,  Simon Muff

IPC: H01R012/00

CPC classification number: H05K1/0246 ,  H05K1/0295 ,  H05K1/141 ,  H05K2201/09954 ,  H05K2201/10022 ,  H05K2201/10159

Abstract: The present invention provides an apparatus for connecting semiconductor modules, in particular memory banks, having: at least two devices (A, B) for receiving a respective semiconductor module (1, 2); a contact device (13a, 13b, 13c, 13d, 13e, 13f) having a first group of contacts (13a, 13b, 13c, 13d) and a second group of contacts (13e, 13f), the two groups being able to be connected to one another by means of a variable connection module (3, 4); a group of lines (10, 11, 20, 21) for connecting the receiving devices (A, B) to the first group of contacts (13a, 13b, 13c, 13d), a subgroup (13b, 13c) of the first group of contacts being assigned to the lines (10, 11) of the first receiving device (A); the connection module (3, 4) connecting either a subgroup of the contacts (13b, 13c) to the second group of contacts (13e, 13f), or the first group of contacts (13a, 13b, 13c, 13d) to the second group of contacts (13e, 13f). The present invention likewise provides a method for connecting semiconductor modules, in particular memory banks.

Abstract translation: 本发明提供了一种用于连接半导体模块，特别是存储体的装置，其具有：至少两个用于接收相应的半导体模块（1,2）的装置（A，B）; 具有第一组触点（13a，13b，13c，13d）和第二组触点（13e，13f）的接触装置（13a，13b，13c，13d，13e，13f），所述两组能够 通过可变连接模块（3,4）彼此连接; 用于将接收装置（A，B）连接到第一组触点（13a，13b，13c，13d）的一组线路（10,11,20,21），第一组的子组（13b，13c） 的触点分配给第一接收装置（A）的线（10,11）; 连接模块（3,4）将触点（13b，13c）的子组与第二组触点（13e，13f）或第一组触点（13a，13b，13c，13d）连接到第二组 触点组（13e，13f）。 本发明同样提供了用于连接半导体模块，特别是存储体的方法。

公开(公告)号：US06573620B1

公开(公告)日：2003-06-03

申请号：US09001774

申请日：1997-12-31

Applicant: Dennis Craig ,  James Noble

Inventor： Dennis Craig ,  James Noble

IPC: H01L2500

CPC classification number: H05K1/141 ,  H05K1/0268 ,  H05K2201/09954 ,  H05K2201/10189 ,  Y10T307/858

Abstract: A microprocessor assembly is located on a daughterboard, which is configured to be physically and electrically coupled to a motherboard. One of the electrical terminals in an electrical connector between the daughterboard/motherboard is coupled to either a ground or a voltage supply Vdd on the daughterboard, depending on the type of microprocessor used. The electrical connector passes either the ground or Vdd signal to a semiconductor device on the motherboard to automatically identify the type of microprocessor on the daughterboard.

Abstract translation: 微处理器组件位于子板上，其被配置为物理地和电耦合到主板。 取决于所使用的微处理器的类型，子板/母板之间的电连接器中的一个电端子被耦合到子板上的接地或电压源Vdd。 电连接器将接地或Vdd信号传递到主板上的半导体器件，以自动识别子板上的微处理器类型。

公开(公告)号：US20030027434A1

公开(公告)日：2003-02-06

申请号：US10210275

申请日：2002-08-01

Inventor： Steven S. Homer ,  Lee Atkinson ,  Rahul V. Lakdawala

IPC: H01R012/00 ,  H05K001/00

CPC classification number: H05K1/117 ,  H01R27/00 ,  H01R31/08 ,  H05K1/0295 ,  H05K2201/09954 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49169 ,  Y10T29/49204 ,  Y10T29/49208

Abstract: A connection technique for switchably and mutually exclusively coupling a plurality of device sets. The connection technique utilizes a low profile connector having multiple circuit sets, each of which is configured for mutually exclusive and removable insertion into a receptacle coupled to multiple devices. Each one of the multiple circuit sets, which is inserted into the receptacle, couples a desired set of the plurality of device sets.

Abstract translation: 一种用于可互换地并且互相独立地耦合多个设备组的连接技术。 连接技术使用具有多个电路组的低轮廓连接器，每个电路组被配置为互相排斥并且可移除地插入耦合到多个装置的插座中。 插入到插座中的多个电路组中的每一个耦合多个设备组的期望集合。

公开(公告)号：US20030003809A1

公开(公告)日：2003-01-02

申请号：US10034078

申请日：2001-12-27

Applicant: Seagate Technology LLC

Inventor： Michael Alan Maiers

IPC: H01R024/00

CPC classification number: G11B33/122 ,  G11B25/043 ,  H01R12/7017 ,  H01R12/7023 ,  H01R12/7047 ,  H01R12/721 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09954 ,  H05K2201/10325

Abstract: A circuit board connector for connecting a disc drive circuit board to a device outside the disc drive includes a circuit board tab forming part of the circuit board and extending from the circuit board tab. Contact pads are formed on the circuit board tab. A housing attached to the circuit board includes a housing tab extending from the housing, the housing tab being substantially parallel and adjacent to the circuit board tab, such that the circuit board tab and the housing tab together form a connecting tab.

Abstract translation: 用于将盘驱动电路板连接到盘驱动器外部的装置的电路板连接器包括形成电路板的一部分并从电路板接头延伸的电路板接头。 触点焊盘形成在电路板卡舌上。 附接到电路板的壳体包括从壳体延伸的壳体突出部，壳体突片基本上平行并邻近电路板突片，使得电路板突片和壳体突片一起形成连接突片。

公开(公告)号：US6270354B2

公开(公告)日：2001-08-07

申请号：US38720299

申请日：1999-08-31

Applicant: VISTEON GLOBAL TECH INC

Inventor： LI DELIN ,  BAKER JAY DEAVIS ,  ACHARI ACHYUTA ,  NATION BRENDA JOYCE ,  TRUBLOWSKI JOHN

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/22 ,  H05K3/36 ,  H01R12/00

CPC classification number: H05K3/361 ,  H05K1/0292 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09954

Abstract: A multi-connectable printed circuit assembly, comprising: (a) a printed circuit substrate 11 having a first edge 22 and first and second edge regions 44/55, wherein at least the first edge region 44 is defined along the first edge 22; (b) a first array 77 of electrical connection features 66 disposed on or within the substrate proximate the first edge region 44; (c) a second array 88 of electrical connection features 66 disposed on or within the substrate proximate the second edge region 55, wherein the second array 88 is substantially a duplication or a mirror image of the first array 77; and (d) a plurality of circuit traces 99 disposed on or within the substrate such that each electrical connection feature 66 of the first array 77 is connected by one of the circuit traces 99 to a corresponding electrical connection feature 66 of the second array 88.

Abstract translation: 一种多连接印刷电路组件，包括：（a）具有第一边缘22和第一和第二边缘区域44/55的印刷电路基板11，其中至少第一边缘区域44沿着第一边缘22限定; （b）靠近第一边缘区域44设置在基板上或内部的电连接特征66的第一阵列77; （c）设置在靠近第二边缘区域55的衬底上或衬底内的电连接特征66的第二阵列88，其中第二阵列88基本上是第一阵列77的复制或镜像; 和（d）设置在基板上或内部的多个电路迹线99，使得第一阵列77的每个电连接特征66通过电路迹线99之一连接到第二阵列88的对应电连接特征66。

公开(公告)号：US20010001747A1

公开(公告)日：2001-05-24

申请号：US09387202

申请日：1999-08-31

Inventor： DELIN LI ,  JAY DEAVIS BAKER ,  ACHYUTA ACHARI ,  BRENDA JOYCE NATION ,  JOHN TRUBLOWSKI

IPC: H05K001/00

CPC classification number: H05K3/361 ,  H05K1/0292 ,  H05K1/0295 ,  H05K1/117 ,  H05K2201/09227 ,  H05K2201/09954

Abstract: A multi-connectable printed circuit assembly, comprising: (a) a printed circuit substrate 11 having a first edge 22 and first and second edge regions 44/55, wherein at least the first edge region 44 is defined along the first edge 22; (b) a first array 77 of electrical connection features 66 disposed on or within the substrate proximate the first edge region 44; (c) a second array 88 of electrical connection features 66 disposed on or within the substrate proximate the second edge region 55, wherein the second array 88 is substantially a duplication or a mirror image of the first array 77; and (d) a plurality of circuit traces 99 disposed on or within the substrate such that each electrical connection feature 66 of the first array 77 is connected by one of the circuit traces 99 to a corresponding electrical connection feature 66 of the second array 88.

Abstract translation: 一种多连接印刷电路组件，包括：（a）具有第一边缘22和第一和第二边缘区域44/55的印刷电路基板11，其中至少第一边缘区域44沿着第一边缘22限定; （b）靠近第一边缘区域44设置在基板上或内部的电连接特征66的第一阵列77; （c）设置在靠近第二边缘区域55的衬底上或衬底内的电连接特征66的第二阵列88，其中第二阵列88基本上是第一阵列77的复制或镜像; 和（d）设置在基板上或内部的多个电路迹线99，使得第一阵列77的每个电连接特征66通过电路迹线99之一连接到第二阵列88的对应电连接特征66。

公开(公告)号：US06233157B1

公开(公告)日：2001-05-15

申请号：US09223285

申请日：1998-12-30

Applicant: Yong Sik Yoon ,  Young Suk Suh ,  Jung Woo Lee

Inventor： Yong Sik Yoon ,  Young Suk Suh ,  Jung Woo Lee

IPC: H05K702

CPC classification number: G11C5/063 ,  H05K1/0295 ,  H05K3/222 ,  H05K2201/09954 ,  H05K2201/10287 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2203/173 ,  Y02P70/611

Abstract: Disclosed are a printed circuit board and a method for wiring signal lines on the same. Connecting lines for electrically connecting chip select pins of a semiconductor chip, no connect pins and address designate pins, are formed on a PCB. In case of an unstack type, a pad is connected to chip select pin and no connect functioning pin of other semiconductor chip via a first signal line. In case of a stack type, another pad used with a pad is connected to a no connect functioning pin and a chip select pin of the corresponding semiconductor chip having no connection with the first signal line via a second signal line. According to the type of semiconductor chip, e.g. unstack or stack type, a second connecting pad selectively connecting by a first jumper having almost zero resistance value, is disposed between the first and the second signal lines. A first connecting pad is also disposed at the second signal line, the first pad is selectively connected by a second jumper having zero resistance value. Seven connecting pads are disposed on the PCB and an outer pad for transmitting an address signal is connected to three pads which are not disposed adjacently in series. Among the remained four connecting pads, three pads are connected to connecting lines connecting the respective pins of semiconductor chips by signal lines, and the rest is connected to a signal line by another signal line. According to the memory capacity of semiconductor chip, the spaces between the respective connecting pads are selectively connected by jumpers.

Abstract translation: 公开了一种印刷电路板和用于在其上布线信号线的方法。 在PCB上形成用于电连接半导体芯片的芯片选择引脚的连接线，没有连接引脚和地址指针。 在散装型的情况下，焊盘通过第一信号线连接到芯片选择引脚而不连接其他半导体芯片的连接功能引脚。 在堆叠类型的情况下，与焊盘一起使用的另一个焊盘经由第二信号线连接到没有连接功能的引脚和相应的半导体芯片的与第一信号线没有连接的芯片选择引脚。 根据半导体芯片的种类，例如 通过具有几乎为零电阻值的第一跳线选择性地连接的第二连接焊盘设置在第一和第二信号线之间。 第一连接焊盘也设置在第二信号线处，第一焊盘通过具有零电阻值的第二跳线选择性地连接。 七个连接焊盘设置在PCB上，并且用于发送地址信号的外焊盘连接到三个不是相邻地串联设置的焊盘。 在剩余的四个连接焊盘中，三个焊盘通过信号线连接到连接半导体芯片的各个引脚的连接线，而其余的通过另一个信号线连接到信号线。 根据半导体芯片的存储容量，各连接焊盘之间的空间由跳线选择性地连接。

公开(公告)号：US06177632B1

公开(公告)日：2001-01-23

申请号：US09183612

申请日：1998-10-30

Applicant: Glynn Russell Ashdown

Inventor： Glynn Russell Ashdown

IPC: H02G308

CPC classification number: H05K9/0022 ,  H05K1/141 ,  H05K3/301 ,  H05K3/3426 ,  H05K3/3447 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/09954 ,  H05K2201/10386

Abstract: A case for an auxiliary circuit board to be mounted on a main circuit board includes a copper sheet formed into a U-shape in which the auxiliary circuit board is mounted. Mounting pins extend from two edges of the case for positioning the auxiliary circuit board perpendicularly to or parallel to the main circuit board. Mounting pins for through hole mounting and support tabs for surface mounting are provided, the unneeded features being removed prior to use of the case.

Abstract translation: 安装在主电路板上的辅助电路板的壳体包括形成为辅助电路板的U形的铜片。 安装销从壳体的两个边缘延伸，以将辅助电路板垂直于或平行于主电路板。 提供了用于通孔安装的安装销和用于表面安装的支撑卡舌，在使用外壳之前，不需要的特征被移除。