公开(公告)号：US20040080021A1

公开(公告)日：2004-04-29

申请号：US10686116

申请日：2003-10-15

Inventor： Michael D. Casper ,  William B. Mraz

IPC: H01L029/00

CPC classification number: H01L21/4846 ,  H01L23/15 ,  H01L23/49822 ,  H01L25/16 ,  H01L27/016 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/19011 ,  H01Q21/061 ,  H05K1/16 ,  H05K1/162 ,  H05K1/165 ,  H05K3/002 ,  H05K3/4644 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09763 ,  H01L2924/00

Abstract: A system and method for the fabrication of high reliability capacitors (1011), inductors (1012), and multi-layer interconnects (1013) (including resistors (1014)) on various thin film hybrid substrate surfaces (0501) is disclosed. The disclosed method first employs a thin metal layer (0502) deposited and patterned on the substrate (0501). This thin patterned layer (0502) is used to provide both lower electrodes for capacitor structures (0603) and interconnects (0604) between upper electrode components. Next, a dielectric layer (0705) is deposited over the thin patterned layer (0502) and the dielectric layer (0705) is patterned to open contact holes (0806) to the thin patterned layer. The upper electrode layers (0907, 0908, 1009, 1010) are then deposited and patterned on top of the dielectric (0705).

公开(公告)号：US20040053020A1

公开(公告)日：2004-03-18

申请号：US10466886

申请日：2003-07-22

Inventor： Yasuaki Mashiko ,  Hideshi Sekimori ,  Naotomi Takahashi

IPC: B05D005/12 ,  B05D001/36 ,  B32B003/00

CPC classification number: H01G4/1209 ,  C25D11/04 ,  C25D11/18 ,  H01G4/129 ,  H05K1/162 ,  H05K2201/0179 ,  H05K2201/0338 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0315 ,  Y10T428/24917

Abstract: An object of the present invention is to provide a laminate for forming a capacitor layer for a printed wiring board which is capable of ensuring a higher capacitance and an inner layer core material using the laminate for example. In order to achieve this object, a material for forming a capacitor layer comprising a three-layered structure of an aluminum layer 2/a modified alumina barrier layer 3/an electrode copper layer 4 is used, such as a laminate 1a for forming a capacitor layer in which the above described modified alumina barrier layer 3 is obtained through subjecting one side of an aluminum plate or aluminum foil to an anodic treatment to form an alumina barrier layer as a uniform oxide layer and then subjecting the alumina material with the above described alumina barrier layer formed thereon to a boiling and modifying treatment in water and the above described modified aluminum barrier layer 3 is used as a dielectric layer.

Abstract translation: 本发明的目的是提供一种用于形成能够确保较高电容的印刷电路板的电容器层的层叠体，以及使用该层叠体的内层芯材。 为了实现这个目的，使用包括铝层2 /改性氧化铝阻挡层3 /电极铜层4的三层结构的电容器层形成材料，例如用于形成电容器 通过使铝板或铝箔的一面进行阳极处理而形成上述氧化铝阻隔层3，形成氧化铝阻隔层作为均匀的氧化物层，然后将氧化铝材料与上述氧化铝 形成在其上的阻挡层进行在水中的沸腾和改性处理，并且使用上述改性铝阻挡层3作为介电层。

公开(公告)号：US20040020047A1

公开(公告)日：2004-02-05

申请号：US10611868

申请日：2003-07-03

Inventor： Kazuhiro Nishikawa ,  Norihito Tsukahara ,  Hiroyuki Otani

IPC: H05K003/02 ,  H01K003/10 ,  H05K001/00

CPC classification number: H05K3/0017 ,  H05K3/002 ,  H05K3/0041 ,  H05K3/4644 ,  H05K2201/0179 ,  H05K2201/0376 ,  H05K2203/0278 ,  H05K2203/0582 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayered circuit board and a method of forming the multilayer circuit board are provided. In a first circuit forming process P1p, a first circuit 12a is formed on an insulating board 11a with a conductor 12a; in a circuit embedding process P2p, the first circuit 12a is embedded in the insulating board 11a so as to have a predetermined surface flatness S and a predetermined parallelism P; in a masking process P4p, a pilot hole 15, 20 for a via hole 4, 4a is masked at a part of the surface of the circuit 12a; in an insulating layer forming process P5p, an insulating material 11b is applied as a layer to the surface except the mask 14; in an insulating material layer flattening process, the surface of the insulating material layer 11b is flattened so as to have the predetermined surface flatness S and the predetermined parallelism P; and in a pilot hole forming process, the mask 14 is removed.

Abstract translation: 提供了多层电路板和形成多层电路板的方法。 在第一电路形成处理P1p中，第一电路12a形成在具有导体12a的绝缘板11a上; 在电路嵌入处理P2p中，将第一电路12a嵌入绝缘板11a中，以具有预定的表面平坦度S和预定的平行度P; 在掩模处理P4p中，用于通孔4,4a的引导孔15,20被掩蔽在电路12a的表面的一部分; 在绝缘层形成工序P5p中，除了掩模14之外，将绝缘材料11b作为层施加到表面上; 在绝缘材料层平坦化处理中，绝缘材料层11b的表面被平坦化以具有预定的表面平坦度S和预定的平行度P; 并且在导向孔形成处理中，去除掩模14。

公开(公告)号：US20030202281A1

公开(公告)日：2003-10-30

申请号：US10133596

申请日：2002-04-26

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Lin Zhou

IPC: G11B005/60

CPC classification number: G11B5/187 ,  G11B5/484 ,  G11B5/4853 ,  G11B5/486 ,  H05K1/0221 ,  H05K1/056 ,  H05K3/0041 ,  H05K3/048 ,  H05K2201/0179 ,  H05K2201/09809 ,  H05K2203/0733 ,  Y10T29/49025 ,  Y10T29/49027 ,  Y10T29/49032 ,  Y10T29/49155 ,  Y10T29/49194

Abstract: An assembly includes a suspension, a magnetic head assembly, first and second write wires and first and second read wires wherein the magnetic head assembly includes a write head and a read head with the first and second write wires connected to the write head and the first and second read wires connected to the read head and wherein the first and second insulative sheaths are disposed about the first and second read wires and first and second conductive sheaths are disposed about the first and second insulative sheaths. In another aspect of the invention, third and fourth insulative sheaths are disposed about the first and second write wires and third and fourth conductive sheaths are disposed about the third and fourth insulative sheaths.

Abstract translation: 组件包括悬架，磁头组件，第一和第二写入线以及第一和第二读取线，其中磁头组件包括写入头和读取头，其中第一和第二写入线连接到写入头，第一和第二读取线 以及连接到读取头的第二读取线，并且其中第一和第二绝缘护套围绕第一和第二读取线设置，并且第一和第二导电护套围绕第一和第二绝缘护套设置。 在本发明的另一方面，第三和第四绝缘护套围绕第一和第二写入线布置，第三和第四导电护套围绕第三和第四绝缘护套设置。

公开(公告)号：US06603467B1

公开(公告)日：2003-08-05

申请号：US09679254

申请日：2000-10-04

Applicant: Chi-Yuan Wu

Inventor： Chi-Yuan Wu

IPC: G09G500

CPC classification number: H05K3/243 ,  G02F2001/136254 ,  G09G3/006 ,  H05K1/0306 ,  H05K3/18 ,  H05K2201/0179 ,  H05K2203/0574 ,  H05K2203/0582 ,  Y10S345/904

Abstract: A power up test method and apparatus for a liquid crystal display (LCD) panel are disclosed. A power up test panel is used to perform the power up test on a LCD panel which greatly simplifies the test and reduces cost. The power up test panel includes a plurality of test electrodes formed on a substrate. The plurality of test electrodes corresponds one-on-one to a plurality of input electrodes on the LCD panel. The power up test panel makes electrical communication with a host system circuit which generates driving signals for sending to the power up test panel through a flexible film. During the power up test, the electrodes on the power up test panel and the input electrodes are matched and a pressure is applied for performing the electrical signal communication test of the LCD panel. The method is particularly suitable for the power up test of a high resolution LCD panel which has small pitch distance between input electrodes.

Abstract translation: 公开了一种用于液晶显示（LCD）面板的上电测试方法和装置。 上电测试面板用于在LCD面板上进行上电测试，大大简化了测试并降低了成本。 上电测试面板包括形成在基板上的多个测试电极。 多个测试电极与LCD面板上的多个输入电极一一对应。 上电测试面板与主机系统电路进行电气通信，主电路产生驱动信号，通过柔性薄膜发送给上电测试面板。 在上电测试期间，上电测试面板上的电极和输入电极匹配，并施加压力以进行LCD面板的电信号通信测试。 该方法特别适合于在输入电极之间具有小间距距离的高分辨率LCD面板的上电测试。

公开(公告)号：US06597583B1

公开(公告)日：2003-07-22

申请号：US09690375

申请日：2000-10-17

Applicant: Masayuki Sasaki

Inventor： Masayuki Sasaki

IPC: H05K118

CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L2924/0002 ,  H01L2924/3011 ,  H05K3/002 ,  H05K3/4644 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0187 ,  H05K2201/0195 ,  H05K2201/0394 ,  Y10T29/49126 ,  Y10T29/49144 ,  Y10T29/49156 ,  H01L2924/00

Abstract: A multi-layer circuit board comprises: an insulating layer having upper and lower surfaces thereof, and wiring patterns arranged on the upper and lower surfaces of the insulating layer. A ferroelectric layer has a dieletric constant larger than that of the insulating layer and has upper and lower surfaces. The ferroelectric layer is arranged in the insulating layer in such a manner that the upper and lower surfaces of the ferroelectric layer coincide with the upper and lower surfaces of the insulating layer, respectively. A pair of electrode films are formed on the upper and lower surfaces of the ferroelectric layer, respectively, to define a capacitor incorporated in the multi-layer circuit board.

Abstract translation: 多层电路板包括：具有上表面和下表面的绝缘层和布置在绝缘层的上表面和下表面上的布线图案。 铁电层的绝缘常数大于绝缘层，且具有上表面和下表面。 铁电层以绝缘层的上表面和下表面分别与铁电层的上表面和下表面一致的方式设置在绝缘层中。 分别在铁电层的上表面和下表面上形成一对电极膜，以限定并入多层电路板中的电容器。

公开(公告)号：US20030133249A1

公开(公告)日：2003-07-17

申请号：US10368132

申请日：2003-02-14

Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.

Inventor： Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

IPC: H01G004/005

CPC classification number: H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0289 ,  H05K1/141 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/403 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/049 ,  H05K2201/09236 ,  H05K2201/10734

Abstract: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed. An electronic component (10) configured in this manner is mounted on a wiring board, and a semiconductor chip can be mounted thereon. Along with connecting the semiconductor chip to the wiring board via the penetrating electrode (6), the semiconductor chip or the wiring board is connected to the lead electrodes (4, 5). In this manner, while suppressing the size increase of a mounted area, the capacitor or the like can be arranged near the semiconductor chip. Thus, the semiconductor chip is driven with high frequency more easily.

Abstract translation: 电极层（1,2）布置在相互面对的介质层（3）的两侧，以构成电容器。 在电极层（1,2）中形成引线电极（4,5）。 形成与电极层（1,2）绝缘的穿透电极（6）。 以这种方式配置的电子部件（10）安装在布线板上，并且可以在其上安装半导体芯片。 通过穿透电极（6）将半导体芯片与布线板连接，半导体芯片或布线基板与引线电极（4,5）连接。 以这种方式，在抑制安装区域的尺寸增加的同时，电容器等可以布置在半导体芯片附近。 因此，更容易地以高频率驱动半导体芯片。

公开(公告)号：US06574087B1

公开(公告)日：2003-06-03

申请号：US09720279

申请日：2000-12-21

Applicant: Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

Inventor： Kazuyoshi Honda ,  Noriyasu Echigo ,  Masaru Odagiri ,  Takanori Sugimoto

IPC: H01G4005

CPC classification number: H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/0231 ,  H05K1/0289 ,  H05K1/141 ,  H05K1/162 ,  H05K3/0026 ,  H05K3/403 ,  H05K3/467 ,  H05K2201/0179 ,  H05K2201/049 ,  H05K2201/09236 ,  H05K2201/10734

Abstract: Electrode layers (1, 2) are arranged on both sides of a dielectric layer (3) facing each other so as to configure a capacitor. Lead electrodes (4, 5) are formed in the electrode layers (1, 2). A penetrating electrode (6) that is insulated from the electrode layers (1, 2) is formed. An electronic component (10) configured in this manner is mounted on a wiring board, and a semiconductor chip can be mounted thereon. Along with connecting the semiconductor chip to the wiring board via the penetrating electrode (6), the semiconductor chip or the wiring board is connected to the lead electrodes (4, 5). In this manner, while suppressing the size increase of a mounted area, the capacitor or the like can be arranged near the semiconductor chip. Thus, the semiconductor chip is driven with high frequency more easily.

Abstract translation: 电极层（1,2）布置在相互面对的介质层（3）的两侧，以构成电容器。 在电极层（1,2）中形成引线电极（4,5）。 形成与电极层（1,2）绝缘的穿透电极（6）。 以这种方式配置的电子部件（10）安装在布线板上，并且可以在其上安装半导体芯片。 通过穿透电极（6）将半导体芯片与布线板连接，半导体芯片或布线基板与引线电极（4,5）连接。 以这种方式，在抑制安装区域的尺寸增加的同时，电容器等可以布置在半导体芯片附近。 因此，更容易地以高频率驱动半导体芯片。

公开(公告)号：US06545353B2

公开(公告)日：2003-04-08

申请号：US09848799

申请日：2001-05-04

Applicant: Naohiro Mashino

Inventor： Naohiro Mashino

IPC: H01L2334

CPC classification number: H01L23/49822 ,  H01L23/642 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/053 ,  H05K1/056 ,  H05K1/141 ,  H05K1/162 ,  H05K3/445 ,  H05K3/4608 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09809 ,  H05K2203/0315

Abstract: A multilayer wiring board comprises: a metal substrate as a core, a condenser dielectric layer formed to cover the metal layer, and a condenser electrode metal layer formed to cover the condenser dielectric layer, so that a condenser is defined by the metal substrate, the condenser dielectric layer and the condenser electrode metal layer. Integral with the structure of the wiring board is a discrete capacitor component with the metal substrate and the condenser electrode forming the two plates thereof with the dielectric layer there between. The condenser dielectric layer is provided with a first contact hole to communicate with the metal substrate and the condenser electrode metal layer is provided with a second contact hole to communicate with the first contact hole, the diameter of the second contact hole being larger than that of the first contact hole. An insulating layer is formed on the condenser electrode metal layer and is provided with a via hole to communicate with the metal substrate through the second and first contact holes. A metal substrate contact metal layer formed on an inner wall of the via hole, so that the metal substrate contact metal layer comes into electrical contact with the metal substrate.

Abstract translation: 多层布线板包括：作为芯的金属基板，形成为覆盖金属层的电容器电介质层和形成为覆盖电容器电介质层的电容器电极金属层，从而由金属基板限定冷凝器， 电容电介质层和电容器电极金属层。 与布线板的结构一体是具有分离的电容器部件，其中金属基板和电容器电极形成其两个板之间的介电层。 电容电介质层设置有与金属基板连通的第一接触孔，并且电容器电极金属层设置有与第一接触孔连通的第二接触孔，第二接触孔的直径大于 第一接触孔。 绝缘层形成在电容器电极金属层上，并且设置有通孔，以通过第二和第一接触孔与金属基板连通。 金属基板接触金属层形成在通孔的内壁上，金属基板接触金属层与金属基板电接触。

公开(公告)号：US20030049166A1

公开(公告)日：2003-03-13

申请号：US10038276

申请日：2002-01-02

Inventor： Shaun Pendo ,  Rajiv Shah ,  Edward Chernoff

IPC: G01N027/00

CPC classification number: H05K3/28 ,  A61B5/0006 ,  H05K1/0306 ,  H05K3/4061 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/0317 ,  H05K2201/09472 ,  H05K2203/082 ,  H05K2203/085 ,  H05K2203/1147 ,  H05K2203/1476 ,  H05K2203/1572 ,  H05K2203/308

Abstract: A substrate with hermetically sealed vias extending from one side of the substrate to another and a method for fabricating same. The vias may be filled with a conductive material such as, for example, a fritless ink. The conductive path formed by the conductive material aids in sealing one side of the substrate from another. One side of the substrate may include a sensing element and another side of the substrate may include sensing electronics.