公开(公告)号：US5334804A

公开(公告)日：1994-08-02

申请号：US977571

申请日：1992-11-17

Applicant: David G. Love ,  Larry L. Moresco ,  William T. Chou ,  David A. Horine ,  Connie M. Wong ,  Solomon I. Beilin

Inventor： David G. Love ,  Larry L. Moresco ,  William T. Chou ,  David A. Horine ,  Connie M. Wong ,  Solomon I. Beilin

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/32 ,  H01L23/485 ,  H01L23/498 ,  H05K1/11 ,  H05K3/24 ,  H05K3/34 ,  H05K3/40 ,  H05K1/00

CPC classification number: H05K3/4007 ,  H01L21/486 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05599 ,  H01L2224/10126 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13109 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2224/81801 ,  H01L24/02 ,  H01L2924/00013 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/113 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/10378 ,  H05K2201/10674 ,  H05K2201/2081 ,  H05K2203/0315 ,  H05K2203/072 ,  H05K3/243 ,  H05K3/3436 ,  H05K3/3473

Abstract: An interconnect structure for connecting an integrated circuit (IC) chip to a supporting substrate is described. The supporting substrate serves to communicate signals between the IC chip and the "outside world," such as other IC chips. In one embodiment, the interconnect structure comprises an interconnect substrate having a first post disposed on one of its surfaces and a second post disposed on another of its surfaces. One post is for contacting the IC chip and the other is for contacting the major substrate. Each post comprises an elongated body having top and bottom ends, with the bottom end being mounted to one of the substrate surfaces and the top end having a substantially flat surface which is substantially co-planer with the substrate surface. The interconnect substrate further comprises a device for de-concentrating the mechanical stain present at one or both of the top and bottom ends of each post. The first and second posts are electrically coupled to one anther so that an electrical signal may pass from IC chip to the supporting substrate, and vice-versa.

Abstract translation: 描述了用于将集成电路（IC）芯片连接到支撑衬底的互连结构。 支撑衬底用于在IC芯片和“外部世界”之间传送信号，例如其他IC芯片。 在一个实施例中，互连结构包括具有设置在其一个表面上的第一柱和布置在其另一表面上的第二柱的互连衬底。 一个柱子用于接触IC芯片，另一个用于接触主要基板。 每个柱包括具有顶端和底端的细长体，底端安装到一个衬底表面，并且顶端具有与衬底表面基本上共平面的基本平坦的表面。 互连基板还包括用于对存在于每个柱的顶端和底端中的一个或两个处的机械污渍进行去浓缩的装置。 第一和第二柱电耦合到一个花药，使得电信号可以从IC芯片传递到支撑衬底，反之亦然。

公开(公告)号：US5319159A

公开(公告)日：1994-06-07

申请号：US991553

申请日：1992-12-15

Applicant: Kouichi Watanabe ,  Isao Furuhashi

Inventor： Kouichi Watanabe ,  Isao Furuhashi

IPC: H05K1/11 ,  H05K3/00 ,  H05K3/42 ,  H05K1/00

CPC classification number: H05K1/113 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K3/0094

Abstract: A double-sided printed wiring board includes a base plate having a copper foil laminated on each of the opposite sides thereof. The copper foil-laminated base plate has through-holes extending therethrough, and at least one of the through-holes is internally plated for providing a through-via-hole into which a resin filler is provided and solidified. A closed through-via-hole is thus obtained. The copper foil-laminated base plate including the closed through-via-hole is copper-plated, and a particular wiring pattern is formed thereon. A chip land is formed in alignment with the closed through-via-hole.

Abstract translation: 双面印刷布线板包括在其相对的两侧层叠有铜箔的基板。 铜箔层压基板具有贯穿其中的通孔，并且至少一个通孔被内部镀以提供通孔，树脂填料被提供并固化到该通孔中。 由此获得封闭的通孔。 包括封闭通孔的铜箔层压基板镀铜，并在其上形成特定的布线图案。 形成与封闭通孔相对准的芯片焊盘。

公开(公告)号：US5310966A

公开(公告)日：1994-05-10

申请号：US724

申请日：1993-01-05

Applicant: Atsuko Iida ,  Hiroshi Odaira ,  Yoshizumi Sato ,  Yuichi Yamamoto

Inventor： Atsuko Iida ,  Hiroshi Odaira ,  Yoshizumi Sato ,  Yuichi Yamamoto

IPC: H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H05K1/00 ,  H05K1/05 ,  H05K3/02 ,  H05K3/20 ,  H05K3/24 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/44 ,  H05K3/46

CPC classification number: H01L21/4857 ,  H01L23/49866 ,  H01L23/5387 ,  H05K1/056 ,  H05K3/027 ,  H05K3/242 ,  H05K3/388 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K2201/0112 ,  H05K2201/0326 ,  H05K2201/0347 ,  H05K2201/09554 ,  H05K2201/09563 ,  H05K2203/107 ,  H05K3/205 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  Y10S205/917

Abstract: A multi-layer wiring board where a plurality of wiring boards are laminated. The wiring board comprises a flexible insulating layer having a through hole and a wiring pattern formed on the flexible insulating layer. The wiring pattern is composed at least of two conductive layers. The first conductive layer formed on the insulating layer is made of a non-metallic conductor and the first wiring pattern is formed by a laser beam. The second conductive layer is an electroplated layer formed on the first wiring pattern. The first and second conductive layers have different reflectance for a beam. The wiring board is manufactured by integrally laminating a plastic conductive supporting plate wound in a roll shape and an insulating film similarly wound in a roll shape; forming a through hole in a predetermined position of the insulating film; forming the first conductive layer on the laminated body provided with the through hole; forming the first wiring pattern by a laser beam; and forming the electroplated layer on the first wiring pattern.

Abstract translation: 叠层有多个布线基板的多层布线基板。 布线板包括具有通孔的柔性绝缘层和形成在柔性绝缘层上的布线图案。 布线图案至少由两个导电层组成。 形成在绝缘层上的第一导电层由非金属导体制成，并且第一布线图案由激光束形成。 第二导电层是形成在第一布线图案上的电镀层。 第一和第二导电层对于束具有不同的反射率。 通过将卷绕成卷状的塑料导电支撑板和类似地卷绕成卷状的绝缘膜整体地层叠而制造布线板; 在所述绝缘膜的预定位置形成通孔; 在设置有通孔的层叠体上形成第一导电层; 通过激光束形成第一布线图案; 以及在所述第一布线图案上形成所述电镀层。

公开(公告)号：US5298687A

公开(公告)日：1994-03-29

申请号：US43990

申请日：1993-04-07

Applicant: Nahum Rapoport ,  Michael Curley

Inventor： Nahum Rapoport ,  Michael Curley

IPC: H05K1/09 ,  H05K3/24 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K3/246 ,  H05K3/242 ,  H05K3/4685 ,  H05K1/095 ,  H05K2201/0347 ,  H05K2203/0769 ,  H05K2203/0793 ,  Y10T29/49128

Abstract: High density/heavy current hybrid circuit on a ceramic substrate, or other insulating board material, includes first screen printed silver, or copper, polymer seed layer for basic circuitry and bus bar around this circuitry outside the scribe lines, which is connected by removable silver filled polymer links with the circuitry and also the circuit elements are connected with each other by the same links in order to provide uniform electroplating. The links are protected before electroplating with a removable plating resist and they are removed after electroplating using an appropriate stripping solution. Then a permanent plating resist and dielectric polymer thick film isolation layer are applied (for crossovers) on which the second seed layer is applied, plating of the second metal layer occurs and so on until the desired number of layers are done. Thus, cure temperature is that of polymerization, high density, good heat dissipation conditions, heavy current capacity in all the layers and low manufacturing costs are achieved.

Abstract translation: 陶瓷衬底或其他绝缘板材料上的高密度/大电流混合电路包括用于基本电路的第一丝网印刷银或聚合物种子层，以及在划线之外的该电路周围的母线，其通过可移除的银连接 填充的聚合物链路与电路和电路元件通过相同的链路彼此连接，以提供均匀的电镀。 电镀前使用可移除的电镀抗蚀剂保护连接，并在使用适当的剥离溶液进行电镀后将其除去。 然后施加永久电镀抗蚀剂和介电聚合物厚膜隔离层（用于交叉），在其上施加第二籽晶层，发生第二金属层的电镀等，直到完成所需数量的层。 因此，固化温度是聚合温度高，密度高，散热条件好，所有层的大电流容量和制造成本低。

公开(公告)号：US5244833A

公开(公告)日：1993-09-14

申请号：US683893

申请日：1991-04-11

Applicant: Peter Gansauge ,  Volker Kreuter ,  Helmut Schettler

Inventor： Peter Gansauge ,  Volker Kreuter ,  Helmut Schettler

IPC: H01L21/48 ,  H05K1/11 ,  H05K3/06 ,  H05K3/24 ,  H05K3/38

CPC classification number: H01L21/4846 ,  H01L21/4853 ,  H05K3/243 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1147 ,  H01L2224/1403 ,  H01L2924/00013 ,  H05K1/113 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2203/0574 ,  H05K2203/0585 ,  H05K3/061 ,  H05K3/388

Abstract: A method for making an integrated circuit chip packaging structure comprising a substrate, preferably a semiconductor base substrate, a conductive layer on said substrate in regions where connections to metallization layers of the substrate are formed, solder balls and gold bumps connected to said conductive layer in said regions of said conductive layer, and a solder stop layer on said conductive layer at least around said solder balls. The conductive layer further comprises wiring lines. Further, a method of forming the structure is disclosed which uses only two masks for providing terminals for connecting the substrate to integrated circuits and to other substrates or to the printed circuit board and wiring lines. Thus, there is a need for one less metallization layer. The method is applicable to 200 mm wafers and allows two different packaging technologies (C-4 and TAB or wire-bonding) on the same substrate. Thus, packaging of VLSI circuits is improved.

Abstract translation: 一种制造集成电路芯片封装结构的方法，包括：衬底，优选半导体基底衬底，在形成与衬底的金属化层连接的区域中的所述衬底上的导电层，连接到所述导电层的焊球和金凸块 所述导电层的所述区域以及至少在所述焊球周围的所述导电层上的阻焊层。 导电层还包括布线。 此外，公开了一种形成结构的方法，其仅使用两个掩模来提供用于将基板连接到集成电路和其它基板或印刷电路板和布线的端子。 因此，需要少一个金属化层。 该方法适用于200 mm晶圆，并允许在同一基板上使用两种不同的封装技术（C-4和TAB或引线键合）。 因此，VLSI电路的封装得到改善。

公开(公告)号：US5220726A

公开(公告)日：1993-06-22

申请号：US721080

申请日：1991-06-26

Applicant: David A. Mantell

Inventor： David A. Mantell

IPC: H01B5/14 ,  H01L21/48 ,  H01L23/498 ,  H01R11/01 ,  H01R13/03 ,  H01R29/00 ,  H01R43/00 ,  H05K3/10 ,  H05K3/40

CPC classification number: H01L21/486 ,  H01L23/49827 ,  H01R13/03 ,  H05K3/105 ,  H05K3/4092 ,  H01L2924/0002 ,  H01R29/00 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2201/09754 ,  H05K2203/107 ,  H05K2203/1136 ,  H05K3/403 ,  Y10S428/901 ,  Y10T29/49144 ,  Y10T29/49162 ,  Y10T29/49224

Abstract: An electrically connectable module is manufactured from a substrate of an electrically insulating polymer matrix doped with an electrically insulating fibrous filler capable of heat conversion to an electrically conductive fibrous filler to form a fiber-doped substrate. One end of an electrical connector is embedded in the fiber-doped substrate to locate the one end adjacent the surface of the substrate while exposing an opposite end of the electrical connector. The surface of the fiber-doped substrate is locally heated preferably with a laser to form a conductive trace by the in-situ heat conversion of the electrically insulating fibrous filler, the localized heating including the one end of the electrical connector to electrically connect the electrical connector to the conductive trace. In another embodiment, a conductive material is electrodeposited on the conductive trace by applying a voltage to the opposite end of the electrical connector. The substrate is molded into a desired shape to form the module, and a plurality of electrical connectors can be embedded into the substrate in any one of several different standardized arrangements.

公开(公告)号：US5191708A

公开(公告)日：1993-03-09

申请号：US711864

申请日：1991-06-07

Applicant: Susumu Kasukabe ,  Ryuichi Takagi

Inventor： Susumu Kasukabe ,  Ryuichi Takagi

IPC: G01R31/26 ,  G01R1/06 ,  G01R1/067 ,  G01R1/073 ,  H01L21/66 ,  H05K1/09 ,  H05K3/06 ,  H05K3/24 ,  H05K3/40

CPC classification number: G01R1/06711 ,  G01R1/07314 ,  H05K3/4007 ,  H05K1/092 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/09845 ,  H05K2203/0369 ,  H05K2203/0577 ,  H05K2203/1476 ,  H05K3/064 ,  H05K3/246 ,  Y10T29/49117 ,  Y10T29/49155

Abstract: The present invention relates to a manufacturing method of a probe head for an inspection apparatus of a semiconductor device represented by an LSI, and more particularly to a manufacturing method suitable for forming probes with high accuracy in forming into multipins at high density, and is characterized in that a structure is obtained, in which a probe forming conductive lower layer is formed on a formed conductive attaching layer for improving attaching strength after forming electrode pads on a wiring substrate, a mask pattern for forming a probe tip forming conductive upper layer is formed at a position corresponding to the probe position is removed by etching in a cylindrical form until the probe forming conductive lower layer is exposed, a probe tip forming conductive upper layer is grown at the position where etching removal has been performed, a mask pattern is removed, a mask pattern which covers a probe tip forming conductive upper layer is formed thereafter at a position corresponding to the probe position, and the probe forming conductive lower layer is removed by etching in a cylindrical form until the conductive attaching layer is exposed, and pin tips are formed as the small probe tip forming conductive upper layer, thus processing into a pin configuration by removing the conductive attaching layer and the mask.

Abstract translation: 本发明涉及一种由LSI表示的半导体器件的检查装置用探针头的制造方法，更具体地说，涉及一种适于形成高精度的探针的制造方法，其特征在于： 其特征在于，形成导电性下层的探针形成在形成的导电性附着层上，用于在布线基板上形成电极焊盘之后，提高附着强度，形成形成导电性上层的探针尖端的掩模图案 在与探针位置相对应的位置处通过蚀刻以圆筒形式去除直到形成导电下层的探针暴露，在已经执行蚀刻去除的位置处生长形成导电上层的探针尖端，去除掩模图案 之后，在位置c处形成覆盖形成导电性上层的探针尖端的掩模图案 或者对应于探针位置，并且形成导电性下层的探针通过以圆柱形式的蚀刻被除去，直到导电附着层露出，并且形成作为形成导电上层的小探针尖端的针尖，从而处理成针配置 通过去除导电附着层和掩模。

公开(公告)号：US5110384A

公开(公告)日：1992-05-05

申请号：US510316

申请日：1990-04-17

Applicant: Dietmar Dudek ,  Thomas Pfeiffer

Inventor： Dietmar Dudek ,  Thomas Pfeiffer

IPC: G03F7/28 ,  H01B1/02 ,  H01B13/00 ,  H05K1/03 ,  H05K1/09 ,  H05K3/10 ,  H05K3/38

CPC classification number: H05K3/102 ,  G03F7/28 ,  H05K1/0306 ,  H05K2201/0347 ,  H05K2203/0525 ,  H05K2203/1131 ,  H05K3/38

Abstract: A process for making an electrically conductive pattern on a substrate including forming a patterned adhesive layer on the substrate, applying a conductive metal powder to the adhesive layer, and in a second coating pass, applying a powder containing supplementary elements to the pattern. The patterned substrate is fired to volatilize theadhesive layer and sinter the powders. This process can be used to make printed circuits on ceramic substrates which are useful in hybrid circuits, for example.

Abstract translation: 一种在基板上形成导电图案的方法，包括在基板上形成图案化的粘合剂层，将导电金属粉末施加到粘合剂层上，并在第二涂覆过程中，向该图案施加含有补充元素的粉末。 烧制图案化的基底以使粘附层挥发并烧结粉末。 该方法可以用于制造例如在混合电路中有用的陶瓷基板上的印刷电路。

公开(公告)号：US5004672A

公开(公告)日：1991-04-02

申请号：US377123

申请日：1989-07-10

Applicant: Eugene D. D'Ottavio ,  Robert E. Hawkins ,  Stephen S. Rodriguez ,  James Rychwalski

Inventor： Eugene D. D'Ottavio ,  Robert E. Hawkins ,  Stephen S. Rodriguez ,  James Rychwalski

IPC: C23F1/00 ,  G03F7/16 ,  H05K1/00 ,  H05K3/00 ,  H05K3/06 ,  H05K3/10

CPC classification number: H05K3/108 ,  G03F7/164 ,  H05K3/064 ,  H05K1/0284 ,  H05K2201/0347 ,  H05K2201/09118 ,  H05K2203/135 ,  H05K3/062

Abstract: A process for manufacturing a 3-dimensional circuit board by electrophoretic deposition whereby (a) providing the board with a conductive surface and (b) applying a photoresist by electrophoretic deposition.

公开(公告)号：US4946709A

公开(公告)日：1990-08-07

申请号：US395213

申请日：1989-08-17

Applicant: Mitsuyuki Takada ,  Eishi Gofuku ,  Hayato Takasago

Inventor： Mitsuyuki Takada ,  Eishi Gofuku ,  Hayato Takasago

IPC: H01L21/48 ,  H05K1/03 ,  H05K1/09 ,  H05K3/18 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K3/4661 ,  H01L21/481 ,  H01L21/4846 ,  H05K1/0306 ,  H05K1/092 ,  H05K2201/0116 ,  H05K2201/0236 ,  H05K2201/0347 ,  H05K2203/072 ,  H05K3/184 ,  H05K3/246 ,  H05K3/465 ,  Y10T29/49099

Abstract: A method for fabricating a hybrid IC substrate comprises the steps of: preparing an insulating ceramic substrate having a major surface; baking one or more conductors of a first group formed of high melting point metal or alloy thereof on the major surface; covering the conductors of the first group with a first plated film formed by electroless plating; forming an insulating porous active including a glass component and a small amount of a metal component having a catalytic action for electroless plating on the first plated film; and forming one or more conductors of a second group by electroless plating on the active layer, whereby portions of the active layer sandwiched between the conductors of the first and second groups are rendered conductive.

Abstract translation: 一种制造混合IC基板的方法包括以下步骤：制备具有主表面的绝缘陶瓷基片; 在主表面上烘烤由高熔点金属或其合金形成的第一组的一个或多个导体; 用无电镀形成的第一镀膜覆盖第一组导体; 在所述第一镀膜上形成具有玻璃成分和少量金属成分的绝缘多孔活性物质，所述金属成分具有化学镀的催化作用; 以及通过在有源层上进行化学镀来形成第二组的一个或多个导体，由此夹在第一和第二组的导体之间的有源层的部分变得导电。