公开(公告)号：US07650694B2

公开(公告)日：2010-01-26

申请号：US11173461

申请日：2005-06-30

Applicant: Washington M. Mobley

Inventor： Washington M. Mobley

IPC: H05K3/46

CPC classification number: H01L21/4857 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0265 ,  H05K1/0306 ,  H05K1/0313 ,  H05K3/4617 ,  H05K3/4629 ,  H05K2201/0352 ,  H05K2201/0355 ,  H05K2201/098 ,  H05K2203/0723 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49163 ,  Y10T29/49165 ,  H01L2924/00

Abstract: Embodiments include electronic device substrates and methods for forming the same. A method for forming a package comprising a multilayer substrate includes forming a stack of a plurality of dielectric layers comprising a ceramic material, the stack including upper and lower dielectric layers. The method also includes providing a plurality of metallization lines on the dielectric layers in the stack. The method also includes forming a plurality of vias in the dielectric layers, the vias formed to include electrically conductive material therein. A first metal layer is formed on the upper dielectric layer, and a second metal layer is formed on the lower dielectric layer. The first metal layer and the second metal layer are each formed to be at least 250 μm thick. Other embodiments are described and claimed.

Abstract translation: 实施例包括电子器件基板及其形成方法。 一种用于形成包括多层衬底的封装的方法包括形成包括陶瓷材料的多个电介质层的叠层，所述堆叠包括上和下介电层。 该方法还包括在堆叠中的介电层上提供多条金属化线。 该方法还包括在电介质层中形成多个通孔，形成为在其中包括导电材料的通孔。 第一金属层形成在上电介质层上，第二金属层形成在下电介质层上。 第一金属层和第二金属层各自形成为至少250μm厚。 描述和要求保护其他实施例。

公开(公告)号：US07568922B2

公开(公告)日：2009-08-04

申请号：US11304770

申请日：2005-12-16

Applicant: Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

Inventor： Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/3457 ,  H05K2201/0347 ,  H05K2201/09436 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/098 ,  Y10T29/49144 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.

Abstract translation: 本发明提供了一种印刷电路板，其具有焊盘和焊料之间的接合部分的强烈的耐滴落冲击性。 电极焊盘包括装载有焊球的焊盘部分和突出到支撑焊盘部分的焊球的圆柱形部分。 衬垫部分的外边缘从圆筒部分侧向延伸，使得外边缘能够弯曲。 如果当对焊球30施加应力时外边缘弯曲，则可以放松应力集中的焊盘部分的外边缘上的应力，从而加强电极焊盘和焊球之间的接合强度。

公开(公告)号：US20090107710A1

公开(公告)日：2009-04-30

申请号：US11977783

申请日：2007-10-26

Applicant: Joel R. Goergen

Inventor： Joel R. Goergen

IPC: H05K1/00 ,  H05K3/36

CPC classification number: H05K1/0242 ,  H01P3/081 ,  H05K1/0245 ,  H05K2201/09236 ,  H05K2201/09745 ,  H05K2201/098 ,  Y10T29/49126

Abstract: Circuit boards and methods for their manufacture are disclosed. The circuit boards carry high-speed signals using conductors formed to include lengthwise channels. The channels increase the surface area of the conductors, and therefore enhance the ability of the conductors to carry high-speed signals. In at least some embodiments, a discontinuity also exists between the dielectric constant within the channels and just outside the channels, which is believed to reduce signal loss into the dielectric material.

Abstract translation: 公开了电路板及其制造方法。 电路板使用形成为包括纵向通道的导体承载高速信号。 通道增加了导体的表面积，从而增强了导体承载高速信号的能力。 在至少一些实施例中，通道内的介电常数和通道之外的介质常数之间也存在不连续性，这被认为可减少信号损耗。

公开(公告)号：US07523548B2

公开(公告)日：2009-04-28

申请号：US10580948

申请日：2004-12-02

Applicant: Tatsuo Kataoka ,  Yoshikazu Akashi ,  Yutaka Iguchi

Inventor： Tatsuo Kataoka ,  Yoshikazu Akashi ,  Yutaka Iguchi

IPC: H05K3/02 ,  B05D5/12

CPC classification number: H05K3/06 ,  H05K3/381 ,  H05K3/388 ,  H05K2201/0338 ,  H05K2201/098 ,  Y10T29/49124 ,  Y10T29/49155 ,  Y10T29/5164

Abstract: A process for producing a printed wiring board comprises the steps of depositing a base metal on at least one surface of an insulating film to form a base metal layer and further depositing copper or a copper alloy to form a conductive metal layer, then removing a surface metal layer, which is formed through the above step, by etching to form a wiring pattern, and then treating the base metal layer with a treating liquid capable of dissolving and/or passivating the metal that forms the base metal layer. The printed wiring board so provided comprises an insulating film and a wiring pattern formed on at least one surface of the insulating film, the wiring pattern including a base metal layer deposited on the insulating film surface and a conductive metal layer, the base metal layer for forming the wiring pattern protrudes in a widthwise direction more than the conductive metal layer for forming the wiring pattern.

Abstract translation: 一种制造印刷电路板的方法包括以下步骤：在绝缘膜的至少一个表面上沉积贱金属以形成贱金属层，并进一步沉积铜或铜合金以形成导电金属层，然后除去表面 通过蚀刻形成布线图案，然后用能够溶解和/或钝化形成基底金属层的金属的处理液对基底金属层进行处理。 所提供的印刷电路板包括绝缘膜和形成在绝缘膜的至少一个表面上的布线图案，布线图案包括沉积在绝缘膜表面上的基底金属层和导电金属层，所述基底金属层用于 形成布线图案比形成布线图案的导电金属层的宽度方向突出。

公开(公告)号：US20090092789A1

公开(公告)日：2009-04-09

申请号：US11992209

申请日：2006-08-22

Applicant: Katsuyuki Tsuchida ,  Hironori Kobayashi ,  Ryu Murakami ,  Masashi Kumagai

Inventor： Katsuyuki Tsuchida ,  Hironori Kobayashi ,  Ryu Murakami ,  Masashi Kumagai

IPC: D06N7/04

CPC classification number: H05K1/09 ,  B32B15/08 ,  B32B15/20 ,  B32B27/281 ,  B32B2307/206 ,  H05K1/0346 ,  H05K1/0393 ,  H05K3/108 ,  H05K3/28 ,  H05K3/382 ,  H05K3/388 ,  H05K2201/0355 ,  H05K2201/098 ,  H05K2203/0723 ,  Y10T428/24355

Abstract: The invention provides a two-layer flexible substrate free of surface defects and having excellent etching characteristics and adherence to resist.The two-layer flexible substrate has a copper layer provided on one or both faces of an insulator film without using an adhesive, wherein the surface roughness (Ra) of the copper layer is 0.10 to 0.25 μm, and wherein the average crystal grain size [of copper] is no greater than 0.8 μm at 1 μm from the insulator film in the cross section of the copper layer. Preferably, the insulator film is a polyimide film.

Abstract translation: 本发明提供一种没有表面缺陷且具有优异的蚀刻特性和抗粘附性的双层柔性基材。 双层柔性基板在不使用粘合剂的情况下，在绝缘膜的一面或两面上具有铜层，其中铜层的表面粗糙度（Ra）为0.10〜0.25μm，平均结晶粒径[ 的铜]在铜层的截面中距离绝缘膜1个1um时不大于0.8μm。 优选地，绝缘膜是聚酰亚胺膜。

公开(公告)号：US20090085095A1

公开(公告)日：2009-04-02

申请号：US12243880

申请日：2008-10-01

Applicant: Arvind KAMATH ,  Erik SCHER ,  Patrick SMITH ,  Aditi CHANDRA ,  Steven MOLESA

Inventor： Arvind KAMATH ,  Erik SCHER ,  Patrick SMITH ,  Aditi CHANDRA ,  Steven MOLESA

IPC: H01L29/788 ,  H01L29/786 ,  H01L29/00 ,  H01L21/208

CPC classification number: H01L21/36 ,  C23C18/08 ,  C23C18/122 ,  C23C18/1245 ,  C23C18/1295 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/28273 ,  H01L21/28518 ,  H01L21/288 ,  H01L21/76871 ,  H01L21/76895 ,  H01L27/1285 ,  H01L27/1292 ,  H01L28/40 ,  H01L29/0657 ,  H01L29/66143 ,  H01L29/6675 ,  H01L29/7881 ,  H01L29/872 ,  H05K1/16 ,  H05K1/162 ,  H05K3/125 ,  H05K2201/098

Abstract: The present invention relates to electrically active devices (e.g., capacitors, transistors, diodes, floating gate memory cells, etc.) having dielectric, conductor, and/or semiconductor layers with smooth and/or dome-shaped profiles and methods of forming such devices by depositing or printing (e.g., inkjet printing) an ink composition that includes a semiconductor, metal, or dielectric precursor. The smooth and/or dome-shaped cross-sectional profile allows for smooth topological transitions without sharp steps, preventing feature discontinuities during deposition and allowing for more complete step coverage of subsequently deposited structures. The inventive profile allows for both the uniform growth of oxide layers by thermal oxidation, and substantially uniform etching rates of the structures. Such oxide layers may have a uniform thickness and provide substantially complete coverage of the underlying electrically active feature. Uniform etching allows for an efficient method of reducing a critical dimension of an electrically active structure by simple isotropic etch.

Abstract translation: 本发明涉及具有平滑和/或圆顶形轮廓的电介质，导体和/或半导体层的电活性器件（例如，电容器，晶体管，二极管，浮动栅极存储单元等）和形成这种器件的方法 通过沉积或印刷（例如喷墨印刷）包括半导体，金属或电介质前体的油墨组合物。 平滑和/或圆顶形的横截面轮廓允许平滑的拓扑转变而没有尖锐的步骤，防止沉积期间的特征不连续性，并允许随后沉积的结构的更完整的阶梯覆盖。 本发明的轮廓允许通过热氧化均匀生长氧化物层，以及基本均匀的结构蚀刻速率。 这样的氧化物层可以具有均匀的厚度并且提供基本的电活性特征的基本上完整的覆盖。 均匀蚀刻允许通过简单的各向同性蚀刻来降低电活性结构的临界尺寸的有效方法。

公开(公告)号：US20090042144A1

公开(公告)日：2009-02-12

申请号：US12244870

申请日：2008-10-03

Applicant: Tomofumi KITADA ,  Hiroki Maruo ,  Ryo Takami

Inventor： Tomofumi KITADA ,  Hiroki Maruo ,  Ryo Takami

IPC: G03F7/20

CPC classification number: H05K3/363 ,  H01L2924/0002 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract translation: 一种电路板互连结构，具有第一印刷线路板，其中第一导电电路布置在第一绝缘层上，所述第一导电电路在其端部上具有第一连接端子，其中上表面宽度窄于 底面宽度; 第二印刷线路板，其中具有第二连接端子的第二导电层布置在第二绝缘层上; 以及连接层，其沿着所述第一连接端子的纵向侧表面形成圆角，并且使所述第一连接端子和所述第二连接端子互连。 第一连接端子可以具有突出部分。

公开(公告)号：US20090020316A1

公开(公告)日：2009-01-22

申请号：US12033876

申请日：2008-02-19

Applicant: Chia-Hui Wu ,  Pai-Sheng Cheng ,  Po-Chiang Tseng

Inventor： Chia-Hui Wu ,  Pai-Sheng Cheng ,  Po-Chiang Tseng

IPC: H05K1/00 ,  H05K3/00

CPC classification number: H01L23/4985 ,  H01L21/4846 ,  H01L23/49822 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2224/16225 ,  H05K1/111 ,  H05K2201/098 ,  H05K2201/10674 ,  Y02P70/611 ,  Y10T29/49155

Abstract: A method of manufacturing a chip on film (COF) is provided, including: providing a flexible circuit board; and forming a plurality of leads on the flexible circuit board. Each of the leads has a thickness of 8 um˜15 um and a cross-section shape is substantially rectangular. A COF structure, having a flexible circuit board and a plurality of leads formed on the flexible circuit board, is provided. Each lead has a thickness of 8 um˜15 um, and lead widths of the leads are based on pitch widths of a plurality of bumps corresponding to the leads. A COF structure, having a flexible circuit board and a plurality of leads formed on the flexible circuit board. Each of the leads has a thickness of 8 um˜15 um, and a lead width of each of the leads is greater than a bump width minus 4 um.

Abstract translation: 提供一种制造薄膜（COF）的方法，包括：提供柔性电路板; 以及在所述柔性电路板上形成多个引线。 每个引线的厚度为8um〜15μm，截面形状基本上为矩形。 提供了一种COF结构，其具有柔性电路板和形成在柔性电路板上的多个引线。 每个引线的厚度为8um〜15μm，引线的引线宽度基于对应于引线的多个凸块的间距宽度。 COF结构，具有柔性电路板和形成在柔性电路板上的多个引线。 每个引线的厚度为8um〜15um，每个引线的引线宽度大于凹凸宽度减去4um。

公开(公告)号：US20080142985A1

公开(公告)日：2008-06-19

申请号：US11640262

申请日：2006-12-18

Applicant: Wen-Jeng Fan

Inventor： Wen-Jeng Fan

IPC: H01L23/48

CPC classification number: H05K1/0271 ,  H01L23/498 ,  H01L2924/0002 ,  H05K1/0265 ,  H05K3/28 ,  H05K2201/09672 ,  H05K2201/098 ,  H05K2203/0733 ,  H01L2924/00

Abstract: A wiring substrate with tensile-strength enhanced traces primarily comprises a core layer, a plurality of connecting pads, a plurality of traces, and a solder resist where the connecting pads and the traces are disposed on a top of the core layer. The solder resist is formed over the top of the core layer to cover the traces with the connecting pads partially or completely exposed. Furthermore, the traces have I-shaped cross sections to enhance the tensile strength of the traces.

Abstract translation: 具有拉伸强度增强迹线的布线基板主要包括芯层，多个连接焊盘，多个迹线和阻焊层，其中连接焊盘和迹线设置在芯层的顶部。 阻焊层形成在芯层的顶部上，以覆盖具有部分或完全暴露的连接焊盘的迹线。 此外，迹线具有I形横截面以增强迹线的拉伸强度。

公开(公告)号：US20070273045A1

公开(公告)日：2007-11-29

申请号：US11752843

申请日：2007-05-23

Applicant: Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

Inventor： Tomofumi Kitada ,  Hiroki Maruo ,  Ryo Takami

IPC: H01L23/48 ,  H01L21/00

CPC classification number: H05K3/363 ,  H01L2924/0002 ,  H05K2201/09745 ,  H05K2201/098 ,  H05K2201/09845 ,  H01L2924/00

Abstract: A board interconnection structure having a first printed wiring board in which a first conductive circuit is arranged on a first insulating layer, the first conductive circuit having, on an end portion thereof, a first connection terminal in which an upper surface width is narrower than a bottom surface width; a second printed wiring board in which a second conductive layer having a second connection terminal is arranged on a second insulating layer; and a connection layer that forms fillets along longitudinal side surfaces of the first connection terminal, and interconnects the first connection terminal and the second connection terminal. The first connection terminal may have a projection portion.

Abstract translation: 一种电路板互连结构，具有第一印刷线路板，其中第一导电电路布置在第一绝缘层上，所述第一导电电路在其端部上具有第一连接端子，其中上表面宽度窄于 底面宽度; 第二印刷线路板，其中具有第二连接端子的第二导电层布置在第二绝缘层上; 以及连接层，其沿着所述第一连接端子的纵向侧表面形成圆角，并且将所述第一连接端子和所述第二连接端子互连。 第一连接端子可以具有突出部分。