公开(公告)号：US07145782B2

公开(公告)日：2006-12-05

申请号：US10892804

申请日：2004-07-16

Applicant: Damion Searls ,  Edward Osburn

Inventor： Damion Searls ,  Edward Osburn

IPC: H05K7/06 ,  H01L23/48

CPC classification number: H01L23/49844 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/1531 ,  H01L2924/19106 ,  H05K1/023 ,  H05K1/0231 ,  H05K1/0262 ,  H05K1/181 ,  H05K2201/1006 ,  H05K2201/10166 ,  H05K2201/10325 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10704 ,  Y10T29/4913 ,  Y10T29/49147 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In one embodiment, the present invention includes a method of mounting a semiconductor device to a first side of a circuit board; and mounting at least one voltage regulator device to a second side of the circuit board, the second side opposite to the first side. The voltage regulator devices may be output filters, inductors, capacitors, and the like. In certain embodiments, the devices may be located directly underneath the semiconductor device.

公开(公告)号：US20060208348A1

公开(公告)日：2006-09-21

申请号：US11378685

申请日：2006-03-17

Applicant: Tohru Ohsaka ,  Hiroshi Kondo

Inventor： Tohru Ohsaka ,  Hiroshi Kondo

IPC: H01L23/02

CPC classification number: H05K1/141 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/97 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0263 ,  H05K1/145 ,  H05K3/3436 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00 ,  H01L2224/0401

Abstract: In a stacked semiconductor package, since electric power is supplied to a second semiconductor package through a first semiconductor package, a power supply path becomes complicated and fluctuation of its inductance becomes large, whereby power bounce occurs to reduce signal quality and also prevent high speed signal communication. Therefore, according to the present invention, a first solder ball group for joint to a printed wiring board is attached to a second layer of the first semiconductor package, and a second solder ball group for joint to the first semiconductor package and a solder group for power supply for direct joint to the printed wiring board are provided on the second layer of the second semiconductor package, whereby electric power can be directly supplied from the printed wiring board.

Abstract translation: 在层叠半导体封装中，由于通过第一半导体封装向第二半导体封装供给电力，电源路径变得复杂，电感的波动变大，因此发生电源反弹以降低信号质量并且还防止高速信号 通讯。 因此，根据本发明，与第一半导体封装的第二层和第一半导体封装的接合用的第二焊球组和用于与第一半导体封装接合的第二焊球组， 用于直接接合到印刷线路板的电源设置在第二半导体封装的第二层上，从而可以从印刷线路板直接供应电力。

公开(公告)号：US07101730B2

公开(公告)日：2006-09-05

申请号：US10919090

申请日：2004-08-16

Applicant: Todd O. Bolken ,  Cary J. Baerlocher ,  Chad A. Cobbley ,  David J. Corisis

Inventor： Todd O. Bolken ,  Cary J. Baerlocher ,  Chad A. Cobbley ,  David J. Corisis

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/4763

CPC classification number: H05K3/303 ,  H01L25/105 ,  H01L25/18 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1082 ,  H01L2924/0002 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/10515 ,  H05K2201/10734 ,  H05K2203/167 ,  Y02P70/613 ,  H01L2924/00

Abstract: A method of manufacturing a stackable package to create a 3-dimensional memory array using ball grid array technology. Specifically, memory chips are coupled to a preformed packages which have alignment features to allow for the stacking of the ball grid arrays. The alignment features are used to align and orient each package with respect to an adjacent package, substrate or printed circuit board. The alignment features also support the weight of the adjacent package during solder ball reflow to maintain stack height and parallelism between packages. Each memory device is serially connected to the adjacent memory device through the vias and solder balls on each package.

Abstract translation: 使用球栅阵列技术制造可堆叠封装以创建3维存储器阵列的方法。 具体地，存储器芯片耦合到具有对准特征以允许球栅阵列的堆叠的预成型封装。 对准特征用于相对于相邻的封装，衬底​​或印刷电路板对准和定向每个封装。 对准特征还支持焊球回流期间相邻封装的重量，以保持堆叠高度和封装之间的平行度。 每个存储器件通过每个封装上的通孔和焊球串联连接到相邻的存储器件。

公开(公告)号：US07091619B2

公开(公告)日：2006-08-15

申请号：US10805499

申请日：2004-03-19

Applicant: Akiyoshi Aoyagi

Inventor： Akiyoshi Aoyagi

IPC: H01L23/02

CPC classification number: H01L23/49816 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/1053 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/05599

Abstract: A method is provided to enhance the connection reliability in three-dimensional mounting while considering the warping of packages. Opening diameters of the openings provided corresponding to protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of a carrier substrate, and the opening diameters of openings provided corresponding to the protruding electrodes, respectively, are set so as to gradually decrease from the central portion toward the outer peripheral portion of another carrier substrate.

Abstract translation: 提供了一种在考虑包装翘曲的同时增强三维安装中的连接可靠性的方法。 分别对应于突出电极设置的开口的开口直径被设定为从载体基板的中心部分朝向外周部分逐渐减小，并且分别对应于突出电极设置的开口的开口直径为 被设定为从另一个载体基板的中央部朝向外周部逐渐减小。

公开(公告)号：US20060157843A1

公开(公告)日：2006-07-20

申请号：US11332185

申请日：2006-01-17

Applicant: Sung-Wook Hwang

Inventor： Sung-Wook Hwang

IPC: H01L23/02

CPC classification number: H05K1/141 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/15311 ,  H01L2924/15331 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package including a number of solder ball pads formed on a lower surface of an interposing print circuit board, which is smaller than that of solder ball pads formed on an upper surface thereof, a pitch of the solder ball pads formed on the lower surface of the interposing print circuit board is greater than a pitch of the solder ball pads formed on the upper interposing print circuit board.

公开(公告)号：US20060120056A1

公开(公告)日：2006-06-08

申请号：US11290314

申请日：2005-11-29

Applicant: Yorihiko Sasaki

Inventor： Yorihiko Sasaki

IPC: H05K7/00 ,  H05K3/20

CPC classification number: H01L23/4334 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/3107 ,  H01L23/36 ,  H01L23/49575 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06524 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06586 ,  H01L2225/06589 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/0203 ,  H05K1/0207 ,  H05K1/187 ,  H05K3/205 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/063 ,  Y10T29/49128 ,  Y10T29/49155 ,  H01L2224/0401

Abstract: A circuit component module includes a heat-releasing plate, a resin film stacked on a surface of the heat-releasing plate, an electronic component embedded in the first resin film and partially in contact with the heat-releasing plate, and a wiring pattern embedded in the surface of the first resin film opposite the heat-releasing plate. The wiring pattern forms a circuit in combination with the electronic component.

公开(公告)号：US20060113653A1

公开(公告)日：2006-06-01

申请号：US11002480

申请日：2004-12-01

Applicant: Sherry Xiaoqi ,  Cam Nguyen

Inventor： Sherry Xiaoqi ,  Cam Nguyen

IPC: H01L23/02

CPC classification number: H05K1/141 ,  H01L23/5385 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/1515 ,  H01L2924/15159 ,  H01L2924/15192 ,  H05K1/0284 ,  H05K1/182 ,  H05K3/3436 ,  H05K2201/09072 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2201/10734 ,  H05K2203/1572 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A stack package for a high density memory module includes at least one memory chip, an ASIC and an interposer, wherein the interposer comprises a first surface having contacts arranged in electrical communication with corresponding contacts on the ASIC and a second, substantially opposite surface including contacts arranged in electrical communication with corresponding contacts on a PCB. The at least one memory chip is dimensioned to fit within a cutout section in the interposer.

Abstract translation: 用于高密度存储器模块的堆叠封装包括至少一个存储器芯片，ASIC和插入器，其中所述插入器包括第一表面，所述第一表面具有布置成与所述ASIC上的对应触点电连通的触点和包括触点的第二基本上相对的表面 布置成与PCB上的相应触点电连通。 所述至少一个存储器芯片的尺寸被设计成装配在所述插入器中的切口部分内。

公开(公告)号：US20060108607A1

公开(公告)日：2006-05-25

申请号：US11321811

申请日：2005-12-29

Applicant: Yasuhiro Teshima ,  Noboru Nakama

Inventor： Yasuhiro Teshima ,  Noboru Nakama

IPC: H01L27/10

CPC classification number: H05K1/0231 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/66 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/16 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16235 ,  H01L2224/16265 ,  H01L2224/17104 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19103 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H05K1/023 ,  H05K1/025 ,  H05K1/111 ,  H05K3/3436 ,  H05K3/3442 ,  H05K2201/10022 ,  H05K2201/10515 ,  H05K2201/10636 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00012

Abstract: Disclosed are an integrated circuit component capable of simply mounting at low cost a chip part which adjusts impedance of wiring patterns as well as capable of effectively reducing switching noise from an integrated circuit, and a method for mounting the chip part. The integrated circuit component of the present invention has a constitution that a bypass capacitor is mounted on a wiring board side of a gap between the wiring board and an LSI chip. Therefore, as compared with a case where the capacitor is mounted on the LSI chip side, a transmission path through the capacitor can be extremely shortened. As a result, inductance components of the feeder line can be reduced, so that a response delay of power transmitted through the feeder line can be sufficiently suppressed.

Abstract translation: 公开了能够以低成本简单地安装芯片部分的集成电路部件，其调整布线图案的阻抗以及能够有效地降低集成电路的开关噪声，以及用于安装芯片部分的方法。 本发明的集成电路部件具有在布线基板和LSI芯片之间的间隙的布线基板侧安装旁路电容器的结构。 因此，与将电容器安装在LSI芯片侧的情况相比，可以极大地缩短通过电容器的传输路径。 结果，可以减少馈电线路的电感分量，从而可以充分抑制通过馈电线路传输的功率的响应延迟。

公开(公告)号：US20060107524A1

公开(公告)日：2006-05-25

申请号：US11270317

申请日：2005-11-09

Applicant: Jason Engle ,  Rhandee Abrio ,  Julie Bradbury-Bennett ,  Greg Allee ,  Kenneth Kledzik

Inventor： Jason Engle ,  Rhandee Abrio ,  Julie Bradbury-Bennett ,  Greg Allee ,  Kenneth Kledzik

IPC: H05K3/34 ,  B23P19/00

CPC classification number: B23P23/00 ,  B23P19/00 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/16152 ,  H01L2924/1627 ,  H05K1/023 ,  H05K1/0284 ,  H05K1/141 ,  H05K1/144 ,  H05K13/0434 ,  H05K13/0482 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2201/10734 ,  Y10T29/49133 ,  Y10T29/49144 ,  Y10T29/5137 ,  Y10T29/53174 ,  Y10T29/53178 ,  Y10T29/53183 ,  Y10T29/53261 ,  H01L2224/0401

Abstract: A method and apparatus for fabricating a three dimensional array of semiconductor chips is disclosed. The method uses a multiple step fabrication process that automates the surface mounting of semiconductor chips with unique chip carriers to achieve the three dimensional array of chips. The method can include the steps of depositing solder on one or more chip modules, placing and interconnecting low-cost components on the chip modules, and storing the preprocessed chip modules in pallets or in a tape and reel. Later these chip carriers may then be mounted on a circuit board, possibly over; for example, low and/or high cost components and then populated with low and/or high cost components. The apparatus includes a unique stackable chip module pallet and print fixture pedestal.

Abstract translation: 公开了一种用于制造半导体芯片的三维阵列的方法和装置。 该方法使用多步制造工艺，其使得具有独特芯片载体的半导体芯片的表面安装自动化以实现芯片的三维阵列。 该方法可以包括以下步骤：在一个或多个芯片模块上沉积焊料，将低成本部件放置和互连在芯片模块上，并将预处理的芯片模块存储在托盘中或磁带和卷轴中。 然后可以将这些芯片载体安装在电路板上， 例如低成本和/或高成本组件，然后填充低成本和/或高成本组件。 该设备包括独特的可堆叠芯片模块托盘和打印夹具底座。

公开(公告)号：US20060072368A1

公开(公告)日：2006-04-06

申请号：US10952891

申请日：2004-09-30

Applicant: Wei Koh ,  David Chen

Inventor： Wei Koh ,  David Chen

IPC: G11C8/02

CPC classification number: H05K1/182 ,  G11C5/02 ,  H01L25/0652 ,  H01L25/105 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/0002 ,  H05K2201/10515 ,  H05K2201/10545 ,  H05K2201/10689 ,  H01L2924/00

Abstract: A high density memory card assembly having application for USB drive storage, flash and ROM memory cards, and similar memory card formats. A cavity is formed through a rigid laminate substrate. First and second digital memory devices (e.g., TSOP packages or bare semiconductor dies) are located within the cavity so as to be recessed relative to the top and bottom of the substrate. The recessed first and second memory devices are arranged in spaced, face-to-face alignment with one another within the cavity. The first and second memory devices are covered and protected by respective first and second memory packages that are located on the top and bottom of the substrate. By virtue of the foregoing, the memory package density of the assembly can be increased without increasing the height or area consumed by the assembly for receipt within an existing external housing.

Abstract translation: 适用于USB驱动器存储，闪存和ROM存储卡以及类似存储卡格式的高密度存储卡组件。 通过刚性层压基板形成空腔。 第一和第二数字存储器件（例如，TSOP封装或裸半导体管芯）位于空腔内，以便相对于衬底的顶部和底部凹陷。 凹陷的第一和第二存储器件在空腔内彼此间隔开地面对面地排列。 第一和第二存储器件被位于衬底顶部和底部的相应的第一和第二存储器封装覆盖和保护。 由于上述原因，可以增加组件的存储器封装密度，而不会增加组件消耗的高度或面积，以便在现有的外部外壳内接收。