公开(公告)号：US20130341806A1

公开(公告)日：2013-12-26

申请号：US13654713

申请日：2012-10-18

Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.

Inventor： Chang-Fu Lin ,  Ho-Yi Tsai ,  Chin-Tsai Yao

IPC: H05K1/00 ,  H01L23/488

CPC classification number: H01L24/16 ,  H01L23/49816 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2924/00014 ,  H05K1/111 ,  H05K3/3436 ,  H05K2201/09727 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2224/05552

Abstract: A substrate structure is provided, including a substrate body and a plurality of circuits formed on the substrate body. At least one of the circuits has an electrical contact for connecting to an external element and the electrical contact is narrower in width than the circuit, thereby meeting the requirements of fine line/fine pitch and miniaturization, improving the product yield and reducing the fabrication cost.

Abstract translation: 提供了一种基板结构，包括基板主体和形成在基板主体上的多个电路。 至少一个电路具有用于连接到外部元件的电触点，并且电触头的宽度比电路窄，从而满足细线/细间距和小型化的要求，提高产品产量并降低制造成本 。

公开(公告)号：US08599571B2

公开(公告)日：2013-12-03

申请号：US12279915

申请日：2007-04-18

Applicant: Hidenobu Nishikawa ,  Daido Komyoji ,  Atsunobu Iwamoto ,  Hiroyuki Yamada ,  Shuichi Takeda ,  Shigeru Kondou

Inventor： Hidenobu Nishikawa ,  Daido Komyoji ,  Atsunobu Iwamoto ,  Hiroyuki Yamada ,  Shuichi Takeda ,  Shigeru Kondou

IPC: H01L23/12 ,  H01L23/02 ,  H01L23/34 ,  H05K7/00 ,  H05K7/20 ,  H05K1/11

CPC classification number: H05K1/0271 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2924/19105 ,  H05K3/284 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Memory card (1) includes at least semiconductor chip (3), circuit board (2) with semiconductor chip (3) mounted on main surface (21), having at least rigidity reducing portion (23) formed in main surface (21) or in a linear region of surface (22) opposite to the main surface, and cover portion (71) for covering semiconductor chip (3) on main surface (21) of circuit board (2), wherein circuit board (2) has a plurality of convex regions (201) which flex in a convex shape toward main surface (21) due to rigidity reducing portion (23).

Abstract translation: 存储卡（1）至少包括半导体芯片（3），具有安装在主表面（21）上的半导体芯片（3）的电路板（2），至少具有形成在主表面（21）中的刚性减小部分（23）或 在与所述主表面相对的表面（22）的直线区域中，以及用于覆盖电路板（2）的主表面（21）上的半导体芯片（3）的盖部分（71），其中电路板（2）具有多个 由刚性减小部分（23）向主表面（21）弯曲成凸形的凸区域（201）。

公开(公告)号：US20130316534A1

公开(公告)日：2013-11-28

申请号：US13959003

申请日：2013-08-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Douriet ,  Francesco Preda ,  Brian L. Singletary ,  Lloyd A. Walls

IPC: H01L21/768

CPC classification number: H01L21/768 ,  H01L23/49827 ,  H01L23/50 ,  H01L24/16 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19105 ,  H05K1/0231 ,  H05K1/0263 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718 ,  H05K2201/10674 ,  Y10T29/49165

Abstract: A circuit substrate uses post-fed top side power supply connections to provide improved routing flexibility and lower power supply voltage drop/power loss. Plated-through holes are used near the outside edges of the substrate to provide power supply connections to the top metal layers of the substrate adjacent to the die, which act as power supply planes. Pins are inserted through the plated-through holes to further lower the resistance of the power supply path(s). The bottom ends of the pins may extend past the bottom of the substrate to provide solderable interconnects for the power supply connections, or the bottom ends of the pins may be soldered to “jog” circuit patterns on a bottom metal layer of the substrate which connect the pins to one or more power supply terminals of an integrated circuit package including the substrate.

Abstract translation: 电路基板使用后馈电顶部电源连接来提供改进的布线灵活性和较低的电源电压降/功率损耗。 在基板的外边缘附近使用电镀通孔，以提供与作为电源平面的管芯相邻的基板的顶部金属层的电源连接。 引脚插入通过电镀通孔以进一步降低电源路径的电阻。 引脚的底端可以延伸越过基板的底部以提供用于电源连接的可焊接互连，或者引脚的底端可以被焊接到基板的底部金属层上的“点动”电路图案，其连接 引脚连接到包括基板的集成电路封装的一个或多个电源端子。

公开(公告)号：US08592994B2

公开(公告)日：2013-11-26

申请号：US12517551

申请日：2007-12-05

Applicant: Kenya Tachibana ,  Masahiro Wada ,  Hitoshi Kawaguchi ,  Kensuke Nakamura

Inventor： Kenya Tachibana ,  Masahiro Wada ,  Hitoshi Kawaguchi ,  Kensuke Nakamura

IPC: H01L23/48

CPC classification number: H01L21/563 ,  C08L63/00 ,  H01L23/293 ,  H01L23/3735 ,  H01L23/3737 ,  H01L23/49822 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10253 ,  H05K1/0271 ,  H05K3/305 ,  H05K3/4602 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2201/10977 ,  H01L2924/00 ,  H01L2224/0401

Abstract: A flip-chip semiconductor package includes a circuit board having a core layer and at least one buildup layer, a semiconductor device connected to the circuit board through a metal bump, and a cured member that is made of a sealing resin composition and enclosed between the semiconductor device and the circuit board. The coefficient of linear expansion at 25 to 75° C. of the cured member is 15 to 35 ppm/° C., the glass transition temperature of at least one buildup layer is 170° C. or more, and the coefficient of linear expansion of at 25 to 75° C. of the at least one buildup layer in the planar direction is 25 ppm or less. A highly reliable flip-chip semiconductor package, buildup layer material, core layer material, and sealing resin composition can be provided by preventing cracks and inhibiting delamination.

Abstract translation: 倒装芯片半导体封装包括具有芯层和至少一个堆积层的电路板，通过金属凸块连接到电路板的半导体器件，以及由密封树脂组合物制成的封装在其间的固化构件 半导体器件和电路板。 固化部件的25〜75℃的线膨胀系数为15〜35ppm /℃，至少一层积层的玻璃化转变温度为170℃以上，线膨胀系数 在平面方向上的至少一个堆积层的25〜75℃为25ppm以下。 可以通过防止裂纹和抑制分层而提供高度可靠的倒装芯片半导体封装，堆积层材料，芯层材料和密封树脂组合物。

公开(公告)号：US08590145B2

公开(公告)日：2013-11-26

申请号：US12580537

申请日：2009-10-16

Applicant: Charles W. Eichelberger ,  James E. Kohl

Inventor： Charles W. Eichelberger ,  James E. Kohl

IPC: H05K3/30

CPC classification number: H05K3/30 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/29 ,  H01L23/3128 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L2221/68345 ,  H01L2223/6677 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/211 ,  H01L2224/24137 ,  H01L2224/2518 ,  H01L2224/96 ,  H01L2225/1035 ,  H01L2225/1058 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K1/0206 ,  H05K1/0218 ,  H05K1/185 ,  H05K3/4644 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/0733 ,  Y10T29/49121 ,  Y10T29/49124 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00

Abstract: Methods of fabricating a circuit structure are provided. The fabrication method includes: forming a chip layer, which includes obtaining at least one chip and disposing a structural material around and physically contacting the side surface(s) of each chip in the chip layer. The structural material has an upper surface substantially coplanar with or parallel to an upper surface of each chip and defines at least a portion of a front surface of the chip layer, and has a lower surface substantially coplanar with or parallel to a lower surface of each chip, which defines at least portion of a back surface of the chip layer. The method further includes forming at least one strengthening structure over the back surface of the chip layer. The strengthening structure is formed to strengthen an interface between the chip(s) and the structural material.

Abstract translation: 提供制造电路结构的方法。 制造方法包括：形成芯片层，其包括获得至少一个芯片并且在芯片层中的每个芯片的侧表面周围设置结构材料并物理接触芯片层。 结构材料具有与每个芯片的上表面基本上共面或平行的上表面，并且限定了芯片层的前表面的至少一部分，并且具有与每个芯片的下表面基本上共面或平行于下表面的下表面 芯片，其限定了芯片层的背表面的至少一部分。 该方法还包括在芯片层的背面上形成至少一个强化结构。 形成强化结构以加强芯片和结构材料之间的界面。

公开(公告)号：US08581406B1

公开(公告)日：2013-11-12

申请号：US13452114

申请日：2012-04-20

Applicant: James A. Robbins ,  William J. Davis ,  Robert B. Hallock

Inventor： James A. Robbins ,  William J. Davis ,  Robert B. Hallock

IPC: H01L23/48 ,  H01L29/76 ,  H01L23/10

CPC classification number: H01L23/48 ,  H01L21/563 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/16 ,  H01L2223/6683 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K2201/10166 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A MMIC flip chip mounted to a circuit board having an underfill material disposed between the MMIC and the circuit board and a barrier structure for preventing the underfill material from being disposed under an electronic device of the MMIC while providing a cavity under the electronic device.

Abstract translation: 安装在具有布置在MMIC和电路板之间的底部填充材料的电路板的MMIC倒装芯片以及用于防止底部填充材料设置在MMIC的电子设备下方的阻挡结构，同时在电子设备下方提供空腔。

公开(公告)号：US20130291378A1

公开(公告)日：2013-11-07

申请号：US13868413

申请日：2013-04-23

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Yoshitada HIGASHIZAWA ,  Kosuke KOBAYASHI ,  Yukinori HATAYAMA

IPC: H05K13/04 ,  H05K13/00

CPC classification number: H01L24/81 ,  B23K1/0004 ,  B23K1/0008 ,  B23K1/0016 ,  B23K1/008 ,  B23K1/203 ,  B23K3/082 ,  B23K2101/42 ,  H01L21/561 ,  H01L24/75 ,  H01L24/97 ,  H01L2224/13111 ,  H01L2224/16235 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/7501 ,  H01L2224/75251 ,  H01L2224/75252 ,  H01L2224/7565 ,  H01L2224/75753 ,  H01L2224/75841 ,  H01L2224/7598 ,  H01L2224/7901 ,  H01L2224/81011 ,  H01L2224/81024 ,  H01L2224/81097 ,  H01L2224/81098 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/812 ,  H01L2224/81203 ,  H01L2224/81801 ,  H01L2224/81815 ,  H01L2224/81986 ,  H01L2224/83 ,  H01L2224/83104 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/351 ,  H05K3/3494 ,  H05K13/0061 ,  H05K13/04 ,  H05K13/0465 ,  H05K2201/10515 ,  H05K2201/10674 ,  H05K2203/047 ,  H05K2203/1115 ,  Y10T29/4913 ,  Y10T29/53174 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2224/81 ,  H01L2924/01051 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00012

Abstract: An electronic component mounting device, includes a stage in which a plurality of stage portions are defined, a first heater provided in the plurality of stage portions respectively, and the first heater which can be controlled independently, a mounting head arranged over the stage, and a second heater provided in the mounting head.

Abstract translation: 一种电子部件安装装置，包括分别设置有多个台部的台阶，分别设置在多个台部的第一加热器和可独立控制的第一加热器，布置在台架上的安装头，以及 设置在安装头中的第二加热器。

公开(公告)号：US20130277843A1

公开(公告)日：2013-10-24

申请号：US13452114

申请日：2012-04-20

Applicant: James A. Robbins ,  William J. Davis ,  Robert B. Hallock

Inventor： James A. Robbins ,  William J. Davis ,  Robert B. Hallock

IPC: H01L23/52

CPC classification number: H01L23/48 ,  H01L21/563 ,  H01L23/49894 ,  H01L23/66 ,  H01L24/16 ,  H01L24/32 ,  H01L25/16 ,  H01L2223/6683 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/26145 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81815 ,  H01L2224/83104 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K2201/10166 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00

Abstract: A MMIC flip chip mounted to a circuit board having an underfill material disposed between the MMIC and the circuit board and a barrier structure for preventing the underfill material from being disposed under an electronic device of the MMIC while providing a cavity under the electronic device.

Abstract translation: 安装在具有布置在MMIC和电路板之间的底部填充材料的电路板的MMIC倒装芯片以及用于防止底部填充材料设置在MMIC的电子设备下方的阻挡结构，同时在电子设备下方提供空腔。

公开(公告)号：US20130257525A1

公开(公告)日：2013-10-03

申请号：US13436195

申请日：2012-03-30

Applicant: Stephen V. Kosonocky ,  Noah Sturcken

Inventor： Stephen V. Kosonocky ,  Noah Sturcken

IPC: G05F1/10 ,  H05K3/30

CPC classification number: H05K1/0262 ,  H01F41/041 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2924/15311 ,  H05K1/165 ,  H05K1/185 ,  H05K2201/1003 ,  H05K2201/10674 ,  Y10T29/4913

Abstract: Various circuit board voltage regulators and methods of making and using the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating at least one inductor in a circuit board and coupling a semiconductor chip to the circuit board. The at least one inductor is electrically coupled to the semiconductor chip. Regulator logic is electrically coupled to the at least one inductor, the regulator logic and the at least one inductor are operable to deliver a regulated voltage to the semiconductor chip.

Abstract translation: 公开了各种电路板电压调节器及其制造和使用方法。 一方面，提供一种制造方法，其包括在电路板中制造至少一个电感器并将半导体芯片耦合到电路板。 所述至少一个电感器电耦合到所述半导体芯片。 调节器逻辑电耦合到至少一个电感器，调节器逻辑和至少一个电感器可操作以将调节的电压传送到半导体芯片。

公开(公告)号：US08546700B2

公开(公告)日：2013-10-01

申请号：US13042686

申请日：2011-03-08

Applicant: Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

Inventor： Hiroshi Yamamoto ,  Toshitake Seki ,  Shinji Yuri ,  Masaki Muramatsu ,  Motohiko Sato ,  Kazuhiro Hayashi ,  Jun Otsuka ,  Manabu Sato

IPC: H05K1/16

CPC classification number: H01G4/232 ,  H01G4/30 ,  H01L23/49822 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H05K1/0231 ,  H05K1/112 ,  H05K1/185 ,  H05K3/4602 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2201/10712 ,  H01L2224/05599

Abstract: A capacitor comprising: a capacitor body including a plurality of laminated dielectric layers, a plurality of inner electrode layers which are respectively disposed between mutually adjacent ones of the dielectric layers, a first main surface located in a laminated direction of the dielectric layers, and a second main surface opposite to the first main surface; a first outer electrode formed on the first main surface of the capacitor body and electrically connected to the inner electrode layers; a second outer electrode formed on the second main surface of the capacitor body and electrically connected to the inner electrode layers; a first dummy electrode formed on the first main surface of the capacitor body; and a second dummy electrode formed on the second main surface of the capacitor body.

Abstract translation: 一种电容器，包括：电容器主体，包括多个叠层电介质层，多个内部电极层，分别设置在相互相邻的电介质层之间，第一主表面位于电介质层的层叠方向上， 第二主表面与第一主表面相对; 第一外电极，形成在所述电容器主体的所述第一主表面上并电连接到所述内电极层; 形成在所述电容器主体的所述第二主表面上并与内部电极层电连接的第二外部电极; 形成在所述电容器主体的所述第一主表面上的第一虚拟电极; 以及形成在电容器主体的第二主表面上的第二虚拟电极。