公开(公告)号：US20050205297A1

公开(公告)日：2005-09-22

申请号：US11142399

申请日：2005-06-02

Applicant: Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

Inventor： Tokihito Suwa ,  Haruo Akahoshi ,  Shingo Kumamoto

IPC: H05K1/09 ,  H01L21/4763 ,  H01L23/12 ,  H01L23/14 ,  H05K1/11 ,  H05K1/14 ,  H05K3/44 ,  H05K3/46

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/4641 ,  H05K2201/0338 ,  H05K2201/068 ,  H05K2201/093 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09627 ,  H05K2201/09663

Abstract: A multilayer circuit board including a laminate of at least one insulating layer and at least one wiring layer. The wiring layer is formed by a composite member having a first metal layer and a second metal layer formed on one or both sides of the first metal layer. The first metal layer having a smaller coefficient of thermal expansion than the second metal layer. The second metal layer having a higher electric conductivity than the first metal layer. The insulating layer has a blind via-hole with a bottom provided by a surface of the second metal layer. A layer-to-layer interconnection portion is provided on the surface of the insulating layer and in the blind via-hole and is formed in the blind via-hole to be in contact with the surface of the second metal layer.

Abstract translation: 包括至少一个绝缘层和至少一个布线层的叠层的多层电路板。 布线层由具有形成在第一金属层的一侧或两侧上的第一金属层和第二金属层的复合构件形成。 第一金属层的热膨胀系数小于第二金属层。 第二金属层的导电率比第一金属层高。 绝缘层具有通过第二金属层的表面设置的底部的盲通孔。 在绝缘层的表面和盲通孔中设置层间互连部，并且形成在盲通孔中，与第二金属层的表面接触。

公开(公告)号：US20050161255A1

公开(公告)日：2005-07-28

申请号：US11016156

申请日：2004-12-17

Applicant: Yoshifumi Takada

Inventor： Yoshifumi Takada

IPC: H05K1/02 ,  H05K1/11 ,  H05K3/34 ,  H05K3/42 ,  H05K3/46 ,  H05K7/06

CPC classification number: H05K1/115 ,  H05K1/114 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: In a multi-layer wiring board in which board wirings are arranged in a plurality of wiring layers so as to be connected via a through hole, two through holes are provided in parallel, and two through holes are connected therebetween in both end portions of the respective through holes or one end portion thereof by the wiring board.

Abstract translation: 在多层布线基板中，板布线布置在多个布线层中，以便通过通孔连接，两个通孔平行设置，并且两个通孔连接在它们之间的两端部 相应的通孔或其一个端部通过布线板。

公开(公告)号：US06922062B2

公开(公告)日：2005-07-26

申请号：US10335779

申请日：2003-01-02

Applicant: Aubrey K. Sparkman

Inventor： Aubrey K. Sparkman

IPC: G01R31/28 ,  H05K1/02 ,  G01R27/04

CPC classification number: G01R31/281 ,  H05K1/0237 ,  H05K1/0268 ,  H05K2201/09627 ,  H05K2201/09727

Abstract: Testing of a printed circuit board (PCB) impedance measurement region is performed using time domain reflectometry (TDR) that measures reflections and time delays of pulses injected into an impedance measurement region (impedance coupon). Timing markers are used to give both visual and electrical indications of precisely where the desired impedance measurement region (impedance coupon) begins and ends. The timing markers are placed on either end of the impedance coupon to be measured and give explicit start and end points to the PCB impedance measurement region. The timing markers may be in any form which has a discernable impedance difference from the PCB impedance measurement region.

Abstract translation: 印刷电路板（PCB）阻抗测量区域的测试使用时域反射测量（TDR）进行，其测量注入阻抗测量区域（阻抗试样）的脉冲的反射和时间延迟。 定时标记用于给出所需阻抗测量区域（阻抗试样）开始和结束的精确位置的视觉和电气指示。 定时标记放置在要测量的阻抗试样的任一端，给出PCB阻抗测量区域的明确的起始点和终点。 定时标记可以是与PCB阻抗测量区域具有可辨别的阻抗差异的任何形式。

公开(公告)号：US06916996B2

公开(公告)日：2005-07-12

申请号：US10605324

申请日：2003-09-23

Applicant: Chi-Kung Kuan ,  Chao-Cheng Lee ,  Kuan-Hua Lee

Inventor： Chi-Kung Kuan ,  Chao-Cheng Lee ,  Kuan-Hua Lee

IPC: H05K1/02 ,  H05K1/11 ,  H01R12/04

CPC classification number: H05K1/0245 ,  H05K1/115 ,  H05K2201/09245 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: A symmetric electrical connection system for balancing impedance between a first node and a third node and impedance between a second node and a fourth node. The system includes a first conducting wire, a third conducting wire, a fifth conducting wire, and a seventh conducting wire all installed in a first layer. The system further includes a second conducting wire, a fourth conducting wire, a sixth conducting wire, and an eighth conducting wire all installed in a second layer. The first conducting wire and the eighth conducting wire are crossed but electrically insulated. The second conducting wire and the third conducting wire are crossed but electrically insulated. The fourth conducting wire and the fifth conducting wire are crossed but electrically insulated. The sixth conducting wire and the seventh conducting wire are crossed but electrically insulated. In a preferred embodiment, the appearances and the materials of the conducting wires are essentially equivalent.

Abstract translation: 一种用于平衡第一节点和第三节点之间的阻抗的对称电连接系统以及第二节点和第四节点之间的阻抗。 该系统包括全部安装在第一层中的第一导线，第三导线，第五导线和第七导线。 该系统还包括全部安装在第二层中的第二导线，第四导线，第六导线和第八导线。 第一导线和第八导线交叉但电绝缘。 第二导线和第三导线是交叉但电绝缘的。 第四导线和第五导线交叉但电绝缘。 第六导线和第七导线交叉但电绝缘。 在优选实施例中，导线的外观和材料基本相同。

公开(公告)号：US06861834B2

公开(公告)日：2005-03-01

申请号：US09892850

申请日：2001-06-28

Applicant: James M. Kronrod ,  James J. Freeman ,  Kelly Coffey

Inventor： James M. Kronrod ,  James J. Freeman ,  Kelly Coffey

IPC: G01R1/20 ,  G01R19/165 ,  H05K1/02 ,  G01R27/28

CPC classification number: G01R19/16571 ,  G01R1/203 ,  H05K1/0268 ,  H05K2201/093 ,  H05K2201/09627

Abstract: A system for measuring power of a circuit on a printed circuit board (PCB) including first and second circuits, a power strip, a power plane, and a calibration strip. The power strip is connected to the power plane to the first circuit, is embedded in the PCB during the manufacturing process, and also has at least two vias for measuring a voltage drop. The calibration strip is also embedded in the PCB during the manufacturing process and has at least two vias for measuring a voltage drop. The second circuit is configured to measure a voltage drop across the power strip as a first voltage and a voltage drop across the calibration strip as a second voltage, and to calculate the power being fed to the first circuit based on the first voltage and the second voltage.

公开(公告)号：US20040264153A1

公开(公告)日：2004-12-30

申请号：US10603048

申请日：2003-06-24

Inventor： Jason J. Payne ,  Mark W. Gailus ,  Leon M. Khilchenko ,  Huilin Ren

IPC: H01R012/16

CPC classification number: H01R13/6477 ,  H01R12/714 ,  H01R13/514 ,  H01R13/6471 ,  H01R13/6587 ,  H05K1/0219 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/09381 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/10189

Abstract: In the preferred embodiment, there is disclosed a printed circuit board having a surface providing a mating interface to which is electrically connected an electrical connector having signal conductors and ground conductors. The printed circuit board includes a plurality of stacked dielectric layers, with a conductor disposed on at least one of the plurality of dielectric layers. The mating interface includes a plurality of conductive vias aligned in a plurality of rows, with the plurality of conductive vias extending through at least a portion of the plurality of dielectric layers, at least one of the plurality of conductive vias intersecting the conductor. The plurality of conductive vias includes signal conductor connecting conductive vias and ground conductor connecting conductive vias. For each of the plurality of rows of the conductive vias, there are at least twice as many ground conductor connecting conductive vias as signal conductor connecting conductive vias and the conductive vias are positioned relative to one another so that for each signal conductor connecting conductive via, there are ground conductor connecting conductive vias adjacent either side of the signal conductor connecting conductive via.

Abstract translation: 在优选实施例中，公开了一种印刷电路板，其具有提供配合接口的表面，电连接器具有信号导体和接地导体。 印刷电路板包括多个堆叠的电介质层，其中导体设置在多个电介质层中的至少一个上。 配合接口包括以多行排列的多个导电通孔，多个导电通孔延伸穿过多个电介质层的至少一部分，多个导电通孔中的至少一个与导体相交。 多个导电通孔包括连接导电通孔的信号导体和连接导电通孔的接地导体。 对于导电通孔的多行中的每一行，存在至少两倍的接地导体，其连接导电通孔，作为连接导电通孔的信号导体，并且导电通孔相对于彼此定位，使得对于连接导电通孔的每个信号导体， 有接地导体连接导电通孔，邻近信号导体的任一侧连接导电通孔。

公开(公告)号：US20040201094A1

公开(公告)日：2004-10-14

申请号：US10820799

申请日：2004-04-09

Inventor： Yusuke Sato ,  Kenji Koyama ,  Toshihiro Miura ,  Toshihiko Kyogoku

IPC: H01L023/02

CPC classification number: H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L25/16 ,  H01L25/165 ,  H01L2223/6655 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48195 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49111 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01037 ,  H01L2924/0105 ,  H01L2924/01058 ,  H01L2924/01061 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/12041 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H03F1/0205 ,  H03F1/0283 ,  H03F3/195 ,  H03F2200/111 ,  H03F2200/18 ,  H03F2200/408 ,  H03F2200/451 ,  H05K1/0263 ,  H05K1/115 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2203/049 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: An electrode on a main surface of a module board, to which an emitter electrode of a semiconductor chip which includes a switching element of a power supply control circuit that supplies a power supply voltage to amplifier circuit parts of a power module of a digital cellular phone, is electrically connected to a wiring in an internal layer of the module board through a plurality of via holes. Further, the wiring is electrically connected to an electrode for the supply of the power supply voltage, which is provided on a back surface of the module board. Accordingly, an output characteristic of the semiconductor device is improved.

Abstract translation: 模块板的主表面上的电极，半导体芯片的发射极电极包括电源控制电路的开关元件，电源控制电路将电源电压提供给数字蜂窝电话的电源模块的放大器电路部分 通过多个通孔电连接到模块板的内层中的布线。 此外，布线电连接到设置在模块板的背面上的用于提供电源电压的电极。 因此，提高了半导体器件的输出特性。

公开(公告)号：US20040196056A1

公开(公告)日：2004-10-07

申请号：US10805232

申请日：2004-03-22

Applicant: Broadcom Corporation

Inventor： James M. Kronrod

IPC: H01R004/66 ,  H01R013/648

CPC classification number: G01R1/203 ,  G01R19/16571 ,  H05K1/0268 ,  H05K2201/093 ,  H05K2201/09627

Abstract: System for measuring a thickness of a circuit component on a printed circuit board (PCB). The system includes a first circuit, a power plane, a power strip, a calibration strip, a temperature sensor, and a second circuit. The power plane is coupled to the first circuit. The power strip is for providing power to the power plane and is disposed in the PCB connected to the power plane. The power strip has at least two vias. The calibration strip has a predetermined width and is disposed in said PCB. The calibration strip has at least two vias for measuring a voltage drop. The temperature sensor is coupled to the calibration strip and configured to measuring a temperature of the calibration strip. The second circuit is coupled to the temperature sensor and configured to determine the thickness of the calibration strip based on at least the temperature of the calibration strip.

公开(公告)号：US20040188138A1

公开(公告)日：2004-09-30

申请号：US10395956

申请日：2003-03-24

Inventor： Torben Baras ,  Alan Michael Lyons ,  Carsten Metz

IPC: H05K001/11 ,  H01R012/04

CPC classification number: H05K1/0248 ,  H05K1/0216 ,  H05K1/0219 ,  H05K1/0251 ,  H05K3/429 ,  H05K2201/09254 ,  H05K2201/09263 ,  H05K2201/09627 ,  H05K2201/0979

Abstract: An apparatus is disclosed that substantially reduces or eliminates the resonance that occurs in vias that connect the layers of a printed circuit board by electrically coupling a first transmission line in a circuit board to a second transmission line in a circuit board by two electrical paths having substantially the same electrical length. The two electrical paths are created by connecting the first transmission line to a first via which is in turn connected to a second via having a second transmission line with a plurality of connecting electrical paths between the two vias. In one illustrative embodiment, electrical traces are used to connect the top of the first via to the top of the second via and the bottom of the first via to the bottom of the second via.

Abstract translation: 公开了一种装置，其基本上减少或消除了在通过将电路板中的第一传输线电连接到电路板中的第二传输线的通孔中连接印刷电路板的层的通孔中发生的谐振， 相同的电气长度。 通过将第一传输线连接到第一通孔而产生两个电路径，第一通孔又连接到第二通孔，第二通孔具有在两个通孔之间具有多个连接电路径的第二传输线。 在一个说明性实施例中，电迹线用于将第一通孔的顶部连接到第二通孔的顶部和第一通孔的底部到第二通孔的底部。

公开(公告)号：US20040182265A1

公开(公告)日：2004-09-23

申请号：US10787412

申请日：2004-02-27

Applicant: NGK SPARK PLUG CO., LTD.

Inventor： Hajime Saiki ,  Michitoshi Nakata

IPC: G03C005/18

CPC classification number: H05K1/115 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H01L2924/00

Abstract: A wiring substrate, in which a wiring stacked portion including a conductor layer and a resin layer is stacked on a principal face of a core substrate including a substantially cylindrical through hole conductor in a through hole extending therethrough and a filling material filling the hollow portion of said through hole, comprising: a cover-shaped conductor portion covering an end face of said through hole just over a principal face of said core substrate and connected to said through hole conductor; and an initial conductor layer provided in said wiring stacked portion and across at least one of said resin layer from sad cover-shaped conductor layer, wherein a connection portion composed of via conductors buried in said resin layer brings said cover-shaped conductor portion and said internal conductor layer into conduction, and said via conductors composing said connection portion are provided not above said through hole.

Abstract translation: 一种布线基板，其中包括导体层和树脂层的布线层叠部分堆叠在包括基本上圆柱形的通孔导体的芯基板的主面上，所述芯基板在穿过其中的通孔中填充填充材料， 所述通孔包括：覆盖所述通孔的端面刚好在所述芯基板的主面上并连接到所述通孔导体的盖状导体部分; 以及初始导体层，其设置在所述布线堆叠部分中，并且穿过所述树脂层中的至少一个与所述树脂层的凹陷形导体层，其中由埋入所述树脂层中的通孔导体构成的连接部分将所述盖状导体部分和所述 内部导体层导通，并且构成所述连接部的所述通路导体不设置在所述通孔的上方。