公开(公告)号：US20080009085A1

公开(公告)日：2008-01-10

申请号：US11550910

申请日：2006-10-19

Applicant: Jiun-Heng Wang

Inventor： Jiun-Heng Wang

IPC: H01L21/00

CPC classification number: G01R3/00 ,  G01R1/07314 ,  H05K3/202 ,  H05K3/205 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09481

Abstract: A method for manufacturing a probe card is provided. A first inactive layer, a first patterned photoresist layer and a first metal layer are sequentially formed on a substrate. The first metal layer has first through holes exposing a portion of the first patterned photoresist layer. A second inactive layer and a second patterned photoresist layer are sequentially formed thereon. The second patterned photoresist layer has second through holes exposing the first through holes. Pins are formed inside the first and the second through holes. A second metal layer is formed on the second patterned photoresist layer. One end of each pin is connected to the second metal layer. The pins and the second metal layer are taken out. A circuit carrier having third through holes is provided. The pins are inserted into the third through holes. The second metal layer is patterned to form pinheads.

Abstract translation: 提供一种制造探针卡的方法。 在衬底上依次形成第一非活性层，第一图案化光致抗蚀剂层和第一金属层。 第一金属层具有暴露第一图案化光致抗蚀剂层的一部分的第一通孔。 在其上依次形成第二非活性层和第二图案化光致抗蚀剂层。 第二图案化光致抗蚀剂层具有暴露第一通孔的第二通孔。 销形成在第一和第二通孔内。 在第二图案化光致抗蚀剂层上形成第二金属层。 每个引脚的一端连接到第二金属层。 销和第二金属层被取出。 提供具有第三通孔的电路载体。 引脚插入第三个通孔。 图案化第二金属层以形成针头。

公开(公告)号：US20080003402A1

公开(公告)日：2008-01-03

申请号：US11717587

申请日：2007-03-13

Applicant: Belgacem Haba ,  Yoichi Kubota ,  Teck-Gyu Kang ,  Jae Park

Inventor： Belgacem Haba ,  Yoichi Kubota ,  Teck-Gyu Kang ,  Jae Park

IPC: C23F1/00 ,  B32B7/00

CPC classification number: H01L24/14 ,  H01L21/4828 ,  H01L21/4853 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/11 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13099 ,  H01L2224/16225 ,  H01L2224/73203 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01084 ,  H01L2924/01322 ,  H01L2924/014 ,  H05K3/061 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2203/0369 ,  H05K2203/0597 ,  H05K2203/1476 ,  Y10T29/49126 ,  Y10T428/24174 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A method includes applying a final etch-resistant material to an in-process substrate so that the final etch-resistant material at least partially covers first microcontact portions integral with the substrate and projecting upwardly from a surface of the substrate, and etching the surface of the substrate so as to leave second microcontact portions below the first microcontact portions and integral therewith, the final etch-resistant material at least partially protecting the first microcontact portions from etching during the further etching step. A microelectronic unit includes a substrate, and a plurality of microcontacts projecting in a vertical direction from the substrate, each microcontact including a base region adjacent the substrate and a tip region remote from the substrate, each microcontact having a horizontal dimension which is a first function of vertical location in the base region and which is a second function of vertical location in the tip region.

Abstract translation: 一种方法包括将最终的耐蚀刻材料施加到工艺衬底，使得最终耐蚀刻材料至少部分地覆盖与衬底成一体的第一微接触部分并从衬底的表面向上突出，并且蚀刻表面 衬底，以便将第二微接触部分留在第一微接触部分下方并与之成一体，最后的抗蚀刻材料在另外的蚀刻步骤期间至少部分地保护第一微接触部分免受蚀刻。 微电子单元包括衬底以及从衬底沿垂直方向突出的多个微接点，每个微接触器包括邻近衬底的基极区域和远离衬底的尖端区域，每个微接触体具有作为第一功能的水平尺寸 在基部区域中垂直位置，并且其是尖端区域中垂直位置的第二函数。

公开(公告)号：US20070298629A1

公开(公告)日：2007-12-27

申请号：US11760020

申请日：2007-06-08

Applicant: TED JU

Inventor： TED JU

IPC: H01R12/14

CPC classification number: H01R13/2414 ,  H01R13/03 ,  H05K3/325 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/10734

Abstract: A conductive component capable of electrically connecting two objects is proposed. The conductive element includes an elastic body that is provided with at least two conductive particles therein. When the conductive component is pressed, a portion of the conductive particles protrudes from the elastic body, thereby forming an electrical connection with external electrical components. In comparison with the prior art, due to the elasticity of the elastic body of the present invention, the conductive component has better elasticity. The conductive particles in the elastic body can protrude from the through holes of the elastic body to connect electrically with the external electrical components. The conductive component of the present invention can assure the efficient electrical connection between the opposing electrical components. The present invention further provides an electrical connector and a chip module that also have the above-mentioned effect.

Abstract translation: 提出了能够电连接两个物体的导电部件。 导电元件包括​​在其中设置有至少两个导电颗粒的弹性体。 当按压导电部件时，导电粒子的一部分从弹性体突出，从而与外部电气部件形成电连接。 与现有技术相比，由于本发明的弹性体的弹性，导电成分具有更好的弹性。 弹性体中的导电颗粒可以从弹性体的通孔突出，以与外部电气部件电连接。 本发明的导电部件可以确保相对的电气部件之间的有效的电连接。 本发明还提供一种也具有上述效果的电连接器和芯片模块。

公开(公告)号：US20070295606A1

公开(公告)日：2007-12-27

申请号：US11850830

申请日：2007-09-06

Applicant: Roger Chang

Inventor： Roger Chang

IPC: C25D5/02

CPC classification number: H05K3/205 ,  C25D7/00 ,  H05K1/0393 ,  H05K3/064 ,  H05K3/386 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2203/0384 ,  H05K2203/1105

Abstract: A manufacturing process of an embedded type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the copper foil according to the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic layer and the organic layer is solidified.

Abstract translation: 嵌入式柔性或刚性印刷电路板的制造工艺包括多个步骤。 首先，将一层干膜施加到一层铜箔上。 然后通过光刻工艺在铜箔上形成电路图案。 根据电路图案，在铜箔上电镀蚀刻停止层。 然后用铜电镀蚀刻停止层。 去除干膜后，铜箔通过高温处理软化。 然后在用有机层涂覆之后蚀刻铜箔层，有机层固化。

公开(公告)号：US20070284738A1

公开(公告)日：2007-12-13

申请号：US11742159

申请日：2007-04-30

Applicant: Nozomi SHIMOISHIZAKA ,  Yoshifumi NAKAMURA

Inventor： Nozomi SHIMOISHIZAKA ,  Yoshifumi NAKAMURA

IPC: H01L23/12 ,  H01L21/60 ,  H05K1/00 ,  H05K3/10

CPC classification number: H05K3/4007 ,  H01L21/4853 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/12 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05155 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/11462 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/81192 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/243 ,  H05K3/244 ,  H05K3/328 ,  H05K3/386 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2203/0278 ,  H05K2203/0285 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A wiring board includes an insulating base; an adhesive layer formed on the surface of the insulating base; a conductor wiring formed on the surface of the adhesive layer; and a bump formed crossing the longitudinal direction of the conductor wiring over regions on the adhesive layer on both sides of the conductor wiring, wherein the back face at a part of the conductor wiring where the bump is formed, and the back faces and parts of the side faces of the bump formed above the regions of the adhesive layer on both sides of the conductor wiring, are embedded in the surface of the adhesive layer so as to be adhered to the adhesive layer. Even when the wiring width of the conductor wiring is decreased, the conductor wiring can be adhered to the wiring board firmly.

Abstract translation: 布线板包括绝缘基底; 形成在所述绝缘基材的表面上的粘合剂层; 形成在所述粘合剂层的表面上的导体布线; 以及在导体布线的两侧的粘合剂层上的区域上与导体布线的纵向交叉的凸块，其中形成有凸块的导体布线的一部分的背面以及背面和 形成在导体布线两侧的粘合剂层的区域之上的凸起的侧面嵌入粘合剂层的表面，从而粘附到粘合剂层上。 即使导体布线的布线宽度减小，导体布线也可以牢固地粘附在布线板上。

公开(公告)号：US07301781B2

公开(公告)日：2007-11-27

申请号：US11585159

申请日：2006-10-24

Applicant: Satoru Konishi ,  Tsuneo Endoh ,  Masaaki Tsuchiya ,  Hirokazu Nakajima

Inventor： Satoru Konishi ,  Tsuneo Endoh ,  Masaaki Tsuchiya ,  Hirokazu Nakajima

IPC: H05K7/02 ,  H05K7/06 ,  H05K7/08 ,  H05K7/10

CPC classification number: H05K3/303 ,  H01L23/3121 ,  H01L23/3677 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32013 ,  H01L2224/32225 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/83138 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06555 ,  H01L2225/06582 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/183 ,  H05K2201/0367 ,  H05K2201/09781 ,  H05K2201/10515 ,  H05K2201/2036 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/0401

Abstract: The present invention realizes strengthening of a ground of a lower-surface ground electrode of an upper semiconductor chip and miniaturization in a semiconductor module on which two semiconductor chips are mounted in a stacked manner. A lower semiconductor chip is fixed to a bottom of a recess formed in an upper surface of a module board, and an upper semiconductor chip is fixed to an upper surface of a support body made of conductor which is formed over the upper surface of the module board around the recess. External electrode terminals and a heat radiation pad are formed over a lower surface of the module board.

Abstract translation: 本发明实现了以半导体模块中的上半导体芯片的下表面接地电极的接地强化和半导体模块的小型化，其中以半导体芯片堆叠的方式安装两个半导体芯片。 下半导体芯片固定在形成在模块板的上表面中的凹部的底部，并且上半导体芯片固定到由导体制成的支撑体的上表面，导体的上表面形成在模块的上表面上 在休息室周围。 外部电极端子和散热垫形成在模块板的下表面上。

公开(公告)号：US20070267218A1

公开(公告)日：2007-11-22

申请号：US11741857

申请日：2007-04-30

Applicant: Masahiro Kimura ,  Yoshifumi Saito

Inventor： Masahiro Kimura ,  Yoshifumi Saito

IPC: H01L23/28

CPC classification number: H01L23/49816 ,  H01L21/4853 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24226 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1532 ,  H01L2924/15787 ,  H01L2924/19041 ,  H01L2924/19106 ,  H05K1/0306 ,  H05K1/111 ,  H05K1/183 ,  H05K3/245 ,  H05K3/28 ,  H05K3/284 ,  H05K3/3421 ,  H05K3/4007 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/096 ,  H05K2203/308 ,  Y02P70/611 ,  Y10T29/49002 ,  H01L2924/00

Abstract: A multilayer electronic component having a ceramic substrate and a resin layer mounted on a mounting substrate. Recess portions are formed at an outside-facing major surface side of the resin layer. In the resin layer, columnar conductors are disposed so that axis line directions thereof are aligned in a thickness direction of the resin layer. End portions of the columnar conductors are located inside the recess portions further from opening faces thereof and have end surfaces exposed in the recess portions. When a multilayer electronic component is mounted on a mounting substrate, solder is provided on the end surfaces of the columnar conductors in the recess portions. The thickness of solder used in the above mounting does not interfere with a reduction in size and height of an electronic device that includes the above multilayer electronic component.

Abstract translation: 一种具有陶瓷基板和安装在安装基板上的树脂层的多层电子部件。 在树脂层的面向外的主表面侧形成凹部。 在树脂层中，柱状导体设置成使其轴线方向在树脂层的厚度方向上排列。 柱状导体的端部位于比其开口面更远的凹部内侧，具有露出于凹部的端面。 当将多层电子部件安装在安装基板上时，在凹部中的柱状导体的端面上设置焊料。 在上述安装中使用的焊料的厚度不会妨碍包括上述多层电子部件的电子设备的尺寸和高度的减小。

公开(公告)号：US07297572B2

公开(公告)日：2007-11-20

申请号：US10702235

申请日：2003-11-05

Applicant: Peter C. Salmon

Inventor： Peter C. Salmon

IPC: H01I21/00

CPC classification number: H05K3/363 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5387 ,  H01L24/16 ,  H01L24/81 ,  H01L2221/68345 ,  H01L2224/05573 ,  H01L2224/11332 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13144 ,  H01L2224/16237 ,  H01L2224/45144 ,  H01L2224/81052 ,  H01L2224/81191 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01L2924/3651 ,  H05K1/0289 ,  H05K1/115 ,  H05K3/007 ,  H05K3/3436 ,  H05K3/3484 ,  H05K3/4015 ,  H05K3/4682 ,  H05K2201/0367 ,  H05K2201/0379 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/10674 ,  H05K2203/016 ,  H05K2203/0568 ,  Y02P70/613 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2224/05599

Abstract: This specification describes techniques for manufacturing an electronic system module. The module includes flexible multi-layer interconnection circuits with trace widths as narrow as 5 microns or less. A glass panel manufacturing facility, similar to those employed for making liquid crystal display, LCD, panels is preferably used to fabricate the interconnection circuits. A multi-layer interconnection circuit is fabricated on the glass panel using a release layer. A special assembly layer is formed over the interconnection circuit comprising a thick dielectric layer with openings formed at input/output (I/O) pad locations. Solder paste is deposited in the openings using a squeegee to form wells filled with solder. IC chips are provided with gold stud bumps at I/O pad locations, and these bumps are inserted in the wells to form flip chip connections. The IC chips are tested and reworked. The same bump/well connections can be used to attach fine-pitch cables. Module packaging layers are provided for hermetic sealing and for electromagnetic shielding. A blade server or supercomputer embodiment is also described.

Abstract translation: 本说明书描述了用于制造电子系统模块的技术。 该模块包括具有窄至5微米或更小的迹线宽度的柔性多层互连电路。 与用于制造液晶显示器，LCD，面板的玻璃面板制造设备相似，优选地用于制造互连电路。 使用剥离层在玻璃面板上制造多层互连电路。 在互连电路上形成特殊的组装层，该电路包括在输入/输出（I / O）焊盘位置处形成有开口的厚电介质层。 使用刮刀将焊膏沉积在开口中以形成填充有焊料的孔。 IC芯片在I / O焊盘位置处设有金柱凸起，并且这些凸块插入孔中以形成倒装芯片连接。 IC芯片经过测试和返工。 相同的凹凸/连接可用于连接细间距电缆。 提供模块封装层用于密封和电磁屏蔽。 还描述了刀片服务器或超级计算机实施例。

公开(公告)号：US07297285B2

公开(公告)日：2007-11-20

申请号：US11197332

申请日：2005-08-05

Applicant: Roger Chang

Inventor： Roger Chang

IPC: H01B13/00

CPC classification number: H05K3/205 ,  H05K1/0393 ,  H05K3/064 ,  H05K3/386 ,  H05K3/4007 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2203/0384 ,  H05K2203/1105

Abstract: A manufacturing process of an emboss type flexible or rigid printed circuit board includes multiple steps. First, a layer of dry film is applied to a layer of copper foil. Then a circuit pattern is formed on the copper foil through photolithography processes. An etching stop layer is electroplated on the circuit pattern. The etching stop layer is then electroplated with copper. The copper foil is softened by a high temperature process after removing the dry film. Then the layer of the copper foil is etched after coating with an organic surface layer and the organic surface layer is solidified.

Abstract translation: 压花型柔性或刚性印刷电路板的制造方法包括多个步骤。 首先，将一层干膜施加到一层铜箔上。 然后通过光刻工艺在铜箔上形成电路图案。 蚀刻停止层电镀在电路图案上。 然后用铜电镀蚀刻停止层。 去除干膜后，铜箔通过高温处理软化。 然后在涂覆有机表面层之后蚀刻铜箔层，并且有机表面层固化。

公开(公告)号：US07294532B2

公开(公告)日：2007-11-13

申请号：US11146610

申请日：2005-06-07

Applicant: Hiroyuki Imamura ,  Nobuyuki Koutani

Inventor： Hiroyuki Imamura ,  Nobuyuki Koutani

IPC: H01L21/44

CPC classification number: H01L21/4853 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/4985 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/83192 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/3025 ,  H05K1/111 ,  H05K3/243 ,  H05K2201/0367 ,  H05K2201/09727 ,  H05K2201/098 ,  H05K2201/0989 ,  H05K2201/10674 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599

Abstract: A method for manufacturing a semiconductor device that includes mounting a semiconductor chip on a circuit board having an insulating substrate, a plurality of wiring layers arranged on the insulating substrate, and bumps formed on the wiring layers respectively, in which the bump is provided across a longitudinal direction of a corresponding one of the wiring layers so as to extend over regions on both sides of the wiring layer and contact a surface of the insulating substrate, without a stepped portion formed on a surface of the bump, and a cross sectional shape of the bump taken in a width direction of the wiring layer is such that a central portion is higher than both side portions. The method also includes connecting electrode pads of the semiconductor chip to the bumps, thereby achieving connection between the electrode pads of the semiconductor chip and the wiring layers via the bumps.

Abstract translation: 一种半导体器件的制造方法，其包括将半导体芯片安装在具有绝缘基板的电路板上，布置在所述绝缘基板上的多个布线层以及分别形成在所述布线层上的凸块， 相对应的一个布线层的纵向方向延伸到布线层的两侧的区域上并与绝缘基板的表面接触，而不形成在凸起的表面上的阶梯部分，并且横截面形状 在布线层的宽度方向上取得的隆起部使得中央部高于两侧部。 该方法还包括将半导体芯片的电极焊盘连接到凸块，从而通过凸块实现半导体芯片的电极焊盘与布线层之间的连接。