公开(公告)号：US20100052145A1

公开(公告)日：2010-03-04

申请号：US12616453

申请日：2009-11-11

Applicant: Phillip Celaya ,  James P. Letterman, JR.

Inventor： Phillip Celaya ,  James P. Letterman, JR.

IPC: H01L23/498

CPC classification number: H01L23/3107 ,  H01L23/57 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H05K1/0275 ,  H05K1/181 ,  H05K2201/09781 ,  H05K2201/10689 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In one embodiment, a semiconductor package is formed to include a tamper barrier that is positioned between at least a portion of the connection terminals of the semiconductor package and an edge of the semiconductor package.

Abstract translation: 在一个实施例中，半导体封装被形成为包括位于半导体封装的至少一部分连接端子与半导体封装的边缘之间的防盗屏障。

公开(公告)号：US07670672B2

公开(公告)日：2010-03-02

申请号：US12265984

申请日：2008-11-06

Applicant: Yuichi Iida

Inventor： Yuichi Iida

IPC: H05K3/46

CPC classification number: H05K1/183 ,  H01L21/4807 ,  H01L23/053 ,  H01L23/15 ,  H01L23/49822 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01012 ,  H01L2924/09701 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15787 ,  H05K1/0306 ,  H05K3/4626 ,  H05K3/4629 ,  H05K3/4697 ,  H05K2201/0195 ,  H05K2201/09781 ,  H05K2203/063 ,  H05K2203/308 ,  Y10T428/24917 ,  Y10T428/24926 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: In a multilayer ceramic substrate having a cavity, base-material layers are arranged on a base side with respect to an interface between the base and a wall defining a cavity, and a constraining interlayer is arranged on the wall side. A conductive film is arranged between the base-material layers and the constraining interlayer, the base-material layers and the constraining interlayer sandwiching the interface. The effect of the first conductive film results in an increase in the adhesion of the constraining interlayer to the substrate layers, thus enhancing a shrinkage-inhibiting effect of the constraining interlayer.

Abstract translation: 在具有空腔的多层陶瓷基板中，基材层相对于基部和限定空腔的壁之间的界面布置在基底侧，并且约束夹层布置在壁侧。 导电膜布置在基材层与约束夹层之间，基材层和约束层间夹持界面。 第一导电膜的效果导致约束夹层对基材层的粘附性的增加，从而提高约束夹层的收缩抑制效果。

公开(公告)号：US20100038117A1

公开(公告)日：2010-02-18

申请号：US12507551

申请日：2009-07-22

Applicant: Yechung CHUNG ,  Chulwoo Kim ,  Eunseok Song ,  Kyoungsei Choi

Inventor： Yechung CHUNG ,  Chulwoo Kim ,  Eunseok Song ,  Kyoungsei Choi

IPC: H05K1/02

CPC classification number: H05K1/0216 ,  H01L23/4985 ,  H01L24/17 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/00014 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/351 ,  H05K1/114 ,  H05K1/189 ,  H05K2201/093 ,  H05K2201/09318 ,  H05K2201/09663 ,  H05K2201/09772 ,  H05K2201/09781 ,  H05K2201/10674 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, the chip mounting area further including an inner area and a peripheral area, the film further including a lower surface, and vias penetrating the film, the vias being located in the inner area, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film. Example embodiments are directed to a tape wiring substrate including a film having an upper surface including a chip mounting area, a lower surface, and vias penetrating the film, an upper metal layer on the upper surface of the film and connected to electrode bumps of a semiconductor chip, and a lower metal layer on the lower surface of the film, the vias being located outside of the chip mounting area. Example embodiments are directed to packages including tape wiring substrates.

Abstract translation: 示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域的上表面的膜，所述芯片安装区域还包括内部区域和周边区域，所述膜还包括下表面，以及穿透所述膜的通孔， 所述通孔位于所述内部区域中，所述膜的上表面上的上金属层连接到半导体芯片的电极凸块，并且在所述膜的下表面上的下金属层。 示例性实施例涉及一种带状布线基板，其包括具有包括芯片安装区域，下表面和通孔的通孔的上表面的膜，在膜的上表面上的上金属层，并连接到膜的电极凸块 半导体芯片以及下部金属层，通孔位于芯片安装区域的外侧。 示例性实施例涉及包括带布线基板的封装。

公开(公告)号：US07661191B2

公开(公告)日：2010-02-16

申请号：US10598469

申请日：2005-02-24

Applicant: Takeshi Nakamura ,  Katsumi Ito

Inventor： Takeshi Nakamura ,  Katsumi Ito

IPC: H01K3/10

CPC classification number: H05K3/4679 ,  H01L2224/16225 ,  H01L2924/19105 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/0032 ,  H05K3/0035 ,  H05K3/064 ,  H05K3/429 ,  H05K3/4652 ,  H05K2201/0394 ,  H05K2201/09063 ,  H05K2201/09536 ,  H05K2201/09563 ,  H05K2201/09781 ,  H05K2203/0554 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165

Abstract: A manufacturing method of a multilayer substrate that suppresses relative displacement of layers and forms interconnecting portions electrically connecting layers having an accurate positioning. A manufacturing method of a multilayer substrate for laminating, via an insulating film, a wiring layer formed by patterning a conductive film comprises providing a positioning hole in a conductive film laminated at the beginning and patterning a second and/or any subsequent wiring layers after identifying a position of an identification section. Interconnecting sections for interconnecting wiring layers are formed using the identification section.

Abstract translation: 一种抑制层的相对位移的多层基板的制造方法，形成具有精确定位的电连接层的互连部。 一种多层基板的制造方法，其特征在于，通过绝缘膜将通过图案形成导电膜形成的布线层层叠在一起，在开始时形成层叠的导电膜的定位孔，并且在识别出第二和/ 识别部分的位置。 用于互连布线层的互连部分使用识别部分形成。

公开(公告)号：US07659605B2

公开(公告)日：2010-02-09

申请号：US12232883

申请日：2008-09-25

Applicant: Yasuto Ishimaru ,  Hirofumi Ebe

Inventor： Yasuto Ishimaru ,  Hirofumi Ebe

IPC: H01L23/495

CPC classification number: H05K1/111 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/056 ,  H05K1/189 ,  H05K2201/09709 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/1545 ,  Y02P70/611 ,  H01L2924/00

Abstract: A COF board includes an insulating layer, and a terminal portion formed on the insulating layer. The terminal portion includes a first lead extending in a longitudinal direction, and a second lead extending in the longitudinal direction, and having a smaller length in the longitudinal direction than a length of the first lead in the longitudinal direction. The first leads are arranged in spaced-apart relation in a direction perpendicular to the longitudinal direction. The second leads are arranged in the direction perpendicular to the longitudinal direction to be interposed between the mutually adjacent first leads such that, when the mutually adjacent first leads are projected in an adjacent direction thereof, overlap portions where the second leads overlap with the first leads and non-overlap portions where the second leads do not overlap with the first leads are formed. Dummy leads are provided at the non-overlap portions.

Abstract translation: COF板包括绝缘层和形成在绝缘层上的端子部分。 端子部分包括沿纵向方向延伸的第一引线和沿纵向方向延伸的第二引线，并且在纵向方向上的长度比第一引线在纵向方向上的长度更小。 第一引线在垂直于纵向方向的方向上以间隔的关系布置。 第二引线沿垂直于纵向方向的方向布置以插入在相互相邻的第一引线之间，使得当相互相邻的第一引线沿其相邻方向突出时，第二引线与第一引线重叠的重叠部分 并且形成第二引线不与第一引线重叠的非重叠部分。 在非重叠部分提供虚拟引线。

公开(公告)号：US20100027291A1

公开(公告)日：2010-02-04

申请号：US12527336

申请日：2007-10-10

Applicant: Tetsuya Hamada

Inventor： Tetsuya Hamada

IPC: F21V7/22

CPC classification number: G02B6/0073 ,  G02B6/0068 ,  G02B6/0083 ,  G02B6/0085 ,  G02F1/133615 ,  H05K1/0209 ,  H05K1/189 ,  H05K3/28 ,  H05K3/321 ,  H05K2201/09363 ,  H05K2201/09781 ,  H05K2201/10106 ,  H05K2201/10969 ,  H05K2201/2054

Abstract: Electrode terminals (33a, 33b) of an LED (3) and a mounting wiring (42) of an FPC (4) are bonded by using a conductive adhesive, and a metal slug (31) of the LED (3) and a heat dissipation wiring (43) of the FPC (4) are bonded by using the conductive adhesive. The heat dissipation wiring (43) corresponds to each of the LEDs (3) and isolates the LEDs one from the other, not to permitting electricity to be carried between them.

Abstract translation: LED（3）的电极端子（33a，33b）和FPC（4）的安装布线（42）通过使用导电粘合剂和LED（3）的金属块（31）和热 通过使用导电粘合剂将FPC（4）的耗散布线（43）接合。 散热布线（43）对应于每个LED（3），并且将LED彼此隔离，而不允许在它们之间承载电力。

公开(公告)号：US20100012356A1

公开(公告)日：2010-01-21

申请号：US12464441

申请日：2009-05-12

Applicant: Kenji Hasegawa

Inventor： Kenji Hasegawa

IPC: H05K1/02

CPC classification number: H05K1/0268 ,  H05K1/0269 ,  H05K3/0008 ,  H05K3/1216 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/093 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09918 ,  H05K2201/2072

Abstract: According to one embodiment, a printed wiring board comprises an insulating substrate having a mounting surface, a recognition mark formed on the mounting surface of the insulating substrate, and a plurality of reinforcing patterns formed on the mounting surface of the insulating substrate. The reinforcing patterns extend from an outer periphery of the recognition mark toward outside of the recognition mark and are arranged circumferentially at intervals relative to the recognition mark. Each of the reinforcing patterns has a width less than a width of a part of the outer periphery of the recognition mark connecting adjacent ones of the reinforcing patterns.

Abstract translation: 根据一个实施例，印刷布线板包括具有安装表面的绝缘基板，形成在绝缘基板的安装表面上的识别标记以及形成在绝缘基板的安装表面上的多个加强图案。 加强图案从识别标记的外周延伸到识别标记的外侧，并相对于识别标记以周期方式布置。 每个加强图案的宽度小于连接相邻的加强图案的识别标记的外周的一部分的宽度。

公开(公告)号：US20100000767A1

公开(公告)日：2010-01-07

申请号：US12458936

申请日：2009-07-28

Applicant: Na-Rae Shin ,  Dong-Han Kim

Inventor： Na-Rae Shin ,  Dong-Han Kim

IPC: H05K1/00

CPC classification number: H05K1/0271 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0393 ,  H05K1/118 ,  H05K2201/0969 ,  H05K2201/09727 ,  H05K2201/09781 ,  H01L2924/00

Abstract: A TAB tape for a tape carrier package may have at least one opening formed in a connection portion. The at least one opening may be provided in the connection portion and a portion of the corresponding second lead. The at least one opening may be arranged near a boundary between the corresponding first lead and the connection portion. The at least one opening may be sized to reduce the change of the lead width from the first lead to the second lead.

Abstract translation: 用于带载包装的TAB带可以具有形成在连接部分中的至少一个开口。 所述至少一个开口可以设置在连接部分和对应的第二引线的一部分中。 至少一个开口可以布置在相应的第一引线和连接部分之间的边界附近。 所述至少一个开口的尺寸可被设计成减小引线宽度从第一引线到第二引线的变化。

公开(公告)号：US20090321750A1

公开(公告)日：2009-12-31

申请号：US12494254

申请日：2009-06-29

Applicant: Kaori NAMIOKA

Inventor： Kaori NAMIOKA

IPC: H01L33/00

CPC classification number: H01L33/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/094 ,  H05K2201/09781 ,  H05K2201/10106 ,  H05K2201/10727 ,  Y02P70/613 ,  H01L2924/00014

Abstract: The disclosed subject matter is directed to a reliable surface mount device using a ceramic package, and includes LED devices that are simply composed and incorporate the use of the surface mount device. The surface mount device can include a ceramic package, a semiconductor optical chip mounted in the package, two soldering pads electrically connected to the chip electrodes and at least one dummy soldering pad located on either side of the soldering pads. Thermal fatigue located at or in the soldering connections connecting the chip electrodes to a mounting board can be reduced because the distance between the soldering pads can be reduced. The dummy soldering pad that is electrically insulated can allow the device to maintain a desirable location with poise during the reflow soldering process that occurs during manufacture, and can also reduce shear stress present at the soldering connections. Thus, the surface mount device and the LED device using the disclosed structure can maintain a high reliability even under harsh environmental conditions.

Abstract translation: 所公开的主题涉及使用陶瓷封装的可靠的表面贴装器件，并且包括简单组合并结合使用表面贴装器件的LED器件。 表面安装器件可以包括陶瓷封装，安装在封装中的半导体光学芯片，与芯片电极电连接的两个焊盘和位于焊盘两侧的至少一个虚拟焊盘。 可以减少位于连接芯片电极到安装板的焊接连接处或其中的热疲劳，因为可以减小焊盘之间的距离。 电绝缘的虚拟焊盘可以允许器件在制造期间发生的回流焊接过程期间保持理想的位置，并且还可以减少焊接连接处存在的剪切应力。 因此，即使在恶劣的环境条件下，使用所公开结构的表面安装器件和LED器件也能保持高的可靠性。

公开(公告)号：US20090321120A1

公开(公告)日：2009-12-31

申请号：US12495507

申请日：2009-06-30

Applicant: Syuji HIRAMOTO ,  Norihiro ISHII

Inventor： Syuji HIRAMOTO ,  Norihiro ISHII

IPC: H05K1/18

CPC classification number: H05K1/111 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/10175 ,  H01L2224/812 ,  H01L2224/81801 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01079 ,  H05K1/0268 ,  H05K3/3442 ,  H05K3/3484 ,  H05K2201/09781 ,  H05K2201/10674 ,  H05K2203/042 ,  H05K2203/0545 ,  Y02P70/611 ,  H01L2224/05599

Abstract: A printed circuit board according to the present invention includes a printed wiring board, first electrodes, second electrodes, third electrodes, solders, and a flip chip. The printed wiring board includes a first surface and a second surface which is opposite the first surface. The first electrodes are respectively formed on the first surface. The second electrodes correspond to and are disposed near each of the first electrodes, and are respectively formed on the first surface. The third electrodes electrically respectively connect the first electrodes and the second electrodes corresponding to each of the first electrodes. The solders are applied so as to respectively cover the first electrodes, the second electrodes corresponding to the first electrodes, and the third electrodes connecting the first electrodes and the second electrodes. The flip chip is electrically connected to each of the first electrodes at a position opposed to the first electrodes.

Abstract translation: 根据本发明的印刷电路板包括印刷线路板，第一电极，第二电极，第三电极，焊料和倒装芯片。 印刷电路板包括与第一表面相对的第一表面和第二表面。 第一电极分别形成在第一表面上。 第二电极对应于并设置在每个第一电极附近，分别形成在第一表面上。 第三电极分别电连接与第一电极对应的第一电极和第二电极。 施加焊料以分别覆盖第一电极，对应于第一电极的第二电极以及连接第一电极和第二电极的第三电极。 倒装芯片在与第一电极相对的位置处电连接到每个第一电极。